diff options
| author | Richard Henderson <rth@redhat.com> | 2018-10-05 11:41:41 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2018-10-05 11:41:42 +0900 |
| commit | 07f5f4c683879e844d20d0d4963bbaf1b7cd47b9 (patch) | |
| tree | 872d6d64ac1dd790d76b214c2f7ae0150d51bdbb /sim/or1k/cpu.h | |
| parent | c8e98e3692cec125b92c995d8f881d9bdf1fac00 (diff) | |
| download | gdb-07f5f4c683879e844d20d0d4963bbaf1b7cd47b9.zip gdb-07f5f4c683879e844d20d0d4963bbaf1b7cd47b9.tar.gz gdb-07f5f4c683879e844d20d0d4963bbaf1b7cd47b9.tar.bz2 | |
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
Diffstat (limited to 'sim/or1k/cpu.h')
| -rw-r--r-- | sim/or1k/cpu.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h index 9646c33..b847f53 100644 --- a/sim/or1k/cpu.h +++ b/sim/or1k/cpu.h @@ -4516,6 +4516,10 @@ union sem_fields { IADDR i_disp26; } sfmt_l_j; struct { /* */ + IADDR i_disp21; + UINT f_r1; + } sfmt_l_adrp; + struct { /* */ UINT f_r1; UINT f_r2; UINT f_uimm6; @@ -4614,6 +4618,17 @@ struct scache { f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc)); \ +#define EXTRACT_IFMT_L_ADRP_VARS \ + UINT f_opcode; \ + UINT f_r1; \ + USI f_disp21; \ + unsigned int length; +#define EXTRACT_IFMT_L_ADRP_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13)); \ + #define EXTRACT_IFMT_L_JR_VARS \ UINT f_opcode; \ UINT f_resv_25_10; \ @@ -4831,6 +4846,23 @@ struct scache { f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \ f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ +#define EXTRACT_IFMT_L_MULD_VARS \ + UINT f_opcode; \ + UINT f_resv_25_5; \ + UINT f_r2; \ + UINT f_r3; \ + UINT f_resv_10_7; \ + UINT f_op_3_4; \ + unsigned int length; +#define EXTRACT_IFMT_L_MULD_CODE \ + length = 4; \ + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \ + f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \ + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \ + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \ + f_resv_10_7 = EXTRACT_LSB0_UINT (insn, 32, 10, 7); \ + f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \ + #define EXTRACT_IFMT_L_EXTHS_VARS \ UINT f_opcode; \ UINT f_r1; \ |