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| author | Joyce Janczyn <janczyn@cygnus> | 1998-03-25 17:10:01 +0000 |
|---|---|---|
| committer | Joyce Janczyn <janczyn@cygnus> | 1998-03-25 17:10:01 +0000 |
| commit | 52ef605e6df09807012c82ca104c0cd49c4e0542 (patch) | |
| tree | fb7f6739f0cf0eda7e6d82c09e805fc650c78735 /sim/mn10300 | |
| parent | bd5eafcd7c35f523ddbd734c5465d97e15702694 (diff) | |
| download | gdb-52ef605e6df09807012c82ca104c0cd49c4e0542.zip gdb-52ef605e6df09807012c82ca104c0cd49c4e0542.tar.gz gdb-52ef605e6df09807012c82ca104c0cd49c4e0542.tar.bz2 | |
* simops.c (OP_F0FD): Initialise variable 'sp' for rti instruction.
Diffstat (limited to 'sim/mn10300')
| -rw-r--r-- | sim/mn10300/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/mn10300/simops.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 700ca36..7e70336 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,3 +1,7 @@ +Wed Mar 25 12:08:00 1998 Joyce Janczyn <janczyn@cygnus.com> + + * simops.c (OP_F0FD): Initialise variable 'sp'. + Thu Mar 26 00:21:32 1998 Andrew Cagney <cagney@b1.cygnus.com> * dv-mn103int.c (decode_group): A group register every 4 bytes not diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index c6b1448..aaf7f48 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -2846,6 +2846,7 @@ void OP_F0FD (insn, extension) { unsigned int sp, next_pc; + sp = State.regs[REG_SP]; PSW = State.mem[sp] | (State.mem[sp + 1] << 8); State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8) | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24)); |