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authorIan Lance Taylor <ian@airs.com>1996-09-19 22:52:26 +0000
committerIan Lance Taylor <ian@airs.com>1996-09-19 22:52:26 +0000
commitc05d17211ee207282e7a8a397a2ee39d798dc708 (patch)
treee887a7efa730eaa2b92f8ac0210a6419346ccf19 /sim/mips
parent47c6ce6c2de14635d0d71d63e5dbea036084b6ec (diff)
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* interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
It's OK to have a mult follow a mult. What's not OK is to have a mult follow an mfhi.
Diffstat (limited to 'sim/mips')
-rw-r--r--sim/mips/ChangeLog4
-rw-r--r--sim/mips/interp.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index aed2073..49060fa 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,9 @@
Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
+ * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
+ It's OK to have a mult follow a mult. What's not OK is to have a
+ mult follow an mfhi.
+
* gencode.c (process_instructions): Correct handling of nor
instruction. Correct shift count for 32 bit shift instructions.
Correct sign extension for arithmetic shifts to not shift the
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index c5fdaeb..9c47b4a 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -361,10 +361,6 @@ static ut_reg HLPC = 0;
#define CHECKHILO(s) {\
if ((HIACCESS != 0) || (LOACCESS != 0))\
sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
- /* Set the access counts, since we are about\
- to update the HI and LO registers: */\
- HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
- HLPC = PC;\
}
/* NOTE: We keep the following status flags as bit values (1 for true,