diff options
| author | Chris Demetriou <cgd@google.com> | 2002-02-11 22:49:45 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2002-02-11 22:49:45 +0000 |
| commit | 9805e2294e532cc7df718b84cbcdd0d300ac861e (patch) | |
| tree | 5087ca46479593f31ef6ab974bd878648dde74a4 /sim/mips | |
| parent | d434e5742847f0e861b272d98dc05175e3557d51 (diff) | |
| download | gdb-9805e2294e532cc7df718b84cbcdd0d300ac861e.zip gdb-9805e2294e532cc7df718b84cbcdd0d300ac861e.tar.gz gdb-9805e2294e532cc7df718b84cbcdd0d300ac861e.tar.bz2 | |
2002-02-11 Chris Demetriou <cgd@broadcom.com>
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
Diffstat (limited to 'sim/mips')
| -rw-r--r-- | sim/mips/ChangeLog | 8 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 13 |
2 files changed, 14 insertions, 7 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 548f1cc..e7d21dc 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,11 @@ +2002-02-11 Chris Demetriou <cgd@broadcom.com> + + * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment + indicating that ALU32_END or ALU64_END are there to check + for overflow. + (DADD): Likewise, but also remove previous comment about + overflow checking. + 2002-02-10 Chris Demetriou <cgd@broadcom.com> * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 4511d17..6576b77 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -237,7 +237,7 @@ { ALU32_BEGIN (GPR[RS]); ALU32_ADD (GPR[RT]); - ALU32_END (GPR[RD]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RD]); } @@ -255,7 +255,7 @@ { ALU32_BEGIN (GPR[RS]); ALU32_ADD (EXTEND16 (IMMEDIATE)); - ALU32_END (GPR[RT]); + ALU32_END (GPR[RT]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RT]); } @@ -709,12 +709,11 @@ *vr4100: *vr5000: { - /* this check's for overflow */ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); { ALU64_BEGIN (GPR[RS]); ALU64_ADD (GPR[RT]); - ALU64_END (GPR[RD]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RD]); } @@ -732,7 +731,7 @@ { ALU64_BEGIN (GPR[RS]); ALU64_ADD (EXTEND16 (IMMEDIATE)); - ALU64_END (GPR[RT]); + ALU64_END (GPR[RT]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RT]); } @@ -1181,7 +1180,7 @@ { ALU64_BEGIN (GPR[RS]); ALU64_SUB (GPR[RT]); - ALU64_END (GPR[RD]); + ALU64_END (GPR[RD]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RD]); } @@ -2210,7 +2209,7 @@ { ALU32_BEGIN (GPR[RS]); ALU32_SUB (GPR[RT]); - ALU32_END (GPR[RD]); + ALU32_END (GPR[RD]); /* This checks for overflow. */ } TRACE_ALU_RESULT (GPR[RD]); } |