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author | Mike Frysinger <vapier@gentoo.org> | 2022-12-22 23:29:21 -0500 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2022-12-23 08:32:58 -0500 |
commit | 7790fabeb76850df5ffa36577a8a5cf40541fc37 (patch) | |
tree | 9399b924bc2f66bad1f34e03c303282e10df778d /sim/microblaze/microblaze-sim.h | |
parent | ca6fd350844c81c64cd145e50823bc806d446935 (diff) | |
download | gdb-7790fabeb76850df5ffa36577a8a5cf40541fc37.zip gdb-7790fabeb76850df5ffa36577a8a5cf40541fc37.tar.gz gdb-7790fabeb76850df5ffa36577a8a5cf40541fc37.tar.bz2 |
sim: microblaze: move arch-specific settings to internal header
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.
Diffstat (limited to 'sim/microblaze/microblaze-sim.h')
-rw-r--r-- | sim/microblaze/microblaze-sim.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/sim/microblaze/microblaze-sim.h b/sim/microblaze/microblaze-sim.h new file mode 100644 index 0000000..9e5fb07 --- /dev/null +++ b/sim/microblaze/microblaze-sim.h @@ -0,0 +1,46 @@ +/* Copyright 2009-2022 Free Software Foundation, Inc. + + This file is part of the Xilinx MicroBlaze simulator. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see <http://www.gnu.org/licenses/>. */ + +#ifndef MICROBLAZE_SIM_H +#define MICROBLAZE_SIM_H + +#include "microblaze.h" + +/* The machine state. + This state is maintained in host byte order. The + fetch/store register functions must translate between host + byte order and the target processor byte order. + Keeping this data in target byte order simplifies the register + read/write functions. Keeping this data in native order improves + the performance of the simulator. Simulation speed is deemed more + important. */ + +/* The ordering of the microblaze_regset structure is matched in the + gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */ + struct microblaze_regset +{ + signed_4 regs[32]; /* primary registers */ + signed_4 spregs[2]; /* pc + msr */ + int cycles; + int insts; + unsigned_1 imm_enable; + signed_2 imm_high; +}; + +#define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu)) + +#endif /* MICROBLAZE_SIM_H */ |