aboutsummaryrefslogtreecommitdiff
path: root/sim/mcore
diff options
context:
space:
mode:
authorJason Molenda <jmolenda@apple.com>1999-05-19 19:58:41 +0000
committerJason Molenda <jmolenda@apple.com>1999-05-19 19:58:41 +0000
commit9e086581c726753ae7459a4c77ea9b37c34c5500 (patch)
tree18cb4aec7982e5c6c740346600199e22b81c9566 /sim/mcore
parent1ceea51453d4ef2d739ce4dfe5d7a74c9a32dc64 (diff)
downloadgdb-9e086581c726753ae7459a4c77ea9b37c34c5500.zip
gdb-9e086581c726753ae7459a4c77ea9b37c34c5500.tar.gz
gdb-9e086581c726753ae7459a4c77ea9b37c34c5500.tar.bz2
import gdb-1999-0519
Diffstat (limited to 'sim/mcore')
-rw-r--r--sim/mcore/ChangeLog6
-rw-r--r--sim/mcore/interp.c5
2 files changed, 9 insertions, 2 deletions
diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog
index 486ad1d..140b96b 100644
--- a/sim/mcore/ChangeLog
+++ b/sim/mcore/ChangeLog
@@ -1,3 +1,9 @@
+1999-05-17 Keith Seitz <keiths@cygnus.com>
+
+ * interp.c (NUM_MCORE_REGS): Increase by one to allow access to PC.
+ (sim_resume): Correct off by one instruction error when a breakpoint
+ is hit.
+
1999-05-08 Felix Lee <flee@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 5807f5d..003f697 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -118,8 +118,8 @@ union
word asints [1]; /* but accessed larger... */
} cpu;
-#define LAST_VALID_CREG 12 /* only 0..12 implemented */
-#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG)
+#define LAST_VALID_CREG 32 /* only 0..12 implemented */
+#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
int memcycles = 1;
@@ -840,6 +840,7 @@ sim_resume (sd, step, siggnal)
{
case 0x0: /* bkpt */
cpu.asregs.exception = SIGTRAP;
+ pc -= 2;
break;
case 0x1: /* sync */