This commit was manufactured by cvs2svn to create branch 'cr-0x5f1'.cr-0x5f1

Sprout from master 2006-07-25 08:39:57 UTC Paolo Bonzini <bonzini@gnu.org> 'Sync from GCC'
Cherrypick from cygnus 2000-02-22 15:59:20 UTC Ian Lance Taylor <ian@airs.com> 'import libiberty from egcs':
    README
    config/mh-armpic
    config/mh-elfalphapic
    config/mh-m68kpic
    config/mh-papic
    config/mh-ppcpic
    config/mh-x86pic
    config/mt-d30v
    config/mt-netware
    config/mt-ospace
    etc/add-log.el
    etc/add-log.vi
    etc/configbuild.ein
    etc/configbuild.fig
    etc/configbuild.jin
    etc/configbuild.tin
    etc/configdev.ein
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    include/aout/hppa.h
    include/coff/sym.h
    include/fopen-bin.h
    include/fopen-same.h
    include/fopen-vms.h
    include/opcode/tahoe.h
    libiberty/config.h-vms
    libiberty/config/mh-aix
    libiberty/config/mh-cxux7
    libiberty/config/mh-fbsd21
    libiberty/config/mh-windows
    libiberty/makefile.vms
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    binutils/testsuite/binutils-all/windres/strtab1.rsd
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    cpu/frv.opc
    cpu/iq10.cpu
    cpu/iq2000.cpu
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    cpu/sh64-compact.cpu
    cpu/sh64-media.cpu
    cpu/simplify.inc
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    djunpack.bat
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    gas/ChangeLog-0203
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    gas/ChangeLog-9295
    gas/ChangeLog-9697
    gas/ChangeLog-9899
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    gas/gdbinit.in
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    gas/testsuite/gas/h8300/symaddgen.s
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    gas/testsuite/gas/h8300/t05_cmp.s
    gas/testsuite/gas/h8300/t06_ari2.exp
    gas/testsuite/gas/h8300/t06_ari2.s
    gas/testsuite/gas/h8300/t07_ari3.exp
    gas/testsuite/gas/h8300/t07_ari3.s
    gas/testsuite/gas/h8300/t08_or.exp
    gas/testsuite/gas/h8300/t08_or.s
    gas/testsuite/gas/h8300/t09_xor.exp
    gas/testsuite/gas/h8300/t09_xor.s
    gas/testsuite/gas/h8300/t10_and.exp
    gas/testsuite/gas/h8300/t10_and.s
    gas/testsuite/gas/h8300/t11_logs.exp
    gas/testsuite/gas/h8300/t11_logs.s
    gas/testsuite/gas/h8300/t12_bit.exp
    gas/testsuite/gas/h8300/t12_bit.s
    gas/testsuite/gas/h8300/t13_otr.exp
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    gas/testsuite/gas/hppa/basic/dcor.s
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    gas/testsuite/gas/hppa/basic/fmemLRbug.s
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    gas/testsuite/gas/m68k-coff/p2430.s
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    gas/testsuite/gas/macros/app3.d
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    gas/testsuite/gas/macros/app4.d
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    gas/testsuite/gas/mips/bltu.d
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    gas/testsuite/gas/mips/branch-misc-1.d
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    gas/testsuite/gas/mips/branch-misc-2-64.d
    gas/testsuite/gas/mips/branch-misc-2.d
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    gas/testsuite/gas/mips/branch-misc-2pic-64.d
    gas/testsuite/gas/mips/branch-misc-2pic.d
    gas/testsuite/gas/mips/branch-misc-3.d
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    gas/testsuite/gas/mips/cp0-names-mips64.d
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    gas/testsuite/gas/s390/esa-z900.d
    gas/testsuite/gas/s390/esa-z900.s
    gas/testsuite/gas/s390/esa-z990.d
    gas/testsuite/gas/s390/esa-z990.s
    gas/testsuite/gas/s390/operands.d
    gas/testsuite/gas/s390/operands.s
    gas/testsuite/gas/s390/operands64.d
    gas/testsuite/gas/s390/operands64.s
    gas/testsuite/gas/s390/s390.exp
    gas/testsuite/gas/s390/zarch-operands.d
    gas/testsuite/gas/s390/zarch-operands.s
    gas/testsuite/gas/s390/zarch-reloc.d
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    gas/testsuite/gas/s390/zarch-z9-109.d
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    gas/testsuite/gas/s390/zarch-z900.d
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    gas/testsuite/gas/s390/zarch-z990.d
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    gas/testsuite/gas/sh/arch/arch.exp
    gas/testsuite/gas/sh/arch/arch_expected.txt
    gas/testsuite/gas/sh/arch/sh-dsp.s
    gas/testsuite/gas/sh/arch/sh.s
    gas/testsuite/gas/sh/arch/sh2.s
    gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
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    gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
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    gas/testsuite/gas/sh/arch/sh3-nommu.s
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    gas/testsuite/gas/sh/arch/sh4-nofpu.s
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    gas/testsuite/gas/sh/arch/sh4al-dsp.s
    gas/testsuite/gas/sh/basic.exp
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    gas/testsuite/gas/sh/pcrel-coff.d
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    gas/testsuite/gas/sh/sh2a.d
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    gas/testsuite/gas/sparc-solaris/addend.exp
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    gas/testsuite/gas/sparc-solaris/gas.exp
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    gas/testsuite/gas/sparc/asi.d
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    gas/testsuite/gas/sparc/pcrel64.d
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    ld/testsuite/ld-cris/dsov32-3.s
    ld/testsuite/ld-cris/dsov32-4.s
    ld/testsuite/ld-cris/euwref1.s
    ld/testsuite/ld-cris/expdref1.s
    ld/testsuite/ld-cris/expdyn1.d
    ld/testsuite/ld-cris/expdyn1.s
    ld/testsuite/ld-cris/expdyn2.d
    ld/testsuite/ld-cris/expdyn3.d
    ld/testsuite/ld-cris/expdyn4.d
    ld/testsuite/ld-cris/expdyn5.d
    ld/testsuite/ld-cris/expdyn6.d
    ld/testsuite/ld-cris/expdyn7.d
    ld/testsuite/ld-cris/globsym1ref.s
    ld/testsuite/ld-cris/globsymw1.s
    ld/testsuite/ld-cris/globsymw2.s
    ld/testsuite/ld-cris/gotplt1.d
    ld/testsuite/ld-cris/gotplt2.d
    ld/testsuite/ld-cris/gotplt3.d
    ld/testsuite/ld-cris/gotrel1.s
    ld/testsuite/ld-cris/gotrel2.s
    ld/testsuite/ld-cris/hiddef1.d
    ld/testsuite/ld-cris/hiddef1.s
    ld/testsuite/ld-cris/hide1
    ld/testsuite/ld-cris/hidrefgotplt1.s
    ld/testsuite/ld-cris/ldsym1.d
    ld/testsuite/ld-cris/libdso-1.d
    ld/testsuite/ld-cris/libdso-10.d
    ld/testsuite/ld-cris/libdso-11.d
    ld/testsuite/ld-cris/libdso-12.d
    ld/testsuite/ld-cris/libdso-13.d
    ld/testsuite/ld-cris/libdso-14.d
    ld/testsuite/ld-cris/libdso-2.d
    ld/testsuite/ld-cris/libdso-3.d
    ld/testsuite/ld-cris/libdso-4.d
    ld/testsuite/ld-cris/locref1.d
    ld/testsuite/ld-cris/locref1.s
    ld/testsuite/ld-cris/locref2.d
    ld/testsuite/ld-cris/locref2.s
    ld/testsuite/ld-cris/move-1.s
    ld/testsuite/ld-cris/nodyn4.d
    ld/testsuite/ld-cris/nodyn5.d
    ld/testsuite/ld-cris/noglob1.d
    ld/testsuite/ld-cris/noglob1.s
    ld/testsuite/ld-cris/noov.d
    ld/testsuite/ld-cris/noov.s
    ld/testsuite/ld-cris/pv32-1.d
    ld/testsuite/ld-cris/pv32.s
    ld/testsuite/ld-cris/stabs1.s
    ld/testsuite/ld-cris/start1.s
    ld/testsuite/ld-cris/undef1.d
    ld/testsuite/ld-cris/undef2.d
    ld/testsuite/ld-cris/undef3.d
    ld/testsuite/ld-cris/v10-v32.d
    ld/testsuite/ld-cris/v10-va.d
    ld/testsuite/ld-cris/v32-ba-1.d
    ld/testsuite/ld-cris/v32-ba-1.s
    ld/testsuite/ld-cris/v32-bin-1.d
    ld/testsuite/ld-cris/v32-bin-1.s
    ld/testsuite/ld-cris/v32-v10.d
    ld/testsuite/ld-cris/v32-va.d
    ld/testsuite/ld-cris/va-v10.d
    ld/testsuite/ld-cris/va-v32.d
    ld/testsuite/ld-cris/warn1.d
    ld/testsuite/ld-cris/warn2.d
    ld/testsuite/ld-cris/warn3.d
    ld/testsuite/ld-cris/warn4.d
    ld/testsuite/ld-cris/weakref1.d
    ld/testsuite/ld-cris/weakref2.d
    ld/testsuite/ld-crx/crx.exp
    ld/testsuite/ld-crx/crx.ld
    ld/testsuite/ld-crx/reloc-abs32.d
    ld/testsuite/ld-crx/reloc-abs32.s
    ld/testsuite/ld-crx/reloc-imm16.d
    ld/testsuite/ld-crx/reloc-imm16.s
    ld/testsuite/ld-crx/reloc-imm32.d
    ld/testsuite/ld-crx/reloc-imm32.s
    ld/testsuite/ld-crx/reloc-num16.d
    ld/testsuite/ld-crx/reloc-num16.s
    ld/testsuite/ld-crx/reloc-num32.d
    ld/testsuite/ld-crx/reloc-num32.s
    ld/testsuite/ld-crx/reloc-num8.d
    ld/testsuite/ld-crx/reloc-num8.s
    ld/testsuite/ld-crx/reloc-regrel12.d
    ld/testsuite/ld-crx/reloc-regrel12.s
    ld/testsuite/ld-crx/reloc-regrel22.d
    ld/testsuite/ld-crx/reloc-regrel22.s
    ld/testsuite/ld-crx/reloc-regrel28.d
    ld/testsuite/ld-crx/reloc-regrel28.s
    ld/testsuite/ld-crx/reloc-regrel32.d
    ld/testsuite/ld-crx/reloc-regrel32.s
    ld/testsuite/ld-crx/reloc-rel16.d
    ld/testsuite/ld-crx/reloc-rel16.s
    ld/testsuite/ld-crx/reloc-rel24.d
    ld/testsuite/ld-crx/reloc-rel24.s
    ld/testsuite/ld-crx/reloc-rel32.d
    ld/testsuite/ld-crx/reloc-rel32.s
    ld/testsuite/ld-crx/reloc-rel4.d
    ld/testsuite/ld-crx/reloc-rel4.s
    ld/testsuite/ld-crx/reloc-rel8-cmp.d
    ld/testsuite/ld-crx/reloc-rel8-cmp.s
    ld/testsuite/ld-crx/reloc-rel8.d
    ld/testsuite/ld-crx/reloc-rel8.s
    ld/testsuite/ld-cygwin/exe-export.exp
    ld/testsuite/ld-cygwin/testdll.c
    ld/testsuite/ld-cygwin/testdll.def
    ld/testsuite/ld-cygwin/testexe.c
    ld/testsuite/ld-cygwin/testexe.def
    ld/testsuite/ld-d10v/d10v.exp
    ld/testsuite/ld-d10v/default_layout.d
    ld/testsuite/ld-d10v/linktest-001.s
    ld/testsuite/ld-d10v/linktest-002.lt
    ld/testsuite/ld-d10v/linktest-002.s
    ld/testsuite/ld-d10v/regression-001.lt
    ld/testsuite/ld-d10v/regression-001.s
    ld/testsuite/ld-d10v/reloc-001.d
    ld/testsuite/ld-d10v/reloc-001.ld
    ld/testsuite/ld-d10v/reloc-001.s
    ld/testsuite/ld-d10v/reloc-002.d
    ld/testsuite/ld-d10v/reloc-002.ld
    ld/testsuite/ld-d10v/reloc-003.d
    ld/testsuite/ld-d10v/reloc-003.ld
    ld/testsuite/ld-d10v/reloc-004.d
    ld/testsuite/ld-d10v/reloc-004.ld
    ld/testsuite/ld-d10v/reloc-005.d
    ld/testsuite/ld-d10v/reloc-005.ld
    ld/testsuite/ld-d10v/reloc-005.s
    ld/testsuite/ld-d10v/reloc-006.d
    ld/testsuite/ld-d10v/reloc-006.ld
    ld/testsuite/ld-d10v/reloc-007.d
    ld/testsuite/ld-d10v/reloc-007.ld
    ld/testsuite/ld-d10v/reloc-008.d
    ld/testsuite/ld-d10v/reloc-008.ld
    ld/testsuite/ld-d10v/reloc-009.d
    ld/testsuite/ld-d10v/reloc-009.ld
    ld/testsuite/ld-d10v/reloc-009.s
    ld/testsuite/ld-d10v/reloc-010.d
    ld/testsuite/ld-d10v/reloc-010.ld
    ld/testsuite/ld-d10v/reloc-011.d
    ld/testsuite/ld-d10v/reloc-011.ld
    ld/testsuite/ld-d10v/reloc-012.d
    ld/testsuite/ld-d10v/reloc-012.ld
    ld/testsuite/ld-d10v/reloc-013.d
    ld/testsuite/ld-d10v/reloc-013.ld
    ld/testsuite/ld-d10v/reloc-014.d
    ld/testsuite/ld-d10v/reloc-014.ld
    ld/testsuite/ld-d10v/reloc-015.d
    ld/testsuite/ld-d10v/reloc-015.ld
    ld/testsuite/ld-d10v/reloc-016.d
    ld/testsuite/ld-d10v/reloc-016.ld
    ld/testsuite/ld-d10v/simple.s
    ld/testsuite/ld-discard/discard.exp
    ld/testsuite/ld-discard/discard.ld
    ld/testsuite/ld-discard/exit.s
    ld/testsuite/ld-discard/extern.d
    ld/testsuite/ld-discard/extern.s
    ld/testsuite/ld-discard/start.d
    ld/testsuite/ld-discard/start.s
    ld/testsuite/ld-discard/static.d
    ld/testsuite/ld-discard/static.s
    ld/testsuite/ld-elf/begin.c
    ld/testsuite/ld-elf/binutils.exp
    ld/testsuite/ld-elf/commonpage1.d
    ld/testsuite/ld-elf/eh1.d
    ld/testsuite/ld-elf/eh1.s
    ld/testsuite/ld-elf/eh1a.s
    ld/testsuite/ld-elf/eh2.d
    ld/testsuite/ld-elf/eh2a.s
    ld/testsuite/ld-elf/eh3.d
    ld/testsuite/ld-elf/eh3.s
    ld/testsuite/ld-elf/eh3a.s
    ld/testsuite/ld-elf/elf.exp
    ld/testsuite/ld-elf/empty.d
    ld/testsuite/ld-elf/empty.s
    ld/testsuite/ld-elf/empty2.d
    ld/testsuite/ld-elf/empty2.s
    ld/testsuite/ld-elf/end.c
    ld/testsuite/ld-elf/endhidden.c
    ld/testsuite/ld-elf/endprotected.c
    ld/testsuite/ld-elf/exclude.exp
    ld/testsuite/ld-elf/exclude1.s
    ld/testsuite/ld-elf/exclude2.s
    ld/testsuite/ld-elf/fini.c
    ld/testsuite/ld-elf/fini.out
    ld/testsuite/ld-elf/foo.c
    ld/testsuite/ld-elf/foo.map
    ld/testsuite/ld-elf/frame.exp
    ld/testsuite/ld-elf/frame.s
    ld/testsuite/ld-elf/group.ld
    ld/testsuite/ld-elf/group1.d
    ld/testsuite/ld-elf/group1a.s
    ld/testsuite/ld-elf/group1b.s
    ld/testsuite/ld-elf/group2.d
    ld/testsuite/ld-elf/hidden.out
    ld/testsuite/ld-elf/init.c
    ld/testsuite/ld-elf/init.out
    ld/testsuite/ld-elf/main.c
    ld/testsuite/ld-elf/maxpage1.d
    ld/testsuite/ld-elf/maxpage1.s
    ld/testsuite/ld-elf/maxpage2.d
    ld/testsuite/ld-elf/merge.d
    ld/testsuite/ld-elf/merge.ld
    ld/testsuite/ld-elf/merge.s
    ld/testsuite/ld-elf/merge2.d
    ld/testsuite/ld-elf/merge2.s
    ld/testsuite/ld-elf/normal.out
    ld/testsuite/ld-elf/orphan.d
    ld/testsuite/ld-elf/orphan.ld
    ld/testsuite/ld-elf/orphan.s
    ld/testsuite/ld-elf/orphan2.d
    ld/testsuite/ld-elf/orphan2.s
    ld/testsuite/ld-elf/preinit.c
    ld/testsuite/ld-elf/preinit.out
    ld/testsuite/ld-elf/sec64k.exp
    ld/testsuite/ld-elf/shared.exp
    ld/testsuite/ld-elf/stab.d
    ld/testsuite/ld-elf/start.s
    ld/testsuite/ld-elf/symbol1ref.s
    ld/testsuite/ld-elf/symbol1w.s
    ld/testsuite/ld-elf/table.s
    ld/testsuite/ld-elf/tbss.s
    ld/testsuite/ld-elf/tbss1.s
    ld/testsuite/ld-elf/tbss2.s
    ld/testsuite/ld-elf/tdata1.s
    ld/testsuite/ld-elf/tdata2.s
    ld/testsuite/ld-elf/tls_common.exp
    ld/testsuite/ld-elf/tls_common.s
    ld/testsuite/ld-elf/unknown.d
    ld/testsuite/ld-elf/unknown2.d
    ld/testsuite/ld-elf/unknown2.s
    ld/testsuite/ld-elf/warn1.d
    ld/testsuite/ld-elfcomm/common1a.c
    ld/testsuite/ld-elfcomm/common1b.c
    ld/testsuite/ld-elfcomm/elfcomm.exp
    ld/testsuite/ld-elfvers/vers.exp
    ld/testsuite/ld-elfvers/vers1.c
    ld/testsuite/ld-elfvers/vers1.dsym
    ld/testsuite/ld-elfvers/vers1.map
    ld/testsuite/ld-elfvers/vers1.sym
    ld/testsuite/ld-elfvers/vers1.ver
    ld/testsuite/ld-elfvers/vers13.asym
    ld/testsuite/ld-elfvers/vers15.c
    ld/testsuite/ld-elfvers/vers15.dsym
    ld/testsuite/ld-elfvers/vers15.sym
    ld/testsuite/ld-elfvers/vers15.ver
    ld/testsuite/ld-elfvers/vers16.c
    ld/testsuite/ld-elfvers/vers16.dsym
    ld/testsuite/ld-elfvers/vers16.map
    ld/testsuite/ld-elfvers/vers16a.c
    ld/testsuite/ld-elfvers/vers16a.dsym
    ld/testsuite/ld-elfvers/vers16a.ver
    ld/testsuite/ld-elfvers/vers17.c
    ld/testsuite/ld-elfvers/vers17.dsym
    ld/testsuite/ld-elfvers/vers17.map
    ld/testsuite/ld-elfvers/vers17.ver
    ld/testsuite/ld-elfvers/vers18.c
    ld/testsuite/ld-elfvers/vers18.dsym
    ld/testsuite/ld-elfvers/vers18.map
    ld/testsuite/ld-elfvers/vers18.sym
    ld/testsuite/ld-elfvers/vers18.ver
    ld/testsuite/ld-elfvers/vers19.c
    ld/testsuite/ld-elfvers/vers19.dsym
    ld/testsuite/ld-elfvers/vers19.ver
    ld/testsuite/ld-elfvers/vers2.c
    ld/testsuite/ld-elfvers/vers2.dsym
    ld/testsuite/ld-elfvers/vers2.map
    ld/testsuite/ld-elfvers/vers2.ver
    ld/testsuite/ld-elfvers/vers20.c
    ld/testsuite/ld-elfvers/vers20.dsym
    ld/testsuite/ld-elfvers/vers20.map
    ld/testsuite/ld-elfvers/vers20.ver
    ld/testsuite/ld-elfvers/vers20a.ver
    ld/testsuite/ld-elfvers/vers21.c
    ld/testsuite/ld-elfvers/vers21.dsym
    ld/testsuite/ld-elfvers/vers21.map
    ld/testsuite/ld-elfvers/vers21.sym
    ld/testsuite/ld-elfvers/vers21.ver
    ld/testsuite/ld-elfvers/vers22.c
    ld/testsuite/ld-elfvers/vers22.dsym
    ld/testsuite/ld-elfvers/vers22.map
    ld/testsuite/ld-elfvers/vers22.ver
    ld/testsuite/ld-elfvers/vers22a.c
    ld/testsuite/ld-elfvers/vers22a.dsym
    ld/testsuite/ld-elfvers/vers22a.sym
    ld/testsuite/ld-elfvers/vers22a.ver
    ld/testsuite/ld-elfvers/vers22b.c
    ld/testsuite/ld-elfvers/vers22b.dsym
    ld/testsuite/ld-elfvers/vers22b.ver
    ld/testsuite/ld-elfvers/vers23.c
    ld/testsuite/ld-elfvers/vers23.dsym
    ld/testsuite/ld-elfvers/vers23.ver
    ld/testsuite/ld-elfvers/vers23a.c
    ld/testsuite/ld-elfvers/vers23a.dsym
    ld/testsuite/ld-elfvers/vers23a.map
    ld/testsuite/ld-elfvers/vers23a.sym
    ld/testsuite/ld-elfvers/vers23a.ver
    ld/testsuite/ld-elfvers/vers23b.c
    ld/testsuite/ld-elfvers/vers23b.dsym
    ld/testsuite/ld-elfvers/vers23b.map
    ld/testsuite/ld-elfvers/vers23b.ver
    ld/testsuite/ld-elfvers/vers23c.ver
    ld/testsuite/ld-elfvers/vers23d.dsym
    ld/testsuite/ld-elfvers/vers24.map
    ld/testsuite/ld-elfvers/vers24.rd
    ld/testsuite/ld-elfvers/vers24a.c
    ld/testsuite/ld-elfvers/vers24b.c
    ld/testsuite/ld-elfvers/vers24c.c
    ld/testsuite/ld-elfvers/vers25a.c
    ld/testsuite/ld-elfvers/vers25a.dsym
    ld/testsuite/ld-elfvers/vers25a.map
    ld/testsuite/ld-elfvers/vers25a.ver
    ld/testsuite/ld-elfvers/vers25b.c
    ld/testsuite/ld-elfvers/vers25b.dsym
    ld/testsuite/ld-elfvers/vers25b.ver
    ld/testsuite/ld-elfvers/vers26a.c
    ld/testsuite/ld-elfvers/vers26a.dsym
    ld/testsuite/ld-elfvers/vers26a.map
    ld/testsuite/ld-elfvers/vers26a.ver
    ld/testsuite/ld-elfvers/vers26b.c
    ld/testsuite/ld-elfvers/vers26b.dsym
    ld/testsuite/ld-elfvers/vers26b.ver
    ld/testsuite/ld-elfvers/vers27a.c
    ld/testsuite/ld-elfvers/vers27a.dsym
    ld/testsuite/ld-elfvers/vers27a.map
    ld/testsuite/ld-elfvers/vers27a.ver
    ld/testsuite/ld-elfvers/vers27b.c
    ld/testsuite/ld-elfvers/vers27b.dsym
    ld/testsuite/ld-elfvers/vers27b.ver
    ld/testsuite/ld-elfvers/vers27c.c
    ld/testsuite/ld-elfvers/vers27c.dsym
    ld/testsuite/ld-elfvers/vers27c.ver
    ld/testsuite/ld-elfvers/vers27d.dsym
    ld/testsuite/ld-elfvers/vers27d.sym
    ld/testsuite/ld-elfvers/vers27d.ver
    ld/testsuite/ld-elfvers/vers27d1.c
    ld/testsuite/ld-elfvers/vers27d2.c
    ld/testsuite/ld-elfvers/vers27d3.c
    ld/testsuite/ld-elfvers/vers27d4.dsym
    ld/testsuite/ld-elfvers/vers27d4.ver
    ld/testsuite/ld-elfvers/vers28a.c
    ld/testsuite/ld-elfvers/vers28a.dsym
    ld/testsuite/ld-elfvers/vers28a.ver
    ld/testsuite/ld-elfvers/vers28b.c
    ld/testsuite/ld-elfvers/vers28b.dsym
    ld/testsuite/ld-elfvers/vers28b.map
    ld/testsuite/ld-elfvers/vers28b.ver
    ld/testsuite/ld-elfvers/vers28c.c
    ld/testsuite/ld-elfvers/vers28c.dsym
    ld/testsuite/ld-elfvers/vers28c.ver
    ld/testsuite/ld-elfvers/vers29.c
    ld/testsuite/ld-elfvers/vers29.dsym
    ld/testsuite/ld-elfvers/vers29.ver
    ld/testsuite/ld-elfvers/vers3.c
    ld/testsuite/ld-elfvers/vers3.dsym
    ld/testsuite/ld-elfvers/vers3.ver
    ld/testsuite/ld-elfvers/vers30.c
    ld/testsuite/ld-elfvers/vers30.dsym
    ld/testsuite/ld-elfvers/vers30.map
    ld/testsuite/ld-elfvers/vers30.ver
    ld/testsuite/ld-elfvers/vers31.c
    ld/testsuite/ld-elfvers/vers31.dsym
    ld/testsuite/ld-elfvers/vers31.map
    ld/testsuite/ld-elfvers/vers31.ver
    ld/testsuite/ld-elfvers/vers4.c
    ld/testsuite/ld-elfvers/vers4.sym
    ld/testsuite/ld-elfvers/vers4a.dsym
    ld/testsuite/ld-elfvers/vers4a.sym
    ld/testsuite/ld-elfvers/vers4a.ver
    ld/testsuite/ld-elfvers/vers5.c
    ld/testsuite/ld-elfvers/vers6.c
    ld/testsuite/ld-elfvers/vers6.dsym
    ld/testsuite/ld-elfvers/vers6.sym
    ld/testsuite/ld-elfvers/vers6.ver
    ld/testsuite/ld-elfvers/vers7.c
    ld/testsuite/ld-elfvers/vers7.map
    ld/testsuite/ld-elfvers/vers7a.c
    ld/testsuite/ld-elfvers/vers7a.dsym
    ld/testsuite/ld-elfvers/vers7a.sym
    ld/testsuite/ld-elfvers/vers7a.ver
    ld/testsuite/ld-elfvers/vers8.c
    ld/testsuite/ld-elfvers/vers8.map
    ld/testsuite/ld-elfvers/vers8.ver
    ld/testsuite/ld-elfvers/vers9.c
    ld/testsuite/ld-elfvers/vers9.dsym
    ld/testsuite/ld-elfvers/vers9.sym
    ld/testsuite/ld-elfvers/vers9.ver
    ld/testsuite/ld-elfvsb/common.c
    ld/testsuite/ld-elfvsb/define.s
    ld/testsuite/ld-elfvsb/elf-offset.ld
    ld/testsuite/ld-elfvsb/elfvsb.dat
    ld/testsuite/ld-elfvsb/elfvsb.exp
    ld/testsuite/ld-elfvsb/hidden0.d
    ld/testsuite/ld-elfvsb/hidden1.d
    ld/testsuite/ld-elfvsb/hidden2.d
    ld/testsuite/ld-elfvsb/hidden2.ld
    ld/testsuite/ld-elfvsb/hidden2.s
    ld/testsuite/ld-elfvsb/internal0.d
    ld/testsuite/ld-elfvsb/internal1.d
    ld/testsuite/ld-elfvsb/main.c
    ld/testsuite/ld-elfvsb/protected0.d
    ld/testsuite/ld-elfvsb/protected1.d
    ld/testsuite/ld-elfvsb/sh1.c
    ld/testsuite/ld-elfvsb/sh2.c
    ld/testsuite/ld-elfvsb/sh3.c
    ld/testsuite/ld-elfvsb/test.c
    ld/testsuite/ld-elfvsb/undef.s
    ld/testsuite/ld-elfweak/bar.c
    ld/testsuite/ld-elfweak/bar1a.c
    ld/testsuite/ld-elfweak/bar1b.c
    ld/testsuite/ld-elfweak/bar1c.c
    ld/testsuite/ld-elfweak/dso.dsym
    ld/testsuite/ld-elfweak/dsodata.dsym
    ld/testsuite/ld-elfweak/dsow.dsym
    ld/testsuite/ld-elfweak/dsowdata.dsym
    ld/testsuite/ld-elfweak/elfweak.exp
    ld/testsuite/ld-elfweak/foo.c
    ld/testsuite/ld-elfweak/foo1a.c
    ld/testsuite/ld-elfweak/foo1b.c
    ld/testsuite/ld-elfweak/main.c
    ld/testsuite/ld-elfweak/main1.c
    ld/testsuite/ld-elfweak/size.dat
    ld/testsuite/ld-elfweak/size2.d
    ld/testsuite/ld-elfweak/size2a.s
    ld/testsuite/ld-elfweak/size2b.s
    ld/testsuite/ld-elfweak/size_bar.c
    ld/testsuite/ld-elfweak/size_foo.c
    ld/testsuite/ld-elfweak/size_main.c
    ld/testsuite/ld-elfweak/strong.dat
    ld/testsuite/ld-elfweak/strong.sym
    ld/testsuite/ld-elfweak/strongcomm.sym
    ld/testsuite/ld-elfweak/strongdata.dat
    ld/testsuite/ld-elfweak/strongdata.sym
    ld/testsuite/ld-elfweak/weak.dat
    ld/testsuite/ld-elfweak/weak.dsym
    ld/testsuite/ld-elfweak/weakdata.dat
    ld/testsuite/ld-elfweak/weakdata.dsym
    ld/testsuite/ld-fastcall/export.s
    ld/testsuite/ld-fastcall/fastcall.exp
    ld/testsuite/ld-fastcall/import.s
    ld/testsuite/ld-frv/fdpic-pie-1.d
    ld/testsuite/ld-frv/fdpic-pie-2.d
    ld/testsuite/ld-frv/fdpic-pie-5.d
    ld/testsuite/ld-frv/fdpic-pie-6-fail.d
    ld/testsuite/ld-frv/fdpic-pie-6.d
    ld/testsuite/ld-frv/fdpic-pie-7.d
    ld/testsuite/ld-frv/fdpic-pie-8.d
    ld/testsuite/ld-frv/fdpic-shared-1.d
    ld/testsuite/ld-frv/fdpic-shared-2-fail.d
    ld/testsuite/ld-frv/fdpic-shared-2.d
    ld/testsuite/ld-frv/fdpic-shared-3.d
    ld/testsuite/ld-frv/fdpic-shared-4.d
    ld/testsuite/ld-frv/fdpic-shared-5.d
    ld/testsuite/ld-frv/fdpic-shared-6-fail.d
    ld/testsuite/ld-frv/fdpic-shared-6.d
    ld/testsuite/ld-frv/fdpic-shared-7.d
    ld/testsuite/ld-frv/fdpic-shared-8-fail.d
    ld/testsuite/ld-frv/fdpic-shared-8.d
    ld/testsuite/ld-frv/fdpic-shared-local-2.d
    ld/testsuite/ld-frv/fdpic-shared-local-8.d
    ld/testsuite/ld-frv/fdpic-static-1.d
    ld/testsuite/ld-frv/fdpic-static-2.d
    ld/testsuite/ld-frv/fdpic-static-5.d
    ld/testsuite/ld-frv/fdpic-static-6.d
    ld/testsuite/ld-frv/fdpic-static-7.d
    ld/testsuite/ld-frv/fdpic-static-8.d
    ld/testsuite/ld-frv/fdpic.exp
    ld/testsuite/ld-frv/fdpic1.s
    ld/testsuite/ld-frv/fdpic2.ldv
    ld/testsuite/ld-frv/fdpic2.s
    ld/testsuite/ld-frv/fdpic2min.ldv
    ld/testsuite/ld-frv/fdpic3.s
    ld/testsuite/ld-frv/fdpic4.s
    ld/testsuite/ld-frv/fdpic5.s
    ld/testsuite/ld-frv/fdpic6.ldv
    ld/testsuite/ld-frv/fdpic6.s
    ld/testsuite/ld-frv/fdpic7.s
    ld/testsuite/ld-frv/fdpic8.ldv
    ld/testsuite/ld-frv/fdpic8.s
    ld/testsuite/ld-frv/fdpic8min.ldv
    ld/testsuite/ld-frv/fr450-link.d
    ld/testsuite/ld-frv/fr450-linka.s
    ld/testsuite/ld-frv/fr450-linkb.s
    ld/testsuite/ld-frv/fr450-linkc.s
    ld/testsuite/ld-frv/frv-elf.exp
    ld/testsuite/ld-frv/tls-1-dep.s
    ld/testsuite/ld-frv/tls-1-shared.lds
    ld/testsuite/ld-frv/tls-1.s
    ld/testsuite/ld-frv/tls-2.s
    ld/testsuite/ld-frv/tls-3.s
    ld/testsuite/ld-frv/tls-dynamic-1.d
    ld/testsuite/ld-frv/tls-dynamic-2.d
    ld/testsuite/ld-frv/tls-dynamic-3.d
    ld/testsuite/ld-frv/tls-initial-shared-2.d
    ld/testsuite/ld-frv/tls-pie-1.d
    ld/testsuite/ld-frv/tls-pie-3.d
    ld/testsuite/ld-frv/tls-relax-dynamic-1.d
    ld/testsuite/ld-frv/tls-relax-dynamic-2.d
    ld/testsuite/ld-frv/tls-relax-dynamic-3.d
    ld/testsuite/ld-frv/tls-relax-initial-shared-2.d
    ld/testsuite/ld-frv/tls-relax-pie-1.d
    ld/testsuite/ld-frv/tls-relax-pie-3.d
    ld/testsuite/ld-frv/tls-relax-shared-1.d
    ld/testsuite/ld-frv/tls-relax-shared-2.d
    ld/testsuite/ld-frv/tls-relax-shared-3.d
    ld/testsuite/ld-frv/tls-relax-static-1.d
    ld/testsuite/ld-frv/tls-relax-static-3.d
    ld/testsuite/ld-frv/tls-shared-1-fail.d
    ld/testsuite/ld-frv/tls-shared-1.d
    ld/testsuite/ld-frv/tls-shared-2.d
    ld/testsuite/ld-frv/tls-shared-3.d
    ld/testsuite/ld-frv/tls-static-1.d
    ld/testsuite/ld-frv/tls-static-3.d
    ld/testsuite/ld-frv/tls.exp
    ld/testsuite/ld-h8300/gcsection.d
    ld/testsuite/ld-h8300/gcsection.s
    ld/testsuite/ld-h8300/h8300.exp
    ld/testsuite/ld-h8300/relax-2.d
    ld/testsuite/ld-h8300/relax-2.s
    ld/testsuite/ld-h8300/relax-3-coff.d
    ld/testsuite/ld-h8300/relax-3.d
    ld/testsuite/ld-h8300/relax-3.s
    ld/testsuite/ld-h8300/relax-4-coff.d
    ld/testsuite/ld-h8300/relax-4.d
    ld/testsuite/ld-h8300/relax-4.s
    ld/testsuite/ld-h8300/relax-5-coff.d
    ld/testsuite/ld-h8300/relax-5.d
    ld/testsuite/ld-h8300/relax-5.s
    ld/testsuite/ld-h8300/relax-6-coff.d
    ld/testsuite/ld-h8300/relax-6.d
    ld/testsuite/ld-h8300/relax-6.s
    ld/testsuite/ld-h8300/relax.d
    ld/testsuite/ld-h8300/relax.s
    ld/testsuite/ld-i386/abs.d
    ld/testsuite/ld-i386/abs.s
    ld/testsuite/ld-i386/combreloc.d
    ld/testsuite/ld-i386/combreloc.s
    ld/testsuite/ld-i386/emit-relocs.d
    ld/testsuite/ld-i386/emit-relocs.s
    ld/testsuite/ld-i386/i386.exp
    ld/testsuite/ld-i386/pcrel16.d
    ld/testsuite/ld-i386/pcrel16.s
    ld/testsuite/ld-i386/pcrel8.d
    ld/testsuite/ld-i386/pcrel8.s
    ld/testsuite/ld-i386/reloc.d
    ld/testsuite/ld-i386/reloc.s
    ld/testsuite/ld-i386/tlsbin.dd
    ld/testsuite/ld-i386/tlsbin.rd
    ld/testsuite/ld-i386/tlsbin.s
    ld/testsuite/ld-i386/tlsbin.sd
    ld/testsuite/ld-i386/tlsbin.td
    ld/testsuite/ld-i386/tlsbindesc.dd
    ld/testsuite/ld-i386/tlsbindesc.rd
    ld/testsuite/ld-i386/tlsbindesc.s
    ld/testsuite/ld-i386/tlsbindesc.sd
    ld/testsuite/ld-i386/tlsbindesc.td
    ld/testsuite/ld-i386/tlsbinpic.s
    ld/testsuite/ld-i386/tlsdesc.dd
    ld/testsuite/ld-i386/tlsdesc.rd
    ld/testsuite/ld-i386/tlsdesc.s
    ld/testsuite/ld-i386/tlsdesc.sd
    ld/testsuite/ld-i386/tlsdesc.td
    ld/testsuite/ld-i386/tlsg.s
    ld/testsuite/ld-i386/tlsg.sd
    ld/testsuite/ld-i386/tlsgdesc.dd
    ld/testsuite/ld-i386/tlsgdesc.rd
    ld/testsuite/ld-i386/tlsgdesc.s
    ld/testsuite/ld-i386/tlsindntpoff.dd
    ld/testsuite/ld-i386/tlsindntpoff.s
    ld/testsuite/ld-i386/tlslib.s
    ld/testsuite/ld-i386/tlsnopic.dd
    ld/testsuite/ld-i386/tlsnopic.rd
    ld/testsuite/ld-i386/tlsnopic.sd
    ld/testsuite/ld-i386/tlsnopic1.s
    ld/testsuite/ld-i386/tlsnopic2.s
    ld/testsuite/ld-i386/tlspic.dd
    ld/testsuite/ld-i386/tlspic.rd
    ld/testsuite/ld-i386/tlspic.sd
    ld/testsuite/ld-i386/tlspic.td
    ld/testsuite/ld-i386/tlspic1.s
    ld/testsuite/ld-i386/tlspic2.s
    ld/testsuite/ld-i386/vxworks1-lib.dd
    ld/testsuite/ld-i386/vxworks1-lib.nd
    ld/testsuite/ld-i386/vxworks1-lib.rd
    ld/testsuite/ld-i386/vxworks1-lib.s
    ld/testsuite/ld-i386/vxworks1-static.d
    ld/testsuite/ld-i386/vxworks1.dd
    ld/testsuite/ld-i386/vxworks1.ld
    ld/testsuite/ld-i386/vxworks1.rd
    ld/testsuite/ld-i386/vxworks1.s
    ld/testsuite/ld-i386/vxworks2-static.sd
    ld/testsuite/ld-i386/vxworks2.s
    ld/testsuite/ld-i386/vxworks2.sd
    ld/testsuite/ld-i386/zero.s
    ld/testsuite/ld-ia64/ia64.exp
    ld/testsuite/ld-ia64/link-order.d
    ld/testsuite/ld-ia64/tlsbin.dd
    ld/testsuite/ld-ia64/tlsbin.rd
    ld/testsuite/ld-ia64/tlsbin.s
    ld/testsuite/ld-ia64/tlsbin.sd
    ld/testsuite/ld-ia64/tlsbin.td
    ld/testsuite/ld-ia64/tlsbinpic.s
    ld/testsuite/ld-ia64/tlsg.s
    ld/testsuite/ld-ia64/tlsg.sd
    ld/testsuite/ld-ia64/tlslib.s
    ld/testsuite/ld-ia64/tlspic.dd
    ld/testsuite/ld-ia64/tlspic.rd
    ld/testsuite/ld-ia64/tlspic.sd
    ld/testsuite/ld-ia64/tlspic.td
    ld/testsuite/ld-ia64/tlspic1.s
    ld/testsuite/ld-ia64/tlspic2.s
    ld/testsuite/ld-linkonce/linkonce.exp
    ld/testsuite/ld-linkonce/x.s
    ld/testsuite/ld-linkonce/y.s
    ld/testsuite/ld-linkonce/zeroeh.ld
    ld/testsuite/ld-linkonce/zeroehl32.d
    ld/testsuite/ld-m68hc11/adj-brset.d
    ld/testsuite/ld-m68hc11/adj-brset.s
    ld/testsuite/ld-m68hc11/adj-jump.d
    ld/testsuite/ld-m68hc11/adj-jump.s
    ld/testsuite/ld-m68hc11/bug-1403.d
    ld/testsuite/ld-m68hc11/bug-1403.s
    ld/testsuite/ld-m68hc11/bug-1417.d
    ld/testsuite/ld-m68hc11/bug-1417.s
    ld/testsuite/ld-m68hc11/bug-3331.d
    ld/testsuite/ld-m68hc11/bug-3331.s
    ld/testsuite/ld-m68hc11/far-hc11.d
    ld/testsuite/ld-m68hc11/far-hc11.s
    ld/testsuite/ld-m68hc11/far-hc12.d
    ld/testsuite/ld-m68hc11/far-hc12.ld
    ld/testsuite/ld-m68hc11/far-hc12.s
    ld/testsuite/ld-m68hc11/link-hc12.s
    ld/testsuite/ld-m68hc11/link-hcs12.d
    ld/testsuite/ld-m68hc11/link-hcs12.s
    ld/testsuite/ld-m68hc11/m68hc11.exp
    ld/testsuite/ld-m68hc11/relax-direct.d
    ld/testsuite/ld-m68hc11/relax-direct.s
    ld/testsuite/ld-m68hc11/relax-group.d
    ld/testsuite/ld-m68hc11/relax-group.s
    ld/testsuite/ld-m68k/isaa-mac.d
    ld/testsuite/ld-m68k/isaa-mac.s
    ld/testsuite/ld-m68k/isaa-nodiv.s
    ld/testsuite/ld-m68k/isaa.d
    ld/testsuite/ld-m68k/isaa.s
    ld/testsuite/ld-m68k/isaaplus.d
    ld/testsuite/ld-m68k/isaaplus.s
    ld/testsuite/ld-m68k/isab-float.d
    ld/testsuite/ld-m68k/isab-float.s
    ld/testsuite/ld-m68k/isab-nousp.s
    ld/testsuite/ld-m68k/isab.d
    ld/testsuite/ld-m68k/isab.s
    ld/testsuite/ld-m68k/m68k.exp
    ld/testsuite/ld-m68k/merge-error-1a.d
    ld/testsuite/ld-m68k/merge-error-1a.s
    ld/testsuite/ld-m68k/merge-error-1b.d
    ld/testsuite/ld-m68k/merge-error-1b.s
    ld/testsuite/ld-m68k/merge-error-1c.d
    ld/testsuite/ld-m68k/merge-error-1d.d
    ld/testsuite/ld-m68k/merge-error-1e.d
    ld/testsuite/ld-m68k/merge-ok-1a.d
    ld/testsuite/ld-m68k/merge-ok-1b.d
    ld/testsuite/ld-m68k/merge-ok-1c.d
    ld/testsuite/ld-m68k/merge.ld
    ld/testsuite/ld-m68k/plt1-68020.d
    ld/testsuite/ld-m68k/plt1-cpu32.d
    ld/testsuite/ld-m68k/plt1-empty.s
    ld/testsuite/ld-m68k/plt1-isab.d
    ld/testsuite/ld-m68k/plt1.ld
    ld/testsuite/ld-m68k/plt1.s
    ld/testsuite/ld-maxq/addend.dd
    ld/testsuite/ld-maxq/addend.s
    ld/testsuite/ld-maxq/maxq.exp
    ld/testsuite/ld-maxq/paddr.dd
    ld/testsuite/ld-maxq/paddr.s
    ld/testsuite/ld-maxq/paddr1.dd
    ld/testsuite/ld-maxq/paddr1.s
    ld/testsuite/ld-maxq/r32-1.s
    ld/testsuite/ld-maxq/r32-2.s
    ld/testsuite/ld-maxq/r32.dd
    ld/testsuite/ld-mips-elf/branch-misc-1.d
    ld/testsuite/ld-mips-elf/eh-frame1-n32.d
    ld/testsuite/ld-mips-elf/eh-frame1-n64.d
    ld/testsuite/ld-mips-elf/eh-frame1.ld
    ld/testsuite/ld-mips-elf/eh-frame1.s
    ld/testsuite/ld-mips-elf/eh-frame2-n32.d
    ld/testsuite/ld-mips-elf/eh-frame2-n64.d
    ld/testsuite/ld-mips-elf/eh-frame3.d
    ld/testsuite/ld-mips-elf/eh-frame4.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n32.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n64.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d
    ld/testsuite/ld-mips-elf/emit-relocs-1.d
    ld/testsuite/ld-mips-elf/emit-relocs-1.ld
    ld/testsuite/ld-mips-elf/emit-relocs-1a.s
    ld/testsuite/ld-mips-elf/emit-relocs-1b.s
    ld/testsuite/ld-mips-elf/jalbal.d
    ld/testsuite/ld-mips-elf/jalbal.s
    ld/testsuite/ld-mips-elf/jaloverflow-2.d
    ld/testsuite/ld-mips-elf/jaloverflow-2.s
    ld/testsuite/ld-mips-elf/jaloverflow.d
    ld/testsuite/ld-mips-elf/jaloverflow.s
    ld/testsuite/ld-mips-elf/jr.s
    ld/testsuite/ld-mips-elf/mips-dyn.ld
    ld/testsuite/ld-mips-elf/mips-elf-flags.exp
    ld/testsuite/ld-mips-elf/mips-elf.exp
    ld/testsuite/ld-mips-elf/mips-lib.ld
    ld/testsuite/ld-mips-elf/mips16-1.d
    ld/testsuite/ld-mips-elf/mips16-1a.s
    ld/testsuite/ld-mips-elf/mips16-1b.s
    ld/testsuite/ld-mips-elf/mips16-call-global-1.s
    ld/testsuite/ld-mips-elf/mips16-call-global-2.s
    ld/testsuite/ld-mips-elf/mips16-call-global-3.s
    ld/testsuite/ld-mips-elf/mips16-call-global.d
    ld/testsuite/ld-mips-elf/mips16-hilo-n32.d
    ld/testsuite/ld-mips-elf/mips16-hilo.d
    ld/testsuite/ld-mips-elf/mips16-hilo.ld
    ld/testsuite/ld-mips-elf/mips16-hilo.s
    ld/testsuite/ld-mips-elf/multi-got-1-1.s
    ld/testsuite/ld-mips-elf/multi-got-1-2.s
    ld/testsuite/ld-mips-elf/multi-got-1.d
    ld/testsuite/ld-mips-elf/multi-got-no-shared-1.s
    ld/testsuite/ld-mips-elf/multi-got-no-shared-2.s
    ld/testsuite/ld-mips-elf/multi-got-no-shared.d
    ld/testsuite/ld-mips-elf/region1.d
    ld/testsuite/ld-mips-elf/region1.t
    ld/testsuite/ld-mips-elf/region1a.s
    ld/testsuite/ld-mips-elf/region1b.s
    ld/testsuite/ld-mips-elf/rel32-n32.d
    ld/testsuite/ld-mips-elf/rel32-o32.d
    ld/testsuite/ld-mips-elf/rel32.s
    ld/testsuite/ld-mips-elf/rel64.d
    ld/testsuite/ld-mips-elf/rel64.s
    ld/testsuite/ld-mips-elf/relax-jalr-n32-shared.d
    ld/testsuite/ld-mips-elf/relax-jalr-n32.d
    ld/testsuite/ld-mips-elf/relax-jalr-n64-shared.d
    ld/testsuite/ld-mips-elf/relax-jalr-n64.d
    ld/testsuite/ld-mips-elf/relax-jalr.s
    ld/testsuite/ld-mips-elf/reloc-1-n32.d
    ld/testsuite/ld-mips-elf/reloc-1-n64.d
    ld/testsuite/ld-mips-elf/reloc-1-rel.d
    ld/testsuite/ld-mips-elf/reloc-1a.s
    ld/testsuite/ld-mips-elf/reloc-1b.s
    ld/testsuite/ld-mips-elf/reloc-2.d
    ld/testsuite/ld-mips-elf/reloc-2.ld
    ld/testsuite/ld-mips-elf/reloc-2a.s
    ld/testsuite/ld-mips-elf/reloc-2b.s
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.d
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.ld
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.s
    ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1.ld
    ld/testsuite/ld-mips-elf/stub-dynsym-1.s
    ld/testsuite/ld-mips-elf/textrel-1.d
    ld/testsuite/ld-mips-elf/textrel-1.s
    ld/testsuite/ld-mips-elf/tls-hidden2-got.d
    ld/testsuite/ld-mips-elf/tls-hidden2.d
    ld/testsuite/ld-mips-elf/tls-hidden2a.s
    ld/testsuite/ld-mips-elf/tls-hidden2b.s
    ld/testsuite/ld-mips-elf/tls-hidden3.d
    ld/testsuite/ld-mips-elf/tls-hidden3.got
    ld/testsuite/ld-mips-elf/tls-hidden3.ld
    ld/testsuite/ld-mips-elf/tls-hidden3.r
    ld/testsuite/ld-mips-elf/tls-hidden3a.s
    ld/testsuite/ld-mips-elf/tls-hidden3b.s
    ld/testsuite/ld-mips-elf/tls-hidden4.got
    ld/testsuite/ld-mips-elf/tls-hidden4.r
    ld/testsuite/ld-mips-elf/tls-hidden4a.s
    ld/testsuite/ld-mips-elf/tls-hidden4b.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1-1.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1-2.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1.d
    ld/testsuite/ld-mips-elf/tls-multi-got-1.got
    ld/testsuite/ld-mips-elf/tls-multi-got-1.r
    ld/testsuite/ld-mips-elf/tlsbin-o32.d
    ld/testsuite/ld-mips-elf/tlsbin-o32.got
    ld/testsuite/ld-mips-elf/tlsbin-o32.s
    ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-1.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.s
    ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-3.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32.s
    ld/testsuite/ld-mips-elf/tlslib-hidden.ver
    ld/testsuite/ld-mips-elf/tlslib-o32-hidden.got
    ld/testsuite/ld-mips-elf/tlslib-o32-ver.got
    ld/testsuite/ld-mips-elf/tlslib-o32.d
    ld/testsuite/ld-mips-elf/tlslib-o32.got
    ld/testsuite/ld-mips-elf/tlslib-o32.s
    ld/testsuite/ld-mips-elf/tlslib.ver
    ld/testsuite/ld-mips-elf/vxworks1-lib.dd
    ld/testsuite/ld-mips-elf/vxworks1-lib.nd
    ld/testsuite/ld-mips-elf/vxworks1-lib.rd
    ld/testsuite/ld-mips-elf/vxworks1-lib.s
    ld/testsuite/ld-mips-elf/vxworks1-static.d
    ld/testsuite/ld-mips-elf/vxworks1.dd
    ld/testsuite/ld-mips-elf/vxworks1.ld
    ld/testsuite/ld-mips-elf/vxworks1.rd
    ld/testsuite/ld-mips-elf/vxworks1.s
    ld/testsuite/ld-mips-elf/vxworks2-static.sd
    ld/testsuite/ld-mips-elf/vxworks2.s
    ld/testsuite/ld-mips-elf/vxworks2.sd
    ld/testsuite/ld-mmix/a.s
    ld/testsuite/ld-mmix/areg-256.s
    ld/testsuite/ld-mmix/areg-t.s
    ld/testsuite/ld-mmix/aregm.s
    ld/testsuite/ld-mmix/b-badfil1.d
    ld/testsuite/ld-mmix/b-badfil1.s
    ld/testsuite/ld-mmix/b-badfil2.d
    ld/testsuite/ld-mmix/b-badfil2.s
    ld/testsuite/ld-mmix/b-badfixo.d
    ld/testsuite/ld-mmix/b-badfixo.s
    ld/testsuite/ld-mmix/b-badloc.d
    ld/testsuite/ld-mmix/b-badloc.s
    ld/testsuite/ld-mmix/b-badlop.d
    ld/testsuite/ld-mmix/b-badlop.s
    ld/testsuite/ld-mmix/b-badm.d
    ld/testsuite/ld-mmix/b-badm2.s
    ld/testsuite/ld-mmix/b-badmain.s
    ld/testsuite/ld-mmix/b-badquot.d
    ld/testsuite/ld-mmix/b-badquot.s
    ld/testsuite/ld-mmix/b-badrx1.d
    ld/testsuite/ld-mmix/b-badrx1.s
    ld/testsuite/ld-mmix/b-badrx2.d
    ld/testsuite/ld-mmix/b-badrx2.s
    ld/testsuite/ld-mmix/b-badrx3.d
    ld/testsuite/ld-mmix/b-badrx3.s
    ld/testsuite/ld-mmix/b-bend.s
    ld/testsuite/ld-mmix/b-bend1.d
    ld/testsuite/ld-mmix/b-bend2.d
    ld/testsuite/ld-mmix/b-bend3.d
    ld/testsuite/ld-mmix/b-bstab1.d
    ld/testsuite/ld-mmix/b-bstab1.s
    ld/testsuite/ld-mmix/b-fixo2.d
    ld/testsuite/ld-mmix/b-fixo2.s
    ld/testsuite/ld-mmix/b-goodmain.s
    ld/testsuite/ld-mmix/b-loc64k.d
    ld/testsuite/ld-mmix/b-loc64k.s
    ld/testsuite/ld-mmix/b-nosym.d
    ld/testsuite/ld-mmix/b-nosym.s
    ld/testsuite/ld-mmix/b-offloc.s
    ld/testsuite/ld-mmix/b-post1.s
    ld/testsuite/ld-mmix/b-twoinsn.s
    ld/testsuite/ld-mmix/b-widec.s
    ld/testsuite/ld-mmix/b-widec1.d
    ld/testsuite/ld-mmix/b-widec2.d
    ld/testsuite/ld-mmix/b-widec2.s
    ld/testsuite/ld-mmix/b-widec3.d
    ld/testsuite/ld-mmix/b-widec3.s
    ld/testsuite/ld-mmix/bpo-1.d
    ld/testsuite/ld-mmix/bpo-1.s
    ld/testsuite/ld-mmix/bpo-10.d
    ld/testsuite/ld-mmix/bpo-10.s
    ld/testsuite/ld-mmix/bpo-11.d
    ld/testsuite/ld-mmix/bpo-11.s
    ld/testsuite/ld-mmix/bpo-12.d
    ld/testsuite/ld-mmix/bpo-12m.d
    ld/testsuite/ld-mmix/bpo-13.d
    ld/testsuite/ld-mmix/bpo-13m.d
    ld/testsuite/ld-mmix/bpo-14.d
    ld/testsuite/ld-mmix/bpo-14m.d
    ld/testsuite/ld-mmix/bpo-15.d
    ld/testsuite/ld-mmix/bpo-15m.d
    ld/testsuite/ld-mmix/bpo-16.d
    ld/testsuite/ld-mmix/bpo-16m.d
    ld/testsuite/ld-mmix/bpo-17.d
    ld/testsuite/ld-mmix/bpo-17m.d
    ld/testsuite/ld-mmix/bpo-18.d
    ld/testsuite/ld-mmix/bpo-18m.d
    ld/testsuite/ld-mmix/bpo-19.d
    ld/testsuite/ld-mmix/bpo-19m.d
    ld/testsuite/ld-mmix/bpo-1m.d
    ld/testsuite/ld-mmix/bpo-2.d
    ld/testsuite/ld-mmix/bpo-2.s
    ld/testsuite/ld-mmix/bpo-20.d
    ld/testsuite/ld-mmix/bpo-20m.d
    ld/testsuite/ld-mmix/bpo-21.d
    ld/testsuite/ld-mmix/bpo-21m.d
    ld/testsuite/ld-mmix/bpo-22.d
    ld/testsuite/ld-mmix/bpo-2m.d
    ld/testsuite/ld-mmix/bpo-3.d
    ld/testsuite/ld-mmix/bpo-3.s
    ld/testsuite/ld-mmix/bpo-3m.d
    ld/testsuite/ld-mmix/bpo-4.d
    ld/testsuite/ld-mmix/bpo-4.s
    ld/testsuite/ld-mmix/bpo-4m.d
    ld/testsuite/ld-mmix/bpo-5.d
    ld/testsuite/ld-mmix/bpo-5.s
    ld/testsuite/ld-mmix/bpo-5m.d
    ld/testsuite/ld-mmix/bpo-6.d
    ld/testsuite/ld-mmix/bpo-6.s
    ld/testsuite/ld-mmix/bpo-6m.d
    ld/testsuite/ld-mmix/bpo-7.d
    ld/testsuite/ld-mmix/bpo-7.s
    ld/testsuite/ld-mmix/bpo-7m.d
    ld/testsuite/ld-mmix/bpo-8.d
    ld/testsuite/ld-mmix/bpo-8.s
    ld/testsuite/ld-mmix/bpo-8m.d
    ld/testsuite/ld-mmix/bpo-9.d
    ld/testsuite/ld-mmix/bpo-9.s
    ld/testsuite/ld-mmix/bpo-9m.d
    ld/testsuite/ld-mmix/bpo64addr.ld
    ld/testsuite/ld-mmix/bspec1.d
    ld/testsuite/ld-mmix/bspec1.s
    ld/testsuite/ld-mmix/bspec1m.d
    ld/testsuite/ld-mmix/bspec2.d
    ld/testsuite/ld-mmix/bspec2.s
    ld/testsuite/ld-mmix/bspec2m.d
    ld/testsuite/ld-mmix/bspec801.s
    ld/testsuite/ld-mmix/bspec802.s
    ld/testsuite/ld-mmix/bspec803.s
    ld/testsuite/ld-mmix/bspec804.s
    ld/testsuite/ld-mmix/bspec805.s
    ld/testsuite/ld-mmix/bspec806.s
    ld/testsuite/ld-mmix/bspec807.s
    ld/testsuite/ld-mmix/bspec808.s
    ld/testsuite/ld-mmix/bza-1b.d
    ld/testsuite/ld-mmix/bza-1f.d
    ld/testsuite/ld-mmix/bza-2b.d
    ld/testsuite/ld-mmix/bza-2f.d
    ld/testsuite/ld-mmix/bza-7b.d
    ld/testsuite/ld-mmix/bza-7f.d
    ld/testsuite/ld-mmix/bza-8b.d
    ld/testsuite/ld-mmix/bza-8f.d
    ld/testsuite/ld-mmix/bza.s
    ld/testsuite/ld-mmix/data1.s
    ld/testsuite/ld-mmix/dloc1.s
    ld/testsuite/ld-mmix/dloc2.s
    ld/testsuite/ld-mmix/ext1-254.s
    ld/testsuite/ld-mmix/ext1.s
    ld/testsuite/ld-mmix/ext1g.s
    ld/testsuite/ld-mmix/ext1l.s
    ld/testsuite/ld-mmix/getaa-1b.d
    ld/testsuite/ld-mmix/getaa-1f.d
    ld/testsuite/ld-mmix/getaa-2b.d
    ld/testsuite/ld-mmix/getaa-2f.d
    ld/testsuite/ld-mmix/getaa-4b.d
    ld/testsuite/ld-mmix/getaa-4f.d
    ld/testsuite/ld-mmix/getaa-6b.d
    ld/testsuite/ld-mmix/getaa-6f.d
    ld/testsuite/ld-mmix/getaa-7b.d
    ld/testsuite/ld-mmix/getaa-7f.d
    ld/testsuite/ld-mmix/getaa-8b.d
    ld/testsuite/ld-mmix/getaa-8f.d
    ld/testsuite/ld-mmix/getaa.s
    ld/testsuite/ld-mmix/getaa12b.d
    ld/testsuite/ld-mmix/getaa12f.d
    ld/testsuite/ld-mmix/getaa14b.d
    ld/testsuite/ld-mmix/getaa14f.d
    ld/testsuite/ld-mmix/greg-1.d
    ld/testsuite/ld-mmix/greg-1.s
    ld/testsuite/ld-mmix/greg-10.d
    ld/testsuite/ld-mmix/greg-11.d
    ld/testsuite/ld-mmix/greg-11b.d
    ld/testsuite/ld-mmix/greg-12.d
    ld/testsuite/ld-mmix/greg-13.d
    ld/testsuite/ld-mmix/greg-14.d
    ld/testsuite/ld-mmix/greg-14s.d
    ld/testsuite/ld-mmix/greg-15.d
    ld/testsuite/ld-mmix/greg-16.d
    ld/testsuite/ld-mmix/greg-17.d
    ld/testsuite/ld-mmix/greg-18.d
    ld/testsuite/ld-mmix/greg-19.d
    ld/testsuite/ld-mmix/greg-2.d
    ld/testsuite/ld-mmix/greg-2.s
    ld/testsuite/ld-mmix/greg-20.d
    ld/testsuite/ld-mmix/greg-3.d
    ld/testsuite/ld-mmix/greg-3.s
    ld/testsuite/ld-mmix/greg-4.d
    ld/testsuite/ld-mmix/greg-4.s
    ld/testsuite/ld-mmix/greg-5.d
    ld/testsuite/ld-mmix/greg-5.s
    ld/testsuite/ld-mmix/greg-5s.d
    ld/testsuite/ld-mmix/greg-6.d
    ld/testsuite/ld-mmix/greg-7.d
    ld/testsuite/ld-mmix/greg-8.d
    ld/testsuite/ld-mmix/greg-9.d
    ld/testsuite/ld-mmix/gregbza1.s
    ld/testsuite/ld-mmix/gregget1.s
    ld/testsuite/ld-mmix/gregget2.s
    ld/testsuite/ld-mmix/gregldo1.s
    ld/testsuite/ld-mmix/gregpsj1.s
    ld/testsuite/ld-mmix/hdr-1.d
    ld/testsuite/ld-mmix/jumpa-1b.d
    ld/testsuite/ld-mmix/jumpa-1f.d
    ld/testsuite/ld-mmix/jumpa-2b.d
    ld/testsuite/ld-mmix/jumpa-2f.d
    ld/testsuite/ld-mmix/jumpa-3b.d
    ld/testsuite/ld-mmix/jumpa-3f.d
    ld/testsuite/ld-mmix/jumpa-4b.d
    ld/testsuite/ld-mmix/jumpa-4f.d
    ld/testsuite/ld-mmix/jumpa-5b.d
    ld/testsuite/ld-mmix/jumpa-5f.d
    ld/testsuite/ld-mmix/jumpa-6b.d
    ld/testsuite/ld-mmix/jumpa-6f.d
    ld/testsuite/ld-mmix/jumpa-7b.d
    ld/testsuite/ld-mmix/jumpa-7f.d
    ld/testsuite/ld-mmix/jumpa-8b.d
    ld/testsuite/ld-mmix/jumpa-8f.d
    ld/testsuite/ld-mmix/jumpa-9b.d
    ld/testsuite/ld-mmix/jumpa-9f.d
    ld/testsuite/ld-mmix/jumpa.s
    ld/testsuite/ld-mmix/jumpa12b.d
    ld/testsuite/ld-mmix/jumpa12f.d
    ld/testsuite/ld-mmix/jumpa13b.d
    ld/testsuite/ld-mmix/jumpa13f.d
    ld/testsuite/ld-mmix/jumpa14b.d
    ld/testsuite/ld-mmix/jumpa14f.d
    ld/testsuite/ld-mmix/loc1.d
    ld/testsuite/ld-mmix/loc1.s
    ld/testsuite/ld-mmix/loc1m.d
    ld/testsuite/ld-mmix/loc2.d
    ld/testsuite/ld-mmix/loc2.s
    ld/testsuite/ld-mmix/loc2m.d
    ld/testsuite/ld-mmix/loc3.d
    ld/testsuite/ld-mmix/loc3m.d
    ld/testsuite/ld-mmix/loc4.d
    ld/testsuite/ld-mmix/loc4m.d
    ld/testsuite/ld-mmix/loc5.d
    ld/testsuite/ld-mmix/loc5m.d
    ld/testsuite/ld-mmix/loc6.d
    ld/testsuite/ld-mmix/loc6m.d
    ld/testsuite/ld-mmix/loc7.d
    ld/testsuite/ld-mmix/loc7m.d
    ld/testsuite/ld-mmix/local1.d
    ld/testsuite/ld-mmix/local1.s
    ld/testsuite/ld-mmix/local10.d
    ld/testsuite/ld-mmix/local10m.d
    ld/testsuite/ld-mmix/local11.d
    ld/testsuite/ld-mmix/local11m.d
    ld/testsuite/ld-mmix/local12.d
    ld/testsuite/ld-mmix/local12m.d
    ld/testsuite/ld-mmix/local1m.d
    ld/testsuite/ld-mmix/local2.d
    ld/testsuite/ld-mmix/local2.s
    ld/testsuite/ld-mmix/local2m.d
    ld/testsuite/ld-mmix/local3.d
    ld/testsuite/ld-mmix/local3m.d
    ld/testsuite/ld-mmix/local4.d
    ld/testsuite/ld-mmix/local4m.d
    ld/testsuite/ld-mmix/local5.d
    ld/testsuite/ld-mmix/local5m.d
    ld/testsuite/ld-mmix/local6.d
    ld/testsuite/ld-mmix/local6m.d
    ld/testsuite/ld-mmix/local7.d
    ld/testsuite/ld-mmix/local7m.d
    ld/testsuite/ld-mmix/local8.d
    ld/testsuite/ld-mmix/local8m.d
    ld/testsuite/ld-mmix/local9.d
    ld/testsuite/ld-mmix/local9m.d
    ld/testsuite/ld-mmix/locdo-1.d
    ld/testsuite/ld-mmix/locdo.s
    ld/testsuite/ld-mmix/loct-1.d
    ld/testsuite/ld-mmix/loct.s
    ld/testsuite/ld-mmix/locto-1.d
    ld/testsuite/ld-mmix/locto.s
    ld/testsuite/ld-mmix/main1.s
    ld/testsuite/ld-mmix/mmix.exp
    ld/testsuite/ld-mmix/mmohdr1.ld
    ld/testsuite/ld-mmix/mmosec1.ld
    ld/testsuite/ld-mmix/mmosec2.ld
    ld/testsuite/ld-mmix/nop123.s
    ld/testsuite/ld-mmix/pad16.s
    ld/testsuite/ld-mmix/pad2p18m32.s
    ld/testsuite/ld-mmix/pad2p26m32.s
    ld/testsuite/ld-mmix/pad4.s
    ld/testsuite/ld-mmix/pushja.s
    ld/testsuite/ld-mmix/pushja1b-s.d
    ld/testsuite/ld-mmix/pushja1b.d
    ld/testsuite/ld-mmix/pushja1f-s.d
    ld/testsuite/ld-mmix/pushja1f.d
    ld/testsuite/ld-mmix/pushja2b.d
    ld/testsuite/ld-mmix/pushja2f.d
    ld/testsuite/ld-mmix/pushja7b-s.d
    ld/testsuite/ld-mmix/pushja7b.d
    ld/testsuite/ld-mmix/pushja7f-s.d
    ld/testsuite/ld-mmix/pushja7f.d
    ld/testsuite/ld-mmix/pushja8b.d
    ld/testsuite/ld-mmix/pushja8f.d
    ld/testsuite/ld-mmix/pushjs1.d
    ld/testsuite/ld-mmix/pushjs1b.d
    ld/testsuite/ld-mmix/pushjs1bm.d
    ld/testsuite/ld-mmix/pushjs1m.d
    ld/testsuite/ld-mmix/pushjs1r.d
    ld/testsuite/ld-mmix/pushjs2.d
    ld/testsuite/ld-mmix/pushjs2b.d
    ld/testsuite/ld-mmix/pushjs2bm.d
    ld/testsuite/ld-mmix/pushjs2m.d
    ld/testsuite/ld-mmix/pushjs2r.d
    ld/testsuite/ld-mmix/pushjs3.d
    ld/testsuite/ld-mmix/pushjs3b.d
    ld/testsuite/ld-mmix/pushjs3bm.d
    ld/testsuite/ld-mmix/pushjs3m.d
    ld/testsuite/ld-mmix/pushjs3r.d
    ld/testsuite/ld-mmix/pushjs4.d
    ld/testsuite/ld-mmix/pushjs4b.d
    ld/testsuite/ld-mmix/pushjs4bm.d
    ld/testsuite/ld-mmix/pushjs4m.d
    ld/testsuite/ld-mmix/pushjs4r.d
    ld/testsuite/ld-mmix/reg-1.d
    ld/testsuite/ld-mmix/reg-1m.d
    ld/testsuite/ld-mmix/reg-2.d
    ld/testsuite/ld-mmix/reg-2m.d
    ld/testsuite/ld-mmix/regext1.s
    ld/testsuite/ld-mmix/sec-1.d
    ld/testsuite/ld-mmix/sec-1.s
    ld/testsuite/ld-mmix/sec-2.d
    ld/testsuite/ld-mmix/sec-2.s
    ld/testsuite/ld-mmix/sec-3.d
    ld/testsuite/ld-mmix/sec-4.d
    ld/testsuite/ld-mmix/sec-5.d
    ld/testsuite/ld-mmix/sec-6.d
    ld/testsuite/ld-mmix/sec-6.s
    ld/testsuite/ld-mmix/sec-6m.d
    ld/testsuite/ld-mmix/sec-7a.s
    ld/testsuite/ld-mmix/sec-7b.s
    ld/testsuite/ld-mmix/sec-7c.s
    ld/testsuite/ld-mmix/sec-7d.s
    ld/testsuite/ld-mmix/sec-7e.s
    ld/testsuite/ld-mmix/sec-7m.d
    ld/testsuite/ld-mmix/sec-8a.s
    ld/testsuite/ld-mmix/sec-8b.s
    ld/testsuite/ld-mmix/sec-8d.s
    ld/testsuite/ld-mmix/sec-8m.d
    ld/testsuite/ld-mmix/sec-8m.s
    ld/testsuite/ld-mmix/sec-9.d
    ld/testsuite/ld-mmix/spec801.d
    ld/testsuite/ld-mmix/spec802.d
    ld/testsuite/ld-mmix/spec803.d
    ld/testsuite/ld-mmix/spec804.d
    ld/testsuite/ld-mmix/spec805.d
    ld/testsuite/ld-mmix/spec806.d
    ld/testsuite/ld-mmix/spec807.d
    ld/testsuite/ld-mmix/spec808.d
    ld/testsuite/ld-mmix/start-1.d
    ld/testsuite/ld-mmix/start-2.d
    ld/testsuite/ld-mmix/start.s
    ld/testsuite/ld-mmix/start2.s
    ld/testsuite/ld-mmix/start3.s
    ld/testsuite/ld-mmix/start4.s
    ld/testsuite/ld-mmix/sym-1.d
    ld/testsuite/ld-mmix/sym-2.d
    ld/testsuite/ld-mmix/sym-2.s
    ld/testsuite/ld-mmix/undef-1.d
    ld/testsuite/ld-mmix/undef-1.s
    ld/testsuite/ld-mmix/undef-1m.d
    ld/testsuite/ld-mmix/undef-2.d
    ld/testsuite/ld-mmix/undef-2.s
    ld/testsuite/ld-mmix/undef-2m.d
    ld/testsuite/ld-mmix/undef-3.d
    ld/testsuite/ld-mmix/undef-3m.d
    ld/testsuite/ld-mmix/x.s
    ld/testsuite/ld-mmix/y.s
    ld/testsuite/ld-mmix/zeroeh.ld
    ld/testsuite/ld-mmix/zeroehelf.d
    ld/testsuite/ld-mmix/zeroehmmo.d
    ld/testsuite/ld-pe/pe.exp
    ld/testsuite/ld-pe/secrel.d
    ld/testsuite/ld-pe/secrel1.s
    ld/testsuite/ld-pe/secrel2.s
    ld/testsuite/ld-pie/pie.c
    ld/testsuite/ld-pie/pie.exp
    ld/testsuite/ld-pie/weakundef-data.c
    ld/testsuite/ld-pie/weakundef.c
    ld/testsuite/ld-pie/weakundef.out
    ld/testsuite/ld-powerpc/apuinfo.rd
    ld/testsuite/ld-powerpc/apuinfo1.s
    ld/testsuite/ld-powerpc/apuinfo2.s
    ld/testsuite/ld-powerpc/powerpc.exp
    ld/testsuite/ld-powerpc/reloc.d
    ld/testsuite/ld-powerpc/reloc.s
    ld/testsuite/ld-powerpc/sdadyn.d
    ld/testsuite/ld-powerpc/sdadyn.s
    ld/testsuite/ld-powerpc/sdalib.s
    ld/testsuite/ld-powerpc/symtocbase-1.s
    ld/testsuite/ld-powerpc/symtocbase-2.s
    ld/testsuite/ld-powerpc/symtocbase.d
    ld/testsuite/ld-powerpc/tls.d
    ld/testsuite/ld-powerpc/tls.g
    ld/testsuite/ld-powerpc/tls.s
    ld/testsuite/ld-powerpc/tls.t
    ld/testsuite/ld-powerpc/tls32.d
    ld/testsuite/ld-powerpc/tls32.g
    ld/testsuite/ld-powerpc/tls32.s
    ld/testsuite/ld-powerpc/tls32.t
    ld/testsuite/ld-powerpc/tlsexe.d
    ld/testsuite/ld-powerpc/tlsexe.g
    ld/testsuite/ld-powerpc/tlsexe.r
    ld/testsuite/ld-powerpc/tlsexe.t
    ld/testsuite/ld-powerpc/tlsexe32.d
    ld/testsuite/ld-powerpc/tlsexe32.g
    ld/testsuite/ld-powerpc/tlsexe32.r
    ld/testsuite/ld-powerpc/tlsexe32.t
    ld/testsuite/ld-powerpc/tlsexetoc.d
    ld/testsuite/ld-powerpc/tlsexetoc.g
    ld/testsuite/ld-powerpc/tlsexetoc.r
    ld/testsuite/ld-powerpc/tlsexetoc.t
    ld/testsuite/ld-powerpc/tlslib.s
    ld/testsuite/ld-powerpc/tlslib32.s
    ld/testsuite/ld-powerpc/tlsso.d
    ld/testsuite/ld-powerpc/tlsso.g
    ld/testsuite/ld-powerpc/tlsso.r
    ld/testsuite/ld-powerpc/tlsso.t
    ld/testsuite/ld-powerpc/tlsso32.d
    ld/testsuite/ld-powerpc/tlsso32.g
    ld/testsuite/ld-powerpc/tlsso32.r
    ld/testsuite/ld-powerpc/tlsso32.t
    ld/testsuite/ld-powerpc/tlstoc.d
    ld/testsuite/ld-powerpc/tlstoc.g
    ld/testsuite/ld-powerpc/tlstoc.s
    ld/testsuite/ld-powerpc/tlstoc.t
    ld/testsuite/ld-powerpc/tlstocso.d
    ld/testsuite/ld-powerpc/tlstocso.g
    ld/testsuite/ld-powerpc/tlstocso.r
    ld/testsuite/ld-powerpc/tlstocso.t
    ld/testsuite/ld-powerpc/vxworks1-lib.dd
    ld/testsuite/ld-powerpc/vxworks1-lib.nd
    ld/testsuite/ld-powerpc/vxworks1-lib.rd
    ld/testsuite/ld-powerpc/vxworks1-lib.s
    ld/testsuite/ld-powerpc/vxworks1-lib.sd
    ld/testsuite/ld-powerpc/vxworks1-static.d
    ld/testsuite/ld-powerpc/vxworks1.dd
    ld/testsuite/ld-powerpc/vxworks1.ld
    ld/testsuite/ld-powerpc/vxworks1.rd
    ld/testsuite/ld-powerpc/vxworks1.s
    ld/testsuite/ld-powerpc/vxworks2-static.sd
    ld/testsuite/ld-powerpc/vxworks2.s
    ld/testsuite/ld-powerpc/vxworks2.sd
    ld/testsuite/ld-s390/s390.exp
    ld/testsuite/ld-s390/tlsbin.dd
    ld/testsuite/ld-s390/tlsbin.rd
    ld/testsuite/ld-s390/tlsbin.s
    ld/testsuite/ld-s390/tlsbin.sd
    ld/testsuite/ld-s390/tlsbin.td
    ld/testsuite/ld-s390/tlsbin_64.dd
    ld/testsuite/ld-s390/tlsbin_64.rd
    ld/testsuite/ld-s390/tlsbin_64.s
    ld/testsuite/ld-s390/tlsbin_64.sd
    ld/testsuite/ld-s390/tlsbin_64.td
    ld/testsuite/ld-s390/tlsbinpic.s
    ld/testsuite/ld-s390/tlsbinpic_64.s
    ld/testsuite/ld-s390/tlslib.s
    ld/testsuite/ld-s390/tlslib_64.s
    ld/testsuite/ld-s390/tlspic.dd
    ld/testsuite/ld-s390/tlspic.rd
    ld/testsuite/ld-s390/tlspic.sd
    ld/testsuite/ld-s390/tlspic.td
    ld/testsuite/ld-s390/tlspic1.s
    ld/testsuite/ld-s390/tlspic1_64.s
    ld/testsuite/ld-s390/tlspic2.s
    ld/testsuite/ld-s390/tlspic2_64.s
    ld/testsuite/ld-s390/tlspic_64.dd
    ld/testsuite/ld-s390/tlspic_64.rd
    ld/testsuite/ld-s390/tlspic_64.sd
    ld/testsuite/ld-s390/tlspic_64.td
    ld/testsuite/ld-scripts/align.exp
    ld/testsuite/ld-scripts/align.s
    ld/testsuite/ld-scripts/align.t
    ld/testsuite/ld-scripts/align2.t
    ld/testsuite/ld-scripts/align2a.d
    ld/testsuite/ld-scripts/align2a.s
    ld/testsuite/ld-scripts/align2b.d
    ld/testsuite/ld-scripts/align2b.s
    ld/testsuite/ld-scripts/align2c.d
    ld/testsuite/ld-scripts/align2c.s
    ld/testsuite/ld-scripts/assert.exp
    ld/testsuite/ld-scripts/assert.s
    ld/testsuite/ld-scripts/assert.t
    ld/testsuite/ld-scripts/cross1.c
    ld/testsuite/ld-scripts/cross1.t
    ld/testsuite/ld-scripts/cross2.c
    ld/testsuite/ld-scripts/cross2.t
    ld/testsuite/ld-scripts/cross3.c
    ld/testsuite/ld-scripts/cross3.t
    ld/testsuite/ld-scripts/cross4.c
    ld/testsuite/ld-scripts/crossref.exp
    ld/testsuite/ld-scripts/data.d
    ld/testsuite/ld-scripts/data.exp
    ld/testsuite/ld-scripts/data.s
    ld/testsuite/ld-scripts/data.t
    ld/testsuite/ld-scripts/defined.exp
    ld/testsuite/ld-scripts/defined.s
    ld/testsuite/ld-scripts/defined.t
    ld/testsuite/ld-scripts/defined2.d
    ld/testsuite/ld-scripts/defined2.t
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    ld/testsuite/ld-scripts/dynamic-sections-2.s
    ld/testsuite/ld-scripts/dynamic-sections.d
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    ld/testsuite/ld-scripts/empty-aligned.exp
    ld/testsuite/ld-scripts/empty-aligned.s
    ld/testsuite/ld-scripts/empty-aligned.t
    ld/testsuite/ld-scripts/empty-orphan.d
    ld/testsuite/ld-scripts/empty-orphan.exp
    ld/testsuite/ld-scripts/empty-orphan.s
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    ld/testsuite/ld-scripts/map-address.exp
    ld/testsuite/ld-scripts/map-address.t
    ld/testsuite/ld-scripts/memory.t
    ld/testsuite/ld-scripts/overlay-size-map.d
    ld/testsuite/ld-scripts/overlay-size.d
    ld/testsuite/ld-scripts/overlay-size.exp
    ld/testsuite/ld-scripts/overlay-size.s
    ld/testsuite/ld-scripts/overlay-size.t
    ld/testsuite/ld-scripts/phdrs.exp
    ld/testsuite/ld-scripts/phdrs.s
    ld/testsuite/ld-scripts/phdrs.t
    ld/testsuite/ld-scripts/phdrs2.exp
    ld/testsuite/ld-scripts/phdrs2.s
    ld/testsuite/ld-scripts/phdrs2.t
    ld/testsuite/ld-scripts/provide-1.d
    ld/testsuite/ld-scripts/provide-1.s
    ld/testsuite/ld-scripts/provide-1.t
    ld/testsuite/ld-scripts/provide-2.d
    ld/testsuite/ld-scripts/provide-2.s
    ld/testsuite/ld-scripts/provide-2.t
    ld/testsuite/ld-scripts/provide-3.d
    ld/testsuite/ld-scripts/provide-3.s
    ld/testsuite/ld-scripts/provide-3.t
    ld/testsuite/ld-scripts/provide.exp
    ld/testsuite/ld-scripts/script.exp
    ld/testsuite/ld-scripts/script.s
    ld/testsuite/ld-scripts/script.t
    ld/testsuite/ld-scripts/scriptm.t
    ld/testsuite/ld-scripts/size-1.d
    ld/testsuite/ld-scripts/size-1.s
    ld/testsuite/ld-scripts/size-1.t
    ld/testsuite/ld-scripts/size-2.d
    ld/testsuite/ld-scripts/size-2.s
    ld/testsuite/ld-scripts/size-2.t
    ld/testsuite/ld-scripts/size.exp
    ld/testsuite/ld-scripts/sizeof.exp
    ld/testsuite/ld-scripts/sizeof.s
    ld/testsuite/ld-scripts/sizeof.t
    ld/testsuite/ld-scripts/sort.exp
    ld/testsuite/ld-scripts/sort_b_a.d
    ld/testsuite/ld-scripts/sort_b_a.s
    ld/testsuite/ld-scripts/sort_b_a.t
    ld/testsuite/ld-scripts/sort_b_a_a-1.d
    ld/testsuite/ld-scripts/sort_b_a_a-2.d
    ld/testsuite/ld-scripts/sort_b_a_a-3.d
    ld/testsuite/ld-scripts/sort_b_a_a.t
    ld/testsuite/ld-scripts/sort_b_a_n-1.d
    ld/testsuite/ld-scripts/sort_b_a_n-2.d
    ld/testsuite/ld-scripts/sort_b_a_n-3.d
    ld/testsuite/ld-scripts/sort_b_a_n.t
    ld/testsuite/ld-scripts/sort_b_n.d
    ld/testsuite/ld-scripts/sort_b_n.s
    ld/testsuite/ld-scripts/sort_b_n.t
    ld/testsuite/ld-scripts/sort_b_n_a-1.d
    ld/testsuite/ld-scripts/sort_b_n_a-2.d
    ld/testsuite/ld-scripts/sort_b_n_a-3.d
    ld/testsuite/ld-scripts/sort_b_n_a.t
    ld/testsuite/ld-scripts/sort_b_n_n-1.d
    ld/testsuite/ld-scripts/sort_b_n_n-2.d
    ld/testsuite/ld-scripts/sort_b_n_n-3.d
    ld/testsuite/ld-scripts/sort_b_n_n.t
    ld/testsuite/ld-scripts/sort_n_a-a.s
    ld/testsuite/ld-scripts/sort_n_a-b.s
    ld/testsuite/ld-scripts/sort_no-1.d
    ld/testsuite/ld-scripts/sort_no-2.d
    ld/testsuite/ld-scripts/sort_no.t
    ld/testsuite/ld-scripts/weak.exp
    ld/testsuite/ld-scripts/weak.t
    ld/testsuite/ld-scripts/weak1.s
    ld/testsuite/ld-scripts/weak2.s
    ld/testsuite/ld-selective/1.c
    ld/testsuite/ld-selective/2.c
    ld/testsuite/ld-selective/3.cc
    ld/testsuite/ld-selective/4.cc
    ld/testsuite/ld-selective/5.cc
    ld/testsuite/ld-selective/keepdot.d
    ld/testsuite/ld-selective/keepdot.ld
    ld/testsuite/ld-selective/keepdot.s
    ld/testsuite/ld-selective/keepdot0.d
    ld/testsuite/ld-selective/keepdot0.ld
    ld/testsuite/ld-selective/sel-dump.exp
    ld/testsuite/ld-selective/selective.exp
    ld/testsuite/ld-sh/arch/arch.exp
    ld/testsuite/ld-sh/arch/arch_expected.txt
    ld/testsuite/ld-sh/arch/sh-dsp.s
    ld/testsuite/ld-sh/arch/sh.s
    ld/testsuite/ld-sh/arch/sh2.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu.s
    ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s
    ld/testsuite/ld-sh/arch/sh2a-or-sh4.s
    ld/testsuite/ld-sh/arch/sh2a.s
    ld/testsuite/ld-sh/arch/sh2e.s
    ld/testsuite/ld-sh/arch/sh3-dsp.s
    ld/testsuite/ld-sh/arch/sh3-nommu.s
    ld/testsuite/ld-sh/arch/sh3.s
    ld/testsuite/ld-sh/arch/sh3e.s
    ld/testsuite/ld-sh/arch/sh4-nofpu.s
    ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s
    ld/testsuite/ld-sh/arch/sh4.s
    ld/testsuite/ld-sh/arch/sh4a-nofpu.s
    ld/testsuite/ld-sh/arch/sh4a.s
    ld/testsuite/ld-sh/arch/sh4al-dsp.s
    ld/testsuite/ld-sh/ld-r-1.d
    ld/testsuite/ld-sh/ldr1.s
    ld/testsuite/ld-sh/ldr2.s
    ld/testsuite/ld-sh/rd-sh.exp
    ld/testsuite/ld-sh/refdbg-0-dso.d
    ld/testsuite/ld-sh/refdbg-1.d
    ld/testsuite/ld-sh/refdbg.s
    ld/testsuite/ld-sh/refdbglib.s
    ld/testsuite/ld-sh/sh.exp
    ld/testsuite/ld-sh/sh1.s
    ld/testsuite/ld-sh/sh2.c
    ld/testsuite/ld-sh/sh64/abi32.sd
    ld/testsuite/ld-sh/sh64/abi32.xd
    ld/testsuite/ld-sh/sh64/abi64.sd
    ld/testsuite/ld-sh/sh64/abi64.xd
    ld/testsuite/ld-sh/sh64/abixx-noexp.sd
    ld/testsuite/ld-sh/sh64/cmpct1.sd
    ld/testsuite/ld-sh/sh64/cmpct1.xd
    ld/testsuite/ld-sh/sh64/crange-1.s
    ld/testsuite/ld-sh/sh64/crange-2a.s
    ld/testsuite/ld-sh/sh64/crange-2b.s
    ld/testsuite/ld-sh/sh64/crange-2c.s
    ld/testsuite/ld-sh/sh64/crange-2d.s
    ld/testsuite/ld-sh/sh64/crange-2e.s
    ld/testsuite/ld-sh/sh64/crange-2f.s
    ld/testsuite/ld-sh/sh64/crange-2g.s
    ld/testsuite/ld-sh/sh64/crange-2h.s
    ld/testsuite/ld-sh/sh64/crange-2i.s
    ld/testsuite/ld-sh/sh64/crange1.rd
    ld/testsuite/ld-sh/sh64/crange2.rd
    ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
    ld/testsuite/ld-sh/sh64/crange3-media.rd
    ld/testsuite/ld-sh/sh64/crange3.dd
    ld/testsuite/ld-sh/sh64/crange3.rd
    ld/testsuite/ld-sh/sh64/crangerel1.rd
    ld/testsuite/ld-sh/sh64/crangerel2.rd
    ld/testsuite/ld-sh/sh64/dlsection-1.s
    ld/testsuite/ld-sh/sh64/dlsection.sd
    ld/testsuite/ld-sh/sh64/endian.dbd
    ld/testsuite/ld-sh/sh64/endian.dld
    ld/testsuite/ld-sh/sh64/endian.ld
    ld/testsuite/ld-sh/sh64/endian.s
    ld/testsuite/ld-sh/sh64/endian.sbd
    ld/testsuite/ld-sh/sh64/endian.sld
    ld/testsuite/ld-sh/sh64/gotplt.d
    ld/testsuite/ld-sh/sh64/gotplt.map
    ld/testsuite/ld-sh/sh64/gotplt.s
    ld/testsuite/ld-sh/sh64/init-cmpct.d
    ld/testsuite/ld-sh/sh64/init-media.d
    ld/testsuite/ld-sh/sh64/init.s
    ld/testsuite/ld-sh/sh64/init64.d
    ld/testsuite/ld-sh/sh64/mix1-noexp.sd
    ld/testsuite/ld-sh/sh64/mix1.sd
    ld/testsuite/ld-sh/sh64/mix1.xd
    ld/testsuite/ld-sh/sh64/mix2-noexp.sd
    ld/testsuite/ld-sh/sh64/mix2.sd
    ld/testsuite/ld-sh/sh64/mix2.xd
    ld/testsuite/ld-sh/sh64/rd-sh64.exp
    ld/testsuite/ld-sh/sh64/rel-1.s
    ld/testsuite/ld-sh/sh64/rel-2.s
    ld/testsuite/ld-sh/sh64/rel32.xd
    ld/testsuite/ld-sh/sh64/rel64.xd
    ld/testsuite/ld-sh/sh64/relax.exp
    ld/testsuite/ld-sh/sh64/relax1.s
    ld/testsuite/ld-sh/sh64/relax2.s
    ld/testsuite/ld-sh/sh64/relax3.s
    ld/testsuite/ld-sh/sh64/relax4.s
    ld/testsuite/ld-sh/sh64/reldl-1.s
    ld/testsuite/ld-sh/sh64/reldl-2.s
    ld/testsuite/ld-sh/sh64/reldl32.rd
    ld/testsuite/ld-sh/sh64/reldl64.rd
    ld/testsuite/ld-sh/sh64/relfail.exp
    ld/testsuite/ld-sh/sh64/relfail.s
    ld/testsuite/ld-sh/sh64/sh64-1.s
    ld/testsuite/ld-sh/sh64/sh64-2.s
    ld/testsuite/ld-sh/sh64/sh64.exp
    ld/testsuite/ld-sh/sh64/shcmp-1.s
    ld/testsuite/ld-sh/sh64/shdl-1.s
    ld/testsuite/ld-sh/sh64/shdl-2.s
    ld/testsuite/ld-sh/sh64/shdl32.xd
    ld/testsuite/ld-sh/sh64/shdl64.sd
    ld/testsuite/ld-sh/sh64/shdl64.xd
    ld/testsuite/ld-sh/sh64/shmix-1.s
    ld/testsuite/ld-sh/sh64/shmix-2.s
    ld/testsuite/ld-sh/sh64/shmix-3.s
    ld/testsuite/ld-sh/sh64/stobin-0-dso.d
    ld/testsuite/ld-sh/sh64/stobin-1.d
    ld/testsuite/ld-sh/sh64/stobin.s
    ld/testsuite/ld-sh/sh64/stolib.s
    ld/testsuite/ld-sh/shared-1.d
    ld/testsuite/ld-sh/shared-2.d
    ld/testsuite/ld-sh/start.s
    ld/testsuite/ld-sh/sub2l-1.d
    ld/testsuite/ld-sh/sub2l.s
    ld/testsuite/ld-sh/textrel1.s
    ld/testsuite/ld-sh/textrel2.s
    ld/testsuite/ld-sh/tlsbin-0-dso.d
    ld/testsuite/ld-sh/tlsbin-1.d
    ld/testsuite/ld-sh/tlsbin-2.d
    ld/testsuite/ld-sh/tlsbin-3.d
    ld/testsuite/ld-sh/tlsbin-4.d
    ld/testsuite/ld-sh/tlsbin.s
    ld/testsuite/ld-sh/tlsbinpic.s
    ld/testsuite/ld-sh/tlslib.s
    ld/testsuite/ld-sh/tlspic-1.d
    ld/testsuite/ld-sh/tlspic-2.d
    ld/testsuite/ld-sh/tlspic-3.d
    ld/testsuite/ld-sh/tlspic-4.d
    ld/testsuite/ld-sh/tlspic1.s
    ld/testsuite/ld-sh/tlspic2.s
    ld/testsuite/ld-sh/tlstpoff-1.d
    ld/testsuite/ld-sh/tlstpoff-2.d
    ld/testsuite/ld-sh/tlstpoff1.s
    ld/testsuite/ld-sh/tlstpoff2.s
    ld/testsuite/ld-sh/weak1.d
    ld/testsuite/ld-sh/weak1.s
    ld/testsuite/ld-shared/elf-offset.ld
    ld/testsuite/ld-shared/main.c
    ld/testsuite/ld-shared/sh1.c
    ld/testsuite/ld-shared/sh2.c
    ld/testsuite/ld-shared/shared.dat
    ld/testsuite/ld-shared/shared.exp
    ld/testsuite/ld-shared/sun4.dat
    ld/testsuite/ld-shared/symbolic.dat
    ld/testsuite/ld-shared/xcoff.dat
    ld/testsuite/ld-sparc/sparc.exp
    ld/testsuite/ld-sparc/tlsg32.s
    ld/testsuite/ld-sparc/tlsg32.sd
    ld/testsuite/ld-sparc/tlsg64.s
    ld/testsuite/ld-sparc/tlsg64.sd
    ld/testsuite/ld-sparc/tlslib.s
    ld/testsuite/ld-sparc/tlsnopic.s
    ld/testsuite/ld-sparc/tlspic.s
    ld/testsuite/ld-sparc/tlssunbin32.dd
    ld/testsuite/ld-sparc/tlssunbin32.rd
    ld/testsuite/ld-sparc/tlssunbin32.s
    ld/testsuite/ld-sparc/tlssunbin32.sd
    ld/testsuite/ld-sparc/tlssunbin32.td
    ld/testsuite/ld-sparc/tlssunbin64.dd
    ld/testsuite/ld-sparc/tlssunbin64.rd
    ld/testsuite/ld-sparc/tlssunbin64.s
    ld/testsuite/ld-sparc/tlssunbin64.sd
    ld/testsuite/ld-sparc/tlssunbin64.td
    ld/testsuite/ld-sparc/tlssunbinpic32.s
    ld/testsuite/ld-sparc/tlssunbinpic64.s
    ld/testsuite/ld-sparc/tlssunnopic32.dd
    ld/testsuite/ld-sparc/tlssunnopic32.rd
    ld/testsuite/ld-sparc/tlssunnopic32.s
    ld/testsuite/ld-sparc/tlssunnopic32.sd
    ld/testsuite/ld-sparc/tlssunnopic64.dd
    ld/testsuite/ld-sparc/tlssunnopic64.rd
    ld/testsuite/ld-sparc/tlssunnopic64.s
    ld/testsuite/ld-sparc/tlssunnopic64.sd
    ld/testsuite/ld-sparc/tlssunpic32.dd
    ld/testsuite/ld-sparc/tlssunpic32.rd
    ld/testsuite/ld-sparc/tlssunpic32.s
    ld/testsuite/ld-sparc/tlssunpic32.sd
    ld/testsuite/ld-sparc/tlssunpic32.td
    ld/testsuite/ld-sparc/tlssunpic64.dd
    ld/testsuite/ld-sparc/tlssunpic64.rd
    ld/testsuite/ld-sparc/tlssunpic64.s
    ld/testsuite/ld-sparc/tlssunpic64.sd
    ld/testsuite/ld-sparc/tlssunpic64.td
    ld/testsuite/ld-sparc/vxworks1-lib.dd
    ld/testsuite/ld-sparc/vxworks1-lib.nd
    ld/testsuite/ld-sparc/vxworks1-lib.rd
    ld/testsuite/ld-sparc/vxworks1-lib.s
    ld/testsuite/ld-sparc/vxworks1-static.d
    ld/testsuite/ld-sparc/vxworks1.dd
    ld/testsuite/ld-sparc/vxworks1.ld
    ld/testsuite/ld-sparc/vxworks1.rd
    ld/testsuite/ld-sparc/vxworks1.s
    ld/testsuite/ld-sparc/vxworks2-static.sd
    ld/testsuite/ld-sparc/vxworks2.s
    ld/testsuite/ld-sparc/vxworks2.sd
    ld/testsuite/ld-srec/sr1.c
    ld/testsuite/ld-srec/sr2.c
    ld/testsuite/ld-srec/sr3.cc
    ld/testsuite/ld-srec/srec.exp
    ld/testsuite/ld-undefined/undefined.c
    ld/testsuite/ld-undefined/undefined.exp
    ld/testsuite/ld-undefined/weak-undef.exp
    ld/testsuite/ld-undefined/weak-undef.s
    ld/testsuite/ld-undefined/weak-undef.t
    ld/testsuite/ld-v850/split-lo16.d
    ld/testsuite/ld-v850/split-lo16.ld
    ld/testsuite/ld-v850/split-lo16.s
    ld/testsuite/ld-v850/v850.exp
    ld/testsuite/ld-versados/t1-1.ro
    ld/testsuite/ld-versados/t1-2.ro
    ld/testsuite/ld-versados/t1.ld
    ld/testsuite/ld-versados/t1.ook
    ld/testsuite/ld-versados/t2-1.ro
    ld/testsuite/ld-versados/t2-2.ro
    ld/testsuite/ld-versados/t2-3.ro
    ld/testsuite/ld-versados/t2.ld
    ld/testsuite/ld-versados/t2.ook
    ld/testsuite/ld-versados/versados.exp
    ld/testsuite/ld-x86-64/abs.d
    ld/testsuite/ld-x86-64/pcrel16.d
    ld/testsuite/ld-x86-64/pcrel8.d
    ld/testsuite/ld-x86-64/tlsbin.dd
    ld/testsuite/ld-x86-64/tlsbin.rd
    ld/testsuite/ld-x86-64/tlsbin.s
    ld/testsuite/ld-x86-64/tlsbin.sd
    ld/testsuite/ld-x86-64/tlsbin.td
    ld/testsuite/ld-x86-64/tlsbindesc.dd
    ld/testsuite/ld-x86-64/tlsbindesc.rd
    ld/testsuite/ld-x86-64/tlsbindesc.s
    ld/testsuite/ld-x86-64/tlsbindesc.sd
    ld/testsuite/ld-x86-64/tlsbindesc.td
    ld/testsuite/ld-x86-64/tlsbinpic.s
    ld/testsuite/ld-x86-64/tlsdesc.dd
    ld/testsuite/ld-x86-64/tlsdesc.pd
    ld/testsuite/ld-x86-64/tlsdesc.rd
    ld/testsuite/ld-x86-64/tlsdesc.s
    ld/testsuite/ld-x86-64/tlsdesc.sd
    ld/testsuite/ld-x86-64/tlsdesc.td
    ld/testsuite/ld-x86-64/tlsg.s
    ld/testsuite/ld-x86-64/tlsg.sd
    ld/testsuite/ld-x86-64/tlsgdesc.dd
    ld/testsuite/ld-x86-64/tlsgdesc.rd
    ld/testsuite/ld-x86-64/tlsgdesc.s
    ld/testsuite/ld-x86-64/tlslib.s
    ld/testsuite/ld-x86-64/tlspic.dd
    ld/testsuite/ld-x86-64/tlspic.rd
    ld/testsuite/ld-x86-64/tlspic.sd
    ld/testsuite/ld-x86-64/tlspic.td
    ld/testsuite/ld-x86-64/tlspic1.s
    ld/testsuite/ld-x86-64/tlspic2.s
    ld/testsuite/ld-x86-64/x86-64.exp
    ld/testsuite/ld-xc16x/absrel.d
    ld/testsuite/ld-xc16x/absrel.s
    ld/testsuite/ld-xc16x/offset.d
    ld/testsuite/ld-xc16x/offset.s
    ld/testsuite/ld-xc16x/pcreloc.d
    ld/testsuite/ld-xc16x/pcreloc.s
    ld/testsuite/ld-xc16x/pcrelocl.d
    ld/testsuite/ld-xc16x/xc16x.exp
    ld/testsuite/ld-xstormy16/external.s
    ld/testsuite/ld-xstormy16/pcrel.d
    ld/testsuite/ld-xstormy16/pcrel.s
    ld/testsuite/ld-xstormy16/xstormy16.exp
    ld/testsuite/ld-xtensa/coalesce.exp
    ld/testsuite/ld-xtensa/coalesce.t
    ld/testsuite/ld-xtensa/coalesce1.s
    ld/testsuite/ld-xtensa/coalesce2.s
    ld/testsuite/ld-xtensa/lcall.exp
    ld/testsuite/ld-xtensa/lcall.t
    ld/testsuite/ld-xtensa/lcall1.s
    ld/testsuite/ld-xtensa/lcall2.s
    ld/testsuite/lib/ld-lib.exp
    opcodes/ChangeLog
    opcodes/ChangeLog-0001
    opcodes/ChangeLog-0203
    opcodes/ChangeLog-2004
    opcodes/ChangeLog-2005
    opcodes/ChangeLog-9297
    opcodes/ChangeLog-9899
    opcodes/MAINTAINERS
    opcodes/Makefile.am
    opcodes/Makefile.in
    opcodes/acinclude.m4
    opcodes/aclocal.m4
    opcodes/alpha-dis.c
    opcodes/alpha-opc.c
    opcodes/arc-dis.c
    opcodes/arc-dis.h
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    opcodes/arc-ext.h
    opcodes/arc-opc.c
    opcodes/arm-dis.c
    opcodes/avr-dis.c
    opcodes/bfin-dis.c
    opcodes/cgen-asm.c
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    opcodes/cgen-bitset.c
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    opcodes/crx-dis.c
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    opcodes/i860-dis.c
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    opcodes/ia64-asmtab.c
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    opcodes/ia64-ic.tbl
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    opcodes/ia64-opc-d.c
    opcodes/ia64-opc-f.c
    opcodes/ia64-opc-i.c
    opcodes/ia64-opc-m.c
    opcodes/ia64-opc-x.c
    opcodes/ia64-opc.c
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    opcodes/ia64-raw.tbl
    opcodes/ia64-war.tbl
    opcodes/ia64-waw.tbl
    opcodes/ip2k-asm.c
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    sim/testsuite/sim/sh64/interwork.exp
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    sim/testsuite/sim/sh64/media/mmacfxwl.cgs
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    sim/testsuite/sim/sh64/misc/fr-dr.s
    sim/v850/ChangeLog
    sim/v850/Makefile.in
    sim/v850/acconfig.h
    sim/v850/config.in
    sim/v850/configure
    sim/v850/configure.ac
    sim/v850/interp.c
    sim/v850/sim-main.h
    sim/v850/simops.c
    sim/v850/simops.h
    sim/v850/v850-dc
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    texinfo/texinfo.tex

44 files changed, 0 insertions, 54148 deletions

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
deleted file mode 100644
index 8a47048..0000000
--- a/sim/m32r/ChangeLog
+++ /dev/null
@@ -1,1514 +0,0 @@
-2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
-
-	* configure: Regenerated.
-
-2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
-
-	* configure: Regenerated.
-
-2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
-
-	* configure: Regenerated.
-
-2005-03-23  Mark Kettenis  <kettenis@gnu.org>
-
-	* configure: Regenerate.
-
-2005-01-14  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Sinclude aclocal.m4 before common.m4.  Add
-	explicit call to AC_CONFIG_HEADER.
-	* configure: Regenerate.
-
-2005-01-12  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Update to use ../common/common.m4.
-	* configure: Re-generate.
-
-2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2005-01-07  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Rename configure.in, require autoconf 2.59.
-	* configure: Re-generate.
-
-2004-12-09  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
-
-	Committed by Kei Sakamoto.
-	* traps-linux.c (m32r_trap): Add entries of the following dummy system
-	calls: __NR_mmap2, __NR_lchown32, __NR_getuid32, __NR_getgid32,
-	__NR_geteuid32, __NR_getegid32, __NR_getgroups32, __NR_fchown32,
-	__NR_setfsuid32, __NR_setfsgid32, __NR_getresuid32,
-	__NR_getresgid32 and __NR_chown32.
-	* syscall.h: Add new definitions of system call number.
-
-2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
-
-	* configure: Regenerate for ../common/aclocal.m4 update.
-
-2004-10-07  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
-
-	Committed by Andrew Cagney.
-	* traps-linux.c: Don't include linux/module.h.
-	(m32r_trap): Remove dummy systemcall's entry of __NR_ustat and
-	__NR_get_kernel_syms.
-
-2004-05-18  Daniel Jacobowitz  <dan@debian.org>
-
-	* Makefile.in (stamp-xmloop, stamp-2mloop): Use -outfile-suffix.
-
-2004-02-04  Andrew Cagney  <cagney@redhat.com>
-
-	Committed by Andrew Cagney.
-	* mloopx.in: Update copyright.
-	(xextract-pbb): Fixed trap for system calls operation in parallel.
-	* mloop2.in (xextract-pbb): Ditto.
-
-2003-12-19  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
-
-        * configure.in: Changed for dummy simulator of m32r-linux.
-	* configure: Regenerate.
-        * Makefile.in: Added traps-linux.o for dummy simulator of m32r-linux.
-        * traps-linux.c: Added for dummy simulator of m32r-linux.
-        * syscall.h: Ditto.
-        * sim-if.c (sim_create_inferior): Changed to setup SP for dummy
-        simulator for m32r-linux.
-        * sim-main.h (M32R_DEFAULT_MEM_SIZE): Changed for dummy simulator of
-        m32r-linux.
-
-2003-12-11  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
-
-	* Makefile.in: Add support for new machine m32r2.
-	* cpu2.c: New file for m32r2 support.
-	* cpu2.h: Likewise.
-	* decode2.c: Likewise.
-	* decode2.h: Likewise.
-	* m32r2.c: Likewise.
-	* mloop2.in: Likewise.
-	* model2.c: Likewise.
-	* sem2-switch.c: Likewise.
-	* arch.c: Regenerate.
-	* arch.h: Regenerate.
-	* cpu.c: Regenerate.
-	* arch.c: Regenerate.
-	* cpuall.c: Regenerate.
-	* cpux.c: Regenerate.
-	* cpux.h: Regenerate.
-	* decode.c: Regenerate.
-	* decode.h: Regenerate.
-	* decodex.c: Regenerate.
-	* decodex.h: Regenerate.
-	* model.c: Regenerate.
-	* modelx.c: Regenerate.
-	* sem-switch.c: Regenerate.
-	* sem.c: Regenerate.
-	* semx-switch.c: Regenerate.
-	* m32r-sim.h: Add EVB register support.
-	* sim-if.c: Likewise.
-	* sim-main.h: Likewise.
-	* traps.c: Likewise.
-
-2003-09-08  Dave Brolley  <brolley@redhat.com>
-
-	On behalf of Doug Evans <dje@sebabeach.org>
-	* Makefile.in (stamp-arch,stamp-cpu,stamp-xcpu): Pass archfile to cgen.
-
-2003-02-27  Andrew Cagney  <cagney@redhat.com>
-
-	* sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
-
-2002-12-19  Doug Evans  <dje@sebabeach.org>
-
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
-
-2002-06-16  Andrew Cagney  <ac131313@redhat.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2001-11-14  Dave Brolley  <brolley@redhat.com>
-
-	* arch.c: Regenerate.
-	* arch.h: Regenerate.
-	* cpu.c: Regenerate.
-	* cpu.h: Regenerate.
-	* cpuall.h: Regenerate.
-	* cpux.c: Regenerate.
-	* cpux.h: Regenerate.
-	* decode.c: Regenerate.
-	* decode.h: Regenerate.
-	* decodex.c: Regenerate.
-	* decodex.h: Regenerate.
-	* model.c: Regenerate.
-	* modelx.c: Regenerate.
-	* sem-switch.c: Regenerate.
-	* sem.c: Regenerate.
-	* semx-switch.c: Regenerate.
-
-2001-07-05  Ben Elliston  <bje@redhat.com>
-
-	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
-	(stamp-cpu): Likewise.
-	(stamp-xcpu): Likewise.
-
-2001-03-05  Dave Brolley  <brolley@redhat.com>
-
-	* arch.c: Regenerate.
-	* arch.h: Regenerate.
-	* cpu.c: Regenerate.
-	* cpu.h: Regenerate.
-	* cpuall.h: Regenerate.
-	* cpux.c: Regenerate.
-	* cpux.h: Regenerate.
-	* decode.c: Regenerate.
-	* decode.h: Regenerate.
-	* decodex.c: Regenerate.
-	* decodex.h: Regenerate.
-	* model.c: Regenerate.
-	* modelx.c: Regenerate.
-	* sem-switch.c: Regenerate.
-	* sem.c: Regenerate.
-	* semx-switch.c: Regenerate.
-
-2001-01-12  Frank Ch. Eigler  <fche@redhat.com>
-
-	* configure: Regenerated with sim_scache fix.
-
-2000-11-18  Greg McGary  <greg@mcgary.org>
-
-	* Makefile.in: remove `@true' commands for rules that have
-	$(CGEN_MAINT) as a prerequisite.
-
-2000-10-06  Dave Brolley  <brolley@redhat.com>
-
-	* sem.c: Regenerated.
-	* sem-switch.c: Regenerated.
-	* semx-switch.c: Regenerated.
-
-2000-08-28  Dave Brolley  <brolley@redhat.com>
-
-	* Makefile.in: Use of @true confuses VPATH. Remove it.
-	* cpu.h: Regenerated.
-	* cpux.h: Regenerated.
-	* decode.c: Regenerated.
-	* decodex.c: Regenerated.
-	* model.c: Regenerated.
-	* modelx.c: Regenerated.
-	* sem-switch.c: Regenerated.
-	* sem.c: Regenerated.
-	* semx-switch.c: Regenerated.
-
-2000-08-21  Frank Ch. Eigler  <fche@redhat.com>
-
-	* Makefile.in (m32r-clean): Add stamp-arch, stamp-cpu.
-	(stamp-arch, stamp-cpu): New targets.
-
-Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2000-03-30  Dave Brolley  <brolley@redhat.com>
-
-	* configure: Regenerated.
-
-1999-10-04  Doug Evans  <devans@casey.cygnus.com>
-
-	* arch.c,arch.h,cpuall.h: Rebuild.
-	* cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
-
-1999-09-29  Doug Evans  <devans@casey.cygnus.com>
-
-	* mloop.in: Update call to sim_engine_invalid_insn.
-	* sem.c,sem-switch.c: Rebuild.
-	* traps.c (sim_engine_invalid_insn): New arg `vpc'.  Change type of
-	result to SEM_PC.  Return vpc.
-	* mloopx.in: Ditto.
-	* semx-switch.c: Rebuild.
-
-Wed Sep 29 14:47:20 1999  Dave Brolley  <brolley@cygnus.com>
-
-	* traps.c (sim_engine_invalid_insn): Return PC.
-
-Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-1999-09-01  Doug Evans  <devans@casey.cygnus.com>
-
-	* decodex.c: Rebuild.
-
-1999-08-28  Doug Evans  <devans@casey.cygnus.com>
-
-	* sem.c: Rebuild
-
-	* cpux.h: Rebuild.
-
-1999-08-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
-	* cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
-
-1999-08-04  Doug Evans  <devans@casey.cygnus.com>
-
-	* m32r-sim.h (SEM_SKIP_INSN): Delete.
-	* cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
-	* mloopx.in (emit_parallel): Call SEM_SKIP_COMPILE.
-	(emit_full_parallel): Ditto.
-
-1999-05-08  Felix Lee  <flee@cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	
-Fri Apr 16 16:47:43 1999  Doug Evans  <devans@charmed.cygnus.com>
-
-	* devices.c (device_io_read_buffer): New arg `sd'.
-	(device_io_write_buffer): New arg `sd'.
-	(device_error): Give proper arg spec.
-
-1999-04-10  Doug Evans  <devans@casey.cygnus.com>
-
-	* sem-switch.c,sem.c: Rebuild.
-	* cpux.h,semx-switch.c: Rebuild.
-
-1999-03-27  Doug Evans  <devans@casey.cygnus.com>
-
-	* decode.c: Rebuild.
-	* decodex.c: Rebuild.
-
-1999-03-26  Doug Evans  <devans@casey.cygnus.com>
-
-	* m32r-sim.h (M32R_DEVICE_LEN): Fix off by one error.
-
-1999-03-22  Doug Evans  <devans@casey.cygnus.com>
-
-	* arch.c,arch.h,model.c: Rebuild.
-	* modelx.c: Rebuild.
-	* m32r-sim.h (a_m32r_h_gr_get,a_m32r_h_gr_set): Declare.
-	(a_m32r_h_cr_get,a_m32r_h_cr_set): Declare.
-	* m32r.c (m32rbf_fetch_register): Replace calls to a_m32r_h_pc_get,
-	a_m32r_h_accum_get with appropriate calls to m32rbf_*.
-	(m32rbf_store_register): Ditto.
-	(a_m32r_h_gr_get,a_m32r_h_gr_set): New functions.
-	(a_m32r_h_cr_get,a_m32r_h_cr_set): Ditto.
-	* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
-	* traps.c (m32r_core_signal): Replace calls to a_m32r_h_*,
-	with appropriate calls to m32rbf_*.
-
-1999-03-11  Doug Evans  <devans@casey.cygnus.com>
-
-	* arch.c,arch.h,cpu.c,cpu.h,sem.c,sem-switch.c: Rebuild.
-	* cpux.c,cpux.h,semx-switch.c: Rebuild.
-	* m32r-sim.h (GET_H_*,SET_H_*, except GET_H_SM): Delete.
-	* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
-
-1999-02-25  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.c,cpu.h: Rebuild.
-
-1999-02-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h.
-	(stamp-xmloop): s/-parallel/-parallel-write/.
-	* configure.in (sim_link_files,sim_link_links): Delete.
-	* configure: Rebuild.
-	* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
-	* decodex.c,decodex.h,modelx.c,semx-switch.c: Rebuild.
-	* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
-	* sim-if.c (sim_open): m32r_cgen_cpu_open renamed from
-	m32r_cgen_opcode_open.  Set disassembler.
-	(sim_close): m32r_cgen_cpu_open renamed from m32r_cgen_opcode_open.
-	* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
-	m32r-desc.h,m32r-opc.h,m32r-sim.h.
-
-Thu Feb  4 16:04:26 1999  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
-
-1999-01-27  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild.
-
-1999-01-15  Doug Evans  <devans@casey.cygnus.com>
-
-	* decode.h,model.c: Regenerate.
-	* decodex.h,modelx.c: Regenerate.
-
-1999-01-14  Doug Evans  <devans@casey.cygnus.com>
-
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
-	* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,semx-switch.c: Regenerate.
-
-1999-01-11  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (m32r-clean): rm eng.h.
-	* sim-main.h: Delete inclusion of ansidecl.h.
-	* cpu.h: Regenerate.
-	* cpux.h: Regenerate.
-
-1999-01-06  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h: Regenerate.
-	* cpux.h: Regenerate.
-
-1999-01-05  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
-	(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
-	(sim-if.o): Use SIM_MAIN_DEPS.
-	(arch.o,traps.o,devices.o): Ditto.
-	(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
-	(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
-	(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
-	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
-	* m32r-sim.h (m32rbf_h_cr_[gs]et_handler): Declare.
-	([GS]ET_H_CR): Define.
-	(m32rbf_h_psw_[gs]et_handler): Declare.
-	([GS]ET_H_PSW): Define.
-	(m32rbf_h_accum_[gs]et_handler): Declare.
-	([GS]ET_H_ACCUM): Define.
-	(m32rxf_h_{cr,psw,accum}_[gs]et_handler): Declare.
-	(m32rxf_h_accums_[gs]et_handler): Declare.
-	([GS]ET_H_ACCUMS): Define.
-	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
-	* m32r.c (WANT_CPU): Define as m32rbf.
-	(all register access fns): Rename to ..._handler.
-	* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
-	* m32rx.c (WANT_CPU): Define as m32rxf.
-	(all register access fns): Rename to ..._handler.
-
-1998-12-14  Doug Evans  <devans@casey.cygnus.com>
-
-	* configure.in: --enable-cgen-maint support moved to common/aclocal.m4.
-	(SIM_AC_OPTION_ALIGNMENT): Make strict.
-	* configure: Regenerate.
-
-	* sem-switch.c,sem.c,semx-switch.c: Regenerate.
-	* sim-main.h (SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Define.
-	* traps.c (m32r_core_signal): Handle --environment=operating.
-
-1998-12-09  Doug Evans  <devans@casey.cygnus.com>
-
-	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
-	* cpux.h,decodex.c,semx-switch.c: Regenerate.
-
-	* sim-if.c: Include string.h or strings.h if present.
-
-1998-12-04  Doug Evans  <devans@casey.cygnus.com>
-
-	* configure.in: Call SIM_AC_OPTION_INLINE.
-	* configure: Regenerate.
-	* sim-main.h: Protect against multiple inclusion.
-	Don't include cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
-	Done by cgen-sim.h now.
-	* tconfig.in (SIM_HAVE_MODEL): Delete, moved to cgen-types.h.
-	* cpuall.h: Regenerate.
-	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
-	* mloop.in (extract16): Make static inline again.
-	Simplify with call to @cpu@_fill_argbuf,@cpu@_fill_argbuf_tp.
-	(extract32): Ditto.
-	Simplify with call to @cpu@_fill_argbuf,@cpu@_fill_argbuf_tp.
-	(execute): Test ARGBUF_PROFILE_P before profiling.
-	Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
-	* cpux.h,decodex.c,modelx.c,semx-switch.c: Regenerate.
-	* mloopx.in: Rewrite.
-
-1998-11-22  Doug Evans  <devans@tobor.to.cygnus.com>
-
-	* devices.c (device_io_write_buffer): Fix typo.
-	* sim-if.c (sim_open): Hack in call to dv_sockser_install.
-	* tconfig.in (HAVE_DV_SOCKSER): Add but comment out.
-
-1998-11-18  Doug Evans  <devans@casey.cygnus.com>
-
-	* Makefile.in (M32R_OBJS): Delete extract.o.
-	(extract.o): Delete.
-	* cpu.c,cpu.h,decode.c,decode.h,sem-switch.c,sem.c: Rebuild.
-	* mloop.in (extract16): Update type of `insn' arg.
-	Delete call to d->extract.
-	(extract32): Ditto.
-	* cpux.c,cpux.h,decodex.c,decodex.h,semx-switch.c: Rebuild.
-	* mloopx.in (extractx16): Update type of `insn' arg.
-	Delete call to d->extract.  Delete arg pbb_p.  All callers updated.
-	(extract-simple,full-exec-simple,fast-exec-simple): Delete.
-	(extractx32): Ditto.
-
-Wed Nov  4 23:55:37 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: Delete inclusion of config.h, include sim-basics.h
-	before cgen-types.h.
-	* tconfig.in: Guard against multiple inclusion.
-	* cpu.h: Delete decls moved to genmloop.sh.
-	* cpux.h: Ditto.
-
-Mon Oct 19 14:13:05 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: #include cpu-opc.h.
-	* arch.c,arch.h,decode.c,extract.c,model.c,sem.c: Regenerate
-	to get #include cleanup.
-	* decodex.c,extractx.c,modelx.c: Ditto.
-
-	* Makefile.in (SIM_EXTRA_DEPS): Replace cgen headers with
-	CGEN_INCLUDE_DEPS.
-	(M32RBF_INCLUDE_DEPS): Define.
-	(m32r .o's): Depend on it.
-	(mloop.c): Update call to genmloop.sh.
-	* cpu.h,cpuall.h: Regenerate.
-	* sim-main.h: Delete inclusion of cpu.h,decode.h, moved to cpuall.h.
-	#include cgen-scache.h,cgen-cpu.h.
-	* tconfig.in (WITH_FOO semantic macros): Delete.
-	* Makefile.in (M32RXF_INCLUDE_DEPS): Define.
-	(m32rx .o's): Depend on it.
-	(mloopx.c): Update call to genmloop.sh.
-	* cpux.h: Regenerate.
-
-Fri Oct 16 09:15:29 1998  Doug Evans  <devans@charmed.cygnus.com>
-
-	* sim-if.c (sim_do_command): Handle "sim info reg {bbpsw,bbpc}".
-
-Fri Oct  9 16:11:58 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	Add pseudo-basic-block execution support.
-	* Makefile.in (SIM_OBJS): Add sim-reg.o, cgen-run.o, sim-stop.o.
-	(SIM_EXTRA_DEPS): Add include/opcode/cgen.h.
-	(INCLUDE_DEPS): Delete cpu-sim.h, include/opcode/cgen.h.
-	(mloop.c): Build pseudo-basic-block version.  Depend on stamp-cpu.
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* m32r-sim.h (M32R_MISC_PROFILE): New members load_regs,
-	load_regs_pending.
-	* m32r.c (m32rbf_fetch_register): Renamed from m32rb_fetch_register.
-	(m32rbf_store_register,m32rbf_h_cr_get,m32rbf_h_cr_set,
-	m32rbf_h_psw_get,m32rbf_h_psw_set,m32rbf_h_accum_get,
-	m32rbf_h_accum_set): Likewise.
-	(m32r_model_{init,update}_insn_cycles): Delete.
-	(m32rbf_model_insn_{before,after}): New fns.
-	(m32r_model_record_cti,m32r_model_record_cycles): Delete.
-	(m32rb_model_mark_get_h_gr,m32rb_model_mark_set_h_gr): Delete.
-	(m32rb_model_mark_busy_reg,m32rb_model_mark_unbusy_reg): Delete.
-	(check_load_stall): New fn.
-	(m32rbf_model_m32r_d_u_{exec,cmp,mac,cti,load,store}): New fns.
-	(m32rbf_model_test_u_exec): New fn.
-	* mloop.in: Rewrite, use pbb support.
-	* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Delete.
-	(sim_fetch_register,sim_store_register): Delete.
-	* sim-main.h (CIA_GET,CIA_SET): Fix.
-	(SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Delete.
-	* tconfig.in (WITH_SCACHE_PBB): Define.
-	(WITH_SCACHE_PBB_M32RBF): Define.
-	* traps.c (sim_engine_invalid_insn): Renamed from ..._illegal_....
-	(m32r_trap): Pass pc to sim_engine_halt.
-	* configure.in (SIM_AC_OPTION_SCACHE): Change 1024 to 16384.
-	* configure: Regenerate.
-	* Makefile.in (M32RX_OBJS): Delete semx.o, add extract.o.
-	(mloopx.c): Build pseudo-basic-block version.
-	(semx.o): Delete.
-	(extractx.o): Add.
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c: Regenerate.
-	* readx.c: Delete.
-	* semx.c: Delete.
-	* extractx.c: New file.
-	* semx-switch.c: New file.
-	* m32r-sim.h (BRANCH_NEW_PC): Delete.
-	(SEM_SKIP_INSN): New macro.
-	* m32rx.c (m32rxf_fetch_register): Renamed from m32rx_fetch_register.
-	(m32rxf_store_register,m32rxf_h_cr_get,m32rxf_h_cr_set,
-	m32rxf_h_psw_get,m32rxf_h_psw_set,m32rxf_h_accum_get,
-	m32rxf_h_accum_set,m32rxf_h_accums_get,m32rxf_h_accums_set): Likewise.
-	(m32rxf_model_insn_{before,after}): New fns.
-	(m32rx_model_mark_get_h_gr,m32rx_model_mark_set_h_gr): Delete.
-	(m32rx_model_mark_busy_reg,m32rx_model_mark_unbusy_reg): Delete.
-	(check_load_stall): New fn.
-	(m32rxf_model_m32rx_u_{exec,cmp,mac,cti,load,store}): New fns.
-	* mloopx.in: Rewrite, use pbb support.
-	* tconfig.in (WITH_SCACHE_PBB_M32RXF): Define.
-	(WITH_SEM_SWITCH_FULL): Change from 0 to 1.
-
-Wed Sep 16 18:22:27 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h ({PSW,CBR,SPI,SPU,BPC,BBPSW,BBPC}_REGNUM): New macros.
-	({ACC1L,ACC1H}_REGNUM): New macros.
-	(m32r_decode_gdb_ctrl_regnum): Add prototype.
-	* m32r.c (m32r_decode_gdb_ctrl_regnum): New function.
-	(m32r_fetch_register,m32r_store_register): Rewrite.
-	* m32rx.c (m32rx_fetch_register,m32rx_store_register): Rewrite.
-
-Tue Sep 15 15:01:14 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (GET_H_SM): New macro.
-	(UART params): Update to msa2000.
-	* devices.c (device_io_read_buffer): Update to msa2000.
-	* m32r.c (m32rb_h_cr_get,m32rb_h_cr_set): Handle bbpc,bbpsw.
-	(m32rb_h_psw_get,m32rb_h_psw_set): New functions.
-	* arch.c,arch.h,cpu.c,cpu.h,sem-switch.c,sem.c: Regenerate.
-	* m32rx.c (m32rx_h_cr_get,m32rx_h_cr_set): Handle bbpc,bbpsw.
-	(m32rx_h_psw_get,m32rx_h_psw_set): New functions.
-	* cpux.c,cpux.h,readx.c,semx.c: Regenerate.
-
-Wed Sep  9 15:29:36 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (m32r_trap): Update prototype.
-	* traps.c (m32r_trap): New arg `pc'.
-	* sem.c,sem-switch.c: Regenerated.
-	* cpux.h,readx.c,semx.c: Regenerated.
-
-Mon Aug  3 12:59:17 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	Rename cpu m32r to m32rb to distinguish from architecture name.
-	* Makefile.in (mloop.c): cpu m32r renamed to m32rb.
-	* sim-main.h (WANT_CPU_M32RB): Renamed from WANT_CPU_M32R.
-	* tconfig.in (WANT_CPU_M32RB): Ditto.
-	* m32r.c (WANT_CPU_M32RB): Ditto.
-	(*): m32r_ cpu fns renamed to m32rb_.
-	* sim-if.c (sim_stop,sim_sync_stop,sim_resume): Update.
-	* arch.h,arch.c: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-
-	* sim-if.c (sim_open): Don't allocate memory on top of any user
-	specified memory.
-	(h_gr_get,h_gr_set): Delete.
-	* sim-main.h (h_gr_get,h_gr_set): Delete.
-	* traps.c (m32r_trap): Replace calls to h_gr_[gs]et with
-	a_m32r_h_gr_[gs]et.
-
-	* Makefile.in (INCLUDE_DEPS): Add include/opcode/cgen.h.
-
-	* sim-if.c (sim_open): Open opcode table.
-	(sim_close): Close it.
-
-Tue Jul 28 13:06:19 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	Add support for new versions of mulwhi,mulwlo,macwhi,macwlo that
-	accept an accumulator choice.
-	* cpux.c,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
-
-Fri Jul 24 13:00:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r.c: Include cgen-mem.h.
-	* traps.c (m32r_trap): Tweak for -Wall.
-	* m32rx.c: Include cgen-mem.h.
-	* semx.c: Regenerate, get -Wall cleanups.
-
-Tue Jul 21 16:53:10 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cpu.h,extract.c: Regenerate.  pc-rel calcs done on f_dispNN now.
-	* cpux.h,readx.c,semx.c: Ditto.
-
-Wed Jul  1 16:51:15 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in: cgen_maint -> CGEN_MAINT.
-	* configure.in: AC_SUBST cgen,cgendir.  No longer look for guile.
-	* configure: Regenerate.
-	* arch.c,arch.h,cpuall.h: Regenerate.
-	* cpu.c,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* cpux.c,cpux.h,decodex.c,decodex.h,modelx.c,readx.c: Regenerate.
-	* semx.c: Regenerate.
-	* mloopx.in (icount): Moved here from genmloop.sh.
-
-Sat Jun 13 07:49:23 1998  Doug Evans  <devans@fallis.cygnus.com>
-
-	* m32r-sim.h (M32R_MISC_PROFILE): New members insn_cycles, cti_stall,
-	load_stall,biggest_cycles.
-	* m32r.c (m32r_model_mark_get_h_gr): Update.
-	(m32r_model_init_insn_cycles,m32r_model_update_insn_cycles): New fns.
-	(m32r_model_record_cti,m32r_model_record_cycles): New functions.
-	* mloop.in: Call cycle init/update fns.
-	* model.c: Regenerate.
-	* m32rx.c (m32rx_model_mark_get_h_gr): Update.
-	* mloopx.in: Call cycle init/update fns.
-	* modelx.c: Regenerate.
-
-Wed Jun 10 17:39:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* traps.c: New file.  Trap support moved here from sim-if.c.
-	* Makefile.in (SIM_OBJS): Add traps.o
-	* sim-if.c: Don't include targ-vals.h.
-	(sim_engine_illegal_insn): Moved to traps.c
-	* sim-main.h (SIM_CORE_SIGNAL): Define.
-	(m32r_core_signal): Declare.
-	* m32r-sim.h (m32r_trap): Declare.
-
-	* devices.c (device_io_read_buffer): Handle cache purging via MCCR
-	register.
-
-	* m32r-sim.h (M32R_MISC_PROFILE): Move here from sim-main.h.
-	(PROFILE_COUNT_SHORTINSNS,PROFILE_COUNT_LONGINSNS): New macros.
-	(TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
-
-	* extract.c,sem-switch.c,sem.c: Regenerate.
-	* cpux.h,readx.c,semx.c: Regenerate.
-
-Wed May 20 00:10:40 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* m32r-sim.h (PROFILE_COUNT_PARINSNS): New macro.
-	* mloopx.in (extract): Set abuf.addr for proper fill nop counting.
-	(execute): Count parallel insns.
-	* sim-if.c (print_m32r_misc_cpu): Print count.
-	* sim-main.h (M32R_MISC_PROFILE): New member parallel_count.
-
-	Zero bottom two bits of pc in jmp,jl insns.
-	* sem.c,sem-switch.c: Regenerate.
-	* semx.c: Regenerate.
-
-Tue May 19 16:45:33 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-if.c (do_trap): Treat traps 2-15 as hardware does.
-
-Sat May 16 13:04:30 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-if.c (sim_stop): Update call to @cpu@_engine_stop.
-	(sim_sync_stop): New function.
-
-Fri May 15 16:43:27 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (devices.o): Add dependencies.
-
-	* arch.h,cpu.c,cpu.h,cpuall.h: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* mloop.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
-	* cpux.c,cpux.h,modelx.c,semx.c: Regenerate.
-	* m32rx.c (m32rx_model_mark_{busy,unbusy}_reg): New functions.
-	* mloopx.in (execute): Update calls to TRACE_INSN_{INIT,FINI}.
-	Fix pc value passed to TRACE_INSN for second parallel insn.
-
-Thu May  7 02:51:35 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-cpu.o.
-
-Wed May  6 14:51:39 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* arch.h,arch.c,cpu.h,cpuall.h: Regenerate, tweaks mostly.
-	* model.c: Ditto.  Reorganize model/mach data.
-	* cpux.h: Ditto.
-	* modelx.c: Ditto.
-
-	* Makefile.in (m32r.o,mloop.o,cpu.o,model.o): Add decode.h dependency.
-	(m32rx.o,mloopx.o,cpux.o,modelx.o): Add decodex.h dependency.
-	* decode.c,decode.h: Regenerate, introduces IDESC table.
-	* mloop.in (extract16,extract32): Add IDESC support.
-	Update names of semantic handler member names.
-	(execute): Ditto.  Delete call to PROFILE_COUNT_INSN.
-	* decodex.c,decodex.h: Regenerate, introduces IDESC table.
-	* mloopx.in: Add IDESC support.
-	Update names of semantic handler member names.
-	Delete call to PROFILE_COUNT_INSN.
-
-	* sem-switch.c: Regenerate.  Redo computed goto label handling.
-	* sem.c: Regenerate.  Call PROFILE_COUNT_INSN.
-	* readx.c: Regenerate.  Redo computed goto label handling.
-	* semx.c: Regenerate.  Call PROFILE_COUNT_INSN.  Finish profiling
-	support.
-
-	* m32r.c (m32r_fetch_register): Change result type and args to
-	conform to sim_fetch_register interface.
-	(m32r_store_register): Ditto for sim_store_register interface.
-	* m32rx.c (m32rx_fetch_register): Change result type and args to
-	conform to sim_fetch_register interface.
-	(m32rx_store_register): Ditto for sim_store_register interface.
-
-	* sim-if.c (alloc_cpu): Delete.
-	(free_state): Uninstall modules here ...
-	(sim_open): ... and not here.  Call sim_cpu_alloc_all.
-	Set default architecture/model if not specified.
-	(sim_fetch_register,sim_store_register): Rewrite.
-
-	* sim-if.c (h_pc_get,h_pc_set): Delete.  Renamed to sim_pc_[gs]et
-	and moved to common/sim-cpu.c.
-	(sim_create_inferior): Update.
-	(do_trap): Update.
-	* sim-main.h (h_pc_get,h_pc_set): Delete.
-
-	* sim-main.h (sim_cia): Change to USI.
-	(sim_cpu): Move m32r_misc_profile before machine generated part.
-
-Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
-
-        * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Apr 28 18:05:53 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* model.c: Rebuilt.
-	* modelx.c: Rebuilt.
-
-Mon Apr 27 15:36:30 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* cpu.h,model.c,sem-switch.c,sem.c: Regenerated.  Mostly comment
-	and variable renaming due to macro insn additions.
-	* mloop.in: Update to use CGEN_INSN_NUM.
-	* cpux.h,modelx.c,readx.c,semx.c: Regenerated.
-	* mloopx.in: Update to use CGEN_INSN_NUM.
-
-Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Sun Apr 26 15:20:05 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* acconfig.h: New file.
-	* configure.in: Reverted change of Apr 24; use sinclude again.
-
-Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Fri Apr 24 11:19:26 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* configure.in: Don't call sinclude.
-
-Mon Apr 20 16:12:35 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpu.c,sem.c,sem-switch.c: Regenerate.  From
-	- cgen/m32r.cpu (h-accum): Add attribute FUN-ACCESS.
-	* m32r.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
-	#include cgen-ops.h.
-	* cpux.c,readx.c,semx.c: Regenerate.
-	* m32rx.c (m32r_h_accum_get,m32r_h_accum_set): New functions.
-	#include cgen-ops.h.  Delete inclusion of several unnecessary headers.
-	(m32r_h_accums_get): Sign extend top 8 bits.
-
-Tue Apr 14 14:04:07 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* semx.c: Regenerate.
-
-Fri Apr 10 18:22:41 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* cpu.h,decode.c,decode.h,extract.c,sem.c,sem-switch.c: Regenerate.
-	* cpux.h,decodex.c,decodex.h,readx.c,semx.c: Regenerate.
-
-Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Mar 14 20:53:36 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* config.in (HAVE_FCNTL_H): Add.
-	* configure: Regenerate.
-	* Makefile.in (SIM_OBJS): Add devices.o.
-	* m32r-sim.h (m32r_devices): Renamed from m32r_mspr_device.
-	(UART_*): Define m32r serial port parameters.
-	(M32R_DEVICE_ADDR,M32R_DEVICE_LEN): Define.
-	* m32r.c (device_io_{read,write}_buffer,device_error): Move from here,
-	* devices.c: To here.
-	* sim-if.c: Don't include signal.h,sim-core.h.
-	(sim_open): Use M32R_DEVICE_{ADDR,LEN} in sim_core_attach call.
-	(sim_resume): Call sim_module_{resume,suspend}.
-	* m32r.c (m32r_h_cr_{get,set}): Use register number enums.
-
-	* tconfig.in (SIM_HANDLES_LMA): Define.
-
-	* sim-if.c (do_trap): Result is new pc.
-	Handle --environment=operating.
-	* sem-switch.c,sem.c: Regenerate.
-	* semx.c: Regenerate.
-
-Wed Mar 11 14:07:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (syscall_read_mem, syscall_write_mem): Replace
- 	sim_core_*_map with read_map, write_map, exec_map resp.
-
-Wed Mar  4 11:36:51 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (SIM_EXTRA_DEPS): Add cpu-opc.h.
-	(arch.o): Delete cpu-opc.h dependency.
-	(decode.o,model.o): Likewise.
-	(decodex.o,modelx.o): Likewise.
-
-	* cpu.h,model.c,sem-switch.c,sem.c: Regenerate.
-	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
-
-Thu Feb 26 18:38:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Initialize PROFILE_INFO_CPU_CALLBACK.
-
-	* sim-if.c (sim_info): Delete.
-
-Fri Feb 27 10:14:29 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* mloopx.in: Fix handling of branch in parallel with another insn.
-	* semx.c: Regenerate.
-
-Mon Feb 23 13:30:46 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* sim-main.h: #include symcat.h.
-	* m32r-sim.h (BRANCH_NEW_PC): Delete current_cpu arg.
-	(NEW_PC_{BASE,SKIP,2,4,BRANCH_P}): New macros.
-	* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
-	* sem.c,sem-switch.c: Regenerate.
-	* m32r-sim.h (SEM_NEXT_PC): Modify to handle parallel exec.
-	* mloopx.in: Rewrite.
-	* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
-
-Mon Feb 23 12:27:52 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* m32r.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
-	in the backup PC register.
-	* m32rx.c (m32r_h_cr_set, m32r_h_cr_get): Shadow control register 6
-	in the backup PC register.
-
-Thu Feb 19 16:39:35 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r.c (do_lock,do_unlock): Delete.
-	* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
-	* sem.c,sem-switch.c: Regenerate.
-	* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.
-
-Tue Feb 17 18:18:10 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (M32R_OBJS): Add cpu.o.
-	(cpu.o): Add rule for.
-	(NL_TARGET): Define.
-	* configure.in: Add AC_CHECK_PROG(SCHEME).
-	* cpu.c: New file.
-	* cpuall.h,cpu.h,decode.c,decode.h,extract.c,model.c: Regenerate.
-	* sem-switch.c,sem.c: Regenerate.
-	* mloop.in (execute): Update call to semantic fn.
-	(M32RX_OBJS): Add cpux.o.
-	(cpux.o): Add rule for.
-	cpux.c: New file.
-	* cpux.h,decodex.c,decodex.h,modelx.c,readx.c,semx.c: Regenerate.
-	* m32rx.c (m32rx_h_accums_{get,set}): Rewrite.
-	(m32rx_h_cr_{get,set}): New functions.
-	(m32rx_h_accums_{get,set}): New functions.
-	* mloopx.in: Rewrite main loop.
-
-	* m32r.c (do_trap): Move from here.
-	* sim-if.c (do_trap): To here, and rewrite to use CB_SYSCALL support.
-	(sim_create_inferior): Use h_pc_set.
-	(h_pc_{get,set}): New functions.
-	(h_gr_{get,set}): New functions.
-	(syscall_{read,write}_mem): New functions.
-	* sim-main.h (h_{gr,pc}_{get,set}): Declare.
-
-Tue Feb 17 12:44:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_store_register, sim_fetch_register): Pass in
- 	length parameter.  Return -1.
-	(sim_create_inferior): Pass 4 sim_store_register.
-
-Wed Feb 11 19:53:48 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* sim-main.h (CIA_GET,CIA_SET): Provide dummy definitions for now.
-
-	* decode.c, decode.h, sem.c, sem-switch.c, model.c: Regenerate.
-	* cpux.c, decodex.c, decodex.h, readx.c, semx.c, modelx.c: Regenerate.
-
-Mon Feb  9 19:41:54 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* decode.c, sem.c: Regenerate.
-	* cpux.h, decodex.c, readx.c, semx.c: Regenerate.
-	* m32rx.c (m32rx_h_accums_set): New function.
-	(m32rx_model_mark_[gs]et_h_gr): New function.
-	* mloopx.in: Rewrite.
-	* Makefile.in (mloopx.o): Build with -parallel.
-	* sim-main.h (_sim_cpu): Delete member `par_exec'.
-	* tconfig.in (WITH_SEM_SWITCH_FULL): Define as 0 for m32rx.
-
-Thu Feb  5 12:44:31 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in (m32r.o): Depend on cpu.h
-	(extract.o): Pass -DSCACHE_P.
-	* mloop.in (extract{16,32}): Update call to m32r_decode.
-	* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
-	* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
-	* sim-main.h: #include "ansidecl.h".
-	Don't include cpu-opc.h, done by arch.h.
-	* Makefile.in (M32RX_OBJS): Build m32rx support now.
-	(m32rx.o): New rule.
-	* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
-	* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
-	(m32rx_h_accums_get): New function.
-	* mloopx.in: Update call to m32rx_decode.  Rewrite exec loop.
-	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
-
-Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Thu Jan 29 11:22:00 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (M32RX_OBJS): Comment out until m32rx port working.
-	* arch.h (HAVE_CPU_M32R{,X}): Delete, moved to m32r-opc.h.
-	* arch.c (machs): Check ifdef HAVE_CPU_FOO for each entry.
-
-Tue Jan 20 14:16:02 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* cpux.h: Fix duplicate definition of h_accums field for
-	fmt_53_sadd structure.
-
-Tue Jan 20 01:42:17 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* Makefile.in: Add m32rx objs, and rules to build them.
-	* cpux.h, decodex.h, decodex.c, readx.c, semx.c, modelx.c: New files.
-	* m32rx.c, mloopx.in: New files.
-
-Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Jan 19 14:13:40 1998  Doug Evans  <devans@seba.cygnus.com>
-
-	* arch.c, arch.h, cpuall.h: New files.
-	* arch-defs.h: Deleted.
-	* mloop.in: Renamed from mainloop.in.
-	* Makefile.in: Update.
-	* sem-ops.h: Deleted.
-	* mem-ops.h: Deleted.
-	(arch): Renamed from CPU.
-	* cpu.h: New file.
-	* decode.c: Redone.
-	* decode.h: Redone.
-	* extract.c: Redone.
-	* model.c: Redone.
-	* sem-switch.c: Redone.
-	* sem.c: Renamed from semantics.c, and redone.
-	* m32r-sim.h (PROFILE_COUNT_FILLNOPS): Update.
-	(GETTWI,SETTWI,BRANCH_NEW_PC): Define.
-	* m32r.c (WANT_CPU,WANT_CPU_M32R): Define.
-	(m32r_{fetch,store}_register): New functions.
-	(model_mark_{get,set}_h_gr): Prefix with m32r_.
-	(m32r_model_mark_{busy,unbusy}_reg): Prefix with m32r_.
-	(h_cr_{get,set}): Prefix with m32r_.
-	(do_trap): Fetch state from current_cpu, not current_state.
-	Call sim_engine_halt instead of engine_halt.
-	* sim-if.c (alloc_cpu): New function.
-	(free_state): New function.
-	(sim_open): Call sim_state_alloc, and malloc space for selected cpu
-	type.  Call sim_analyze_program.
-	(sim_create_inferior): Handle selected cpu type when setting PC.
-	(sim_resume): Handle m32rx.
-	(sim_stop_reason): Deleted.
-	(print_m32r_misc_cpu): Update.
-	(sim_{fetch,store}_register): Handle m32rx.
-	(sim_{read,write}): Deleted.
-	(sim_engine_illegal_insn): New function.
-	* sim-main.h: Don't include arch-defs.h,sim-core.h,sim-events.h.
-	Include arch.h,cpuall.h.  Include cpu.h,decode.h if m32r.
-	Include cpux.h,decodex.h if m32rx.
-	(_sim_cpu): Include member appropriate cpu_data member for the cpu.
-	(M32R_MISC_PROFILE): Renamed from M32R_PROFILE.
-	(sim_state): Delete members core,events,halt_jmp_buf.
-	Change `cpu' member to be a pointer to the cpu's struct, rather than
-	record inside the state struct.
-	* tconfig.in (WITH_DEVICES): Define here.
-	(WITH_FAST,WITH_SEM_SWITCH_{FULL,FAST}): Define for the cpu.
-
-Fri Jan 16 12:16:56 1998  Nick Clifton  <nickc@cygnus.com>
-
-	* arch-defs.h (INSN_NAME): Fix typo.
-
-Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* m32r-sim.h (MSPR_ADDR): New macro.
-	(m32r_mspr_device): Declare.
-	(struct _device): Define.
-	* m32r.c (m32r_mspr_device): New global.
-	(device_{io_{read,write}_buffer,error}): New functions.
-	* mem-ops.h (SETMEM*): Use sim_core_write_map, not read map.
-	* sim-if.c: Delete redundant inclusion of cpu-sim.h.
-	(sim_open): Attach device to handle MSPR register.
-	* sim-main.h (WITH_DEVICES): Define as 1.
-	Include cpu-sim.h.
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Dec  3 18:08:44 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* configure.in (SIM_AC_OPTION_ENVIRONMENT): Call.
-	* configure: Regenerated.
-
-Wed Nov 19 12:17:08 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* mem-ops.h: Rename SIM_SIG{ACCESS,ALIGN} to SIM_SIG{SEGV,BUS}.
-	* sim-if.c (sim_open): Call sim_config.
-	(sim_stop_reason): Update call to sim_signal_to_host.
-
-Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
-
-Fri Oct 31 18:46:46 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Delete dead call to sim_core_attach.
-
-Mon Oct 27 12:43:54 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* sem-ops.h (U{DIV,MOD}[BHSD]I): Use unsigned division.
-
-Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_SCACHE,
- 	SIM_DEFAULT_MODEL): Delete, moved to common.
-	(SIM_EXTRA_CFLAGS): Update.
-	
-Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (sim_link_links): Configure non-strict memory
- 	alignment.
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 17 17:44:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Allocate memory under sim-memopt module
- 	using sim_do_commandf.
-	(sim_open): Set magic-number at the start.
-	(sim_do_command): Implement.
-
-	* sim-main.h (sim_engine_halt): Map onto engine_halt.
-
-Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep  5 10:21:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-memopt.o module.
-
-Thu Sep  4 10:30:02 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Pass zero modulo arg to sim_core_attach.
-
-Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Tue Aug 26 10:39:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_kill): Delete.
-	(sim_create_inferior): Add ABFD argument.
-	(sim_load): Move setting of PC from here.
-	(sim_create_inferior): To here.
-	(sim_load): Delete, use sim-hload.c instead.
-
-	* Makefile.in (SIM_OBJS): Add sim-hload.o module.
-
-Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Mon Aug 25 15:54:08 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Add ABFD argument.
-
-Tue Jul 22 10:16:16 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* sim-main.h (M32R_DEFAULT_MEM_SIZE): New macro.
-	* sim-if.c (sim_open): Use it.
-
-Wed Jun  4 12:48:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (WITH_ENGINE): Disable the common engine for now.
-
-Tue May 27 14:15:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
-	(sim_write): Ditto for write.
-
-	* m32r.c (do_trap): Ditto for read/write.
-
-Tue May 20 10:18:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Add callback argument.
-	(sim_set_callbacks, sim_callback): Delete.
-	(sim_load): Set STATE_LOADED_P.
-
-Mon May 19 12:55:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Link in sim-abort.o as a stub for
- 	sim_engine_abort.
-
-Mon May  5 12:45:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-if.c (sim_open): Update to reflect changes to core in
- 	../common/.
-	* mem-ops.h (GETMEMQI, GETMEMHI, GETMEMSI, GETMEMDI, GETMEMUQI,
- 	GETMEMUHI, GETMEMUSI, GETMEMUDI, SETMEMQI, SETMEMHI, SETMEMSI,
- 	SETMEMDI, SETMEMUQI, SETMEMUHI, SETMEMUSI, SETMEMUDI): Ditto.
-
-Sat May  3 08:38:55 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* decode.c (decode): Add computed goto support.
-
-Fri May  2 16:30:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mem-ops.h: Stub additional core read/write arguments.
-
-	* sim-main.h: Declare sim_cia - type SI.
-	(struct _sim_cpu): Move base type to end per common.
-	(struct _sim_state): Ditto.
-
-Thu May  1 11:15:34 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	Merge from branch into devo.  CGEN generic files moved to common
-	directory.  K&R C support is no longer provided.
-
-Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Apr 12 12:57:33 1997  Felix Lee  <flee@yin.cygnus.com>
-
-	* Makefile.in, seman-cache.c: new file, for wingdb build.
-	* sim-alloca.h: fixed for wingdb.
-	
-Mon Apr  7 13:33:29 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* decode.c (*): m32r_cgen_insn_table renamed to ..._entries.
-	* mainloop.in: Use CGEN_INSN_INDEX instead of CGEN_INSN_TYPE.
-	* simdefs.h (INSN_NAME): m32r_cgen_insn_table renamed to ..._entries.
-
-Fri Apr  4 19:23:12 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* cgen-utils.in (ex_illegal): Fill in abuf->length, abuf->addr.
-	(exc_illegal): Likewise.
-	* decode.c (decode_vars): Add decode_illegal.
-	* genmloop.sh: #include "cpu-opc.h".
-	* sem-switch.c (case_INSN_ILLEGAL): Declare.
-	(labels): Add case_INSN_ILLEGAL.
-	(SWITCH): Add INSN_ILLEGAL case.
-
-Wed Mar 26 12:34:00 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* model.c (model_module): Use 0 not NULL.
-
-	* genmloop.sh (sim_main_loop): Handle k&r c.
-
-	* sem-switch.c: Regenerate to get k&r c support.
-	* semantics.c: Likewise.
-
-	* m32r.c (ADD_{OV,CA}_SI,SUB_{OV,CA}_SI): Renamed to {ADD,SUB}[OC]FSI.
-	(ADDCSI,SUBCSI): New functions.
-	* sem-switch.c (addv,addv3,addx,subv,subx): Fix carry bit handling.
-	* semantics.c (addv,addv3,addx,subv,subx): Fix carry bit handling.
-
-	* simcache.c (simcache_{install,init,uninstall}): Use
-	DECLARE_MODULE_INSTALL_HANDLER.
-	(simcache_option_handler): Use DECLARE_OPTION_HANDLER.
-
-	* utils.c: #include "semops.h".
-
-Tue Mar 11 14:30:26 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* profile.c (profile_print_simcache): Fix thinko in printf text.
-
-	* simdefs.h (struct argbuf): Add member to fmt_20 so it's not empty.
-
-Mon Mar 10 11:06:29 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* m32r.c (h_cr_get): Rewrite.
-	(h_cr_set): Rewrite.
-	* sem-switch.c (rte): bcarry renamed to bcond.
-	* semantics.c (rte): Likewise.
-	* simdefs.h (CPU_STATE): Likewise.
-
-	* config.in (HAVE_SYS_TIME_H): Add.
-	* configure.in: Check for sys/time.h.
-	* configure: Regenerated.
-	* utils.c: Include sys/time.h if present.
-
-	* common.c (sim_parse_args): Account for NULL terminating entry
-	in long_options table.
-
-	* genmloop.sh (RUN_FAST_P): Don't run fast if tracing.
-	Always use cache if configured in.
-	* mainloop.in (do_extract_insn{16,32}): New functions.
-	(normal,fast): Call them.  Handle starting in left slot.
-	* simcache.c (simcache_option_handler): Disallow -c0.
-	* sem-switch.c (TRACE_RESULT): Redefine so no tracing.
-
-	* profile.c (profile_print_simcache): Fix percentage calc.
-
-	* Makefile.in (INCLUDE_DEPS): Delete simcommon.h.
-
-Sun Mar  9 20:42:17 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* Makefile.in (COMMON_{PRE,POST}_CONFIG_FRAG): Add delimiters for.
-	(M32R_INCLUDE_DEPS): Use cpu-sim.h instead of m32r-sim.h.
-	Add mod-list.h.
-	(mrun.o): Don't depend on M32R_INCLUDE_DEPS.
-	(sim-if.o,m32r.o,utils.o): Likewise.
-	(common.o): Don't explicitly depend on mod-list.h.
-	(mainloop.c): Pass CPU to genmloop.sh.
-	(stamp-modules): Depend on configure.
-	(decode.o): Depend on decode,h, memops.h, semops.h, cpu-opc.h.
-	(extract.o): Depend on decode.h, memops.h, semops.h.
-	(semantics.o,seman-cache.o): Likewise.
-	(model.o,ops.o): Depend on memops.h.
-	(extr-cache.o): Disable building for the moment.
-
-	* simcommon.h: Delete, move contents into cgen-sim.h.
-	* cgen-sim.h: Don't include ansidecl.h,bfd.h,simfns.h.
-	(UINT,CGEN_CAT3): Define.
-	({extract,semantic}_fn_t): Renamed to {EXTRACT,SEMANTIC}_FN.
-	(decode_t): Renamed to DECODE.
-
-	* simfns.h: Delete, contents moved to memops.h,semops.h.
-	* memops.h: New file.
-	* semops.h: New file.
-	* decode.h: Renamed from semantics.h.
-
-	* sim-argv.h: New file.
-	* Makefile.in (memory.o,trace.o,profile.o,simcache.o,common): Add
-	dependency of sim-argv.h.
-
-	* sim-alloca.h: New file.
-	* common.c: Include it.
-	* Makefile.in (common.o): Add dependency.
-
-	* config.in (HAVE_TIME_H,HAVE_SYS_RESOURCE_H): Add.
-	(HAVE_GETRUSAGE,HAVE_TIME): Add.
-	* configure.in: sinclude ../common/aclocal.m4.
-	Check for headers time.h, sys/resource.h.
-	Check for functions time, getrusage.
-	(sim_link_{files,links}): Add link cpu-opc.h.
-	(sim_profile): Add simcache.
-	(SIM_AC_PROFILE): Add simcache, profile.o.
-	(simcache module): Delete extr-cache.o for now.
-	(--enable-sim-cache): Allow specification of default cache size.
-	* configure: Regenerated.
-
-	* decode.c: #include cgen-sim.h,memops.h,semops.h,decode.h,
-	cpu-sim.h,cpu-opc.h.  Don't include m32r-sim.h.
-	Regenerate.
-
-	* extract.c: #include cgen-sim.h,decode.h,cpu-sim.h.
-	Don't include m32r-sim.h.
-	(*): Define/Undef FLD macro.  Use it to reference ARGBUF.
-	Simplify profiling test with PROFILE_MODEL_P.
-	(mvfc,mvtc): Fix access of control registers.
-	* semantic.c: #include cgen-sim.h,memops.h,semops.h,decode.h,cpu-sim.h.
-	Don't include m32r-sim.h.
-	(*): Define/Undef FLD macro.  Use it to reference ARGBUF.
-	Simplify profiling test with PROFILE_MODEL_P.
-	(mvfc,mvtc): Fix access of control registers.
-
-	* sem-switch.c: New file, for GCC computed goto support.
-
-	* genmloop.sh: Add #include's of bfd.h,callback.h,cgen-sim.h,
-	memops.h,semops.h,trace.h,cpu-sim.h.
-	(RUN_FAST_P): Change default to run fast if cache size > 0
-	and not profiling.
-	(sim_main_loop): Record execution time.
-	Record instruction count even in fast mode.
-	(init): Allow cpu to provide init code in mainloop.in.
-	(FAST): Define as 0 or 1 depending on fast mode.
-	* mainloop.in (normal): Combine with fast case.
-	Add support for GCC computed gotos.  Count simcache hits/misses.
-	(init): Initialize "switch" labels if GNUC.
-
-	* cgen-utils.in: Don't include opcode/cgen.h.
-	Include cgen-sim.h, cpu-opc.h.
-	* common.c: Don't include simcommon.h,mod-list.h.  Include cgen-sim.h.
-	* m32r-sim.h: Don't include mod-list.h
-	(RUN_FAST_P): Delete.
-	* m32r.c: Don't include profile.h.  #include ansidecl.h,cgen-sim.h,
-	semops.h,memory.h,trace.h
-	(h_cr_get,h_cr_set): New functions.
-	* memory.c: #include cgen-sim.h,callback.h.
-	* ops.c: Don't include profile.h,m32r-sim.h.
-	Include cgen-sim.h,memops.h,cpu-sim.h.
-	(MEMOPS_DEFINE_INLINE): Renamed from SIMFNS_DEFINE_INLINE.
-	* trace.c: Include cgen-sim.h,cpu-opc.h.
-	* trace.h (trace_insn_{init,fini}): Declare.
-
-	* model.c: Don't include signal.h,stdlib.h,m32r-sim.h.
-	Include cgen-sim.h,cpu-sim.h,cpu-opc.h.
-	Regenerate to get new insn aliases.
-
-	* mrun.c: #include "ansidecl.h".
-	(STATE): Use struct sim_state instead.
-
-	* profile.c: Surround #include <stdlib.h> with HAVE_STDLIB_H.
-	Don't include simcommon.h.  Include cgen-sim.h,cpu-opc.h.
-	(PROFILE_{READ,WRITE}_MASK): Replace with PROFILE_MEMORY_MASK.
-	(profile_print_simcache): New function.
-	(profile_print): Call it.  Print simulator speed stats.
-	* profile.h (PROFILE_{READ,WRITE}_MASK): Replace with
-	PROFILE_MEMORY_MASK.
-	(MODULE_PROFILE_SIMCACHE_P): Define.
-	(PROFILE_SIMCACHE_MASK): Define.
-	(PROFILE_COUNT): New members total_insn_count,exec_time.
-	New members simcache_hits,simcache_misses.
-	(PROFILE_SIMCACHE_{HITS,MISSES}): Define.
-	(PROFILE_MODEL_P): New macro.
-	(PROFILE_COUNT_SIMCACHE_{HIT,MISS}): New macros.
-
-	* sim-if.c: Surround #include <stdlib.h> with HAVE_STDLIB_H.
-	Don't include simcommon.h,m32r-sim.h.  Include cgen-sim.h,cpu-sim.h.
-	(sim_resume): Use USING_SIMCACHE_P instead of RUN_FAST_P.
-	(sim_info): Pass verbose to profile_print.
-
-	* simcache.c: Include cgen-sim.h,callback.h.
-	(USING_SIMCACHE_P): Replace with SIMCACHE_P.
-	(simcache_option_handler): Ensure cache size at least 2.
-	Allow config time specification of default cache size.
-	* simcache.h (struct simcache): Support GCC computed gotos.
-	(SIMCACHE_DEFAULT_CACHE_SIZE): USe CONFIG_SIM_CACHE_SIZE if defined.
-	(USING_SIMCACHE_P): New macro.
-
-	* simdefs.h: Don't include m32r-opc.h.
-	(CGEN_MAX_SIM_INSNS): Define.
-	(CPU_STATE): Regenerate.
-	(ARGBUF): Regenerate.
-	(extract,semantic handler decls): Delete, moved to decode.h.
-
-	* tconfig.in: Don't include cgen-sim.h,m32r-sim.h.
-	(USE_SEM_SWITCH): Define.
-
-	* utils.c: Include bfd.h,time.h,sys/resource.h.
-	(sim_time_get,sim_time_elapsed): New functions.
-	* cgen-sim.h (SIM_TIME,sim_time_get,sim_time_elapsed): Declare.
-
-Fri Jan 31 20:25:06 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure.in (AC_CHECK_HEADERS): Handle i386-windows.
-	* configure: Regenerated.
-	* model.c: #include <stdlib.h>.
-	* simcache.c: #include "libiberty.h".
-	* simcommon.h (alloca): Handle i386-windows.
-
-	* common.c: #include libiberty.h.
-	(sim_signal_to_host): Return 5 if wingdb.
-
-Mon Jan 27 15:22:49 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	* configure.in (sim_cache): Enabled by default now, pass default
-	cache size to --enable-sim-cache.
-	* simcache.c (simcache_option_handler): Allow -c 0.
-
-	* simdefs.h,simfns.h: Regenerate
-	* decode.c,extract.c,model.c,ops.c,semantics.c: Regenerate.
-
-Tue Jan 21 16:21:01 1997  Doug Evans  <dje@seba.cygnus.com>
-
-	Add model profiling support.
-	* configure.in: Handle --enable-sim-model.
-	(sim_profile): Add model.
-	* Makefile.in (model.o): Add rule.
-	* cgen-sim.h (UNIT,INSN_TIMING,MACH,MODEL): New types.
-	* extract.c (*): Add model profiling support.
-	* m32r.c (model_mark_{get,set}_h_gr): New functions.
-	(model_mark_{busy,unbusy}_reg): New functions.
-	* profile.c (profile_option_handler): Recognize --profile model.
-	(profile_print_model): New function.
-	(profile_print): Call it.
-	* profile.h (MODULE_profile_model,MODULE_PROFILE_MODEL_P): Define.
-	(PROFILE_MODEL_MASK,PROFILE_LABEL_WIDTH): Define.
-	(PROFILE_COUNT): New members cycle_count,cti_stall_count,
-	load_stall_count,taken_count,untaken_count.
-	* semantics.c (*): Add model profiling support.
-	* simcommon.h (struct sim_state): New members mach,model.
-	* simdefs.h (CPU_PROFILE,MODEL_TYPE,UNIT_TYPE): New type.
-	(MAX_MODELS,MAX_UNITS): Define.
-	* tconfig.in (STATE_EXTRA_MEMBERS): Add cpu_profile.
-
-	* Makefile.in (INCLUDE_DEPS): Add $(SIM_MODULES_HDRS).
-	(stamp-modules): Depend on genmodlist.sh.
-	* common.c (standard_options): Add --max-insns.
-	(copy_argv): New function.
-	* tconfig.in (SIM_HAVE_MAX_INSNS): Define.
-	* genmloop.sh: Allow mainloop.in to contain support code.
-	* mainloop.in: Move do_insn16,do_insn32 here.
-	* m32r.c (do_trap): Handle SYS_argvlen,SYS_argv,SYS_read.
-	* sim-if.c (sim_open): Don't set max insn count.
-	(sim_create_inferior): Save argv,envp.
-	* simcommon.h (struct sim_state): New members argv,envp.
-	* simdefs.h ([GS]ETTWI,[GS]ETTUWI,[GS]ETTAI): Define.
-	([GS]ETMEMWI,[GS]ETMEMUWI,[GS]ETMEMAI): Define.
-	(ARGBUF): New members h_gr_get, h_gr_set.
-	* trace.c (trace_insn_init,trace_insn_fini): New functions.
-	(trace_printf): Print to buffer, output later by trace_insn_fini.
-	* trace.h (TRACE_INSN_{INIT,FINI}): Define.
-
-Thu Dec 19 16:01:59 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure.in (AC_FUNC_ALLOCA): Call.
-	* configure: Regenerate.
-	* config.h (HAVE_ALLOCA_H): Add.
-	* simcommon.h: Add alloca support.
-	(DECLARE_MODULE_INSTALL_HANDLER): Define.
-	(DECLARE_OPTION_HANDLER): Define.
-	(MEM_FN): Declare using PARAMS.
-	(DECLARE_MEM_FN): Define.
-	* trace.c (trace_result): Tweak for !STDC.
-	* cgen-sim.h (UDI_FN_SUPPORT): Define if ! HAVE_LONGLONG.
-	* cgen-utils.in (disasm_sprintf): Fix va_arg call in !STDC case.
-	* common.c (sim_print_help_fn): Use PARAMS.
-	(standard_option_handler): Fix decl for !STDC systems.
-	* memory.c: #include <stdio.h>
-	(mem_flat_{install,init,uninstall}): Fix decl for !STDC systems.
-	(mem_flat_{read,write},mem_flat_option_handler): Likewise.
-	* profile.c (profile_install): Likewise.
-	(profile_option_handler): Likewise.
-
-Thu Dec 19 11:06:19 1996  Doug Evans  <dje@seba.cygnus.com>
-
-	* semantics.c (*): Don't suffix big unsigned numbers with "U".
-	Prefix them with 0x instead.
-
-	* cgen-sim.h (DI_FN_SUPPORT): Define if ! HAVE_LONGLONG.
-	(SLADI,SRADI,CONVSIDI,CONVDISI): Delete, moved to simfns.h.
-	* semantics.c (machi,maclo,macwhi,macwlo,mulhi,mullo): Implement.
-	(mulwhi,mulwlo,mvtachi,mvtaclo,rac,rach): Implement.
-	* simfns.h: Add decls for functional DI,UDI,SF,DF,XF,TF support.
-	Add support for boolean and/or.
-	* utils.c: Redo naming of DI functional support.
-	(ANDDI,ORDI,ADDDI,MULDI,GEDI,LEDI,CONVHIDI): New functions.
-
-Tue Dec 17 12:57:48 1996  Doug Evans  <dje@seba.cygnus.com>
-
-	* Directory created.
diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in
deleted file mode 100644
index e2dc82f..0000000
--- a/sim/m32r/Makefile.in
+++ /dev/null
@@ -1,192 +0,0 @@
-# Makefile template for Configure for the m32r simulator
-# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2003, 2004
-# Free Software Foundation, Inc.
-# Contributed by Cygnus Support.
-#
-# This file is part of GDB, the GNU debugger.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-## COMMON_PRE_CONFIG_FRAG
-
-M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
-M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
-M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
-TRAPS_OBJ = @traps_obj@
-
-CONFIG_DEVICES = dv-sockser.o
-CONFIG_DEVICES =
-
-SIM_OBJS = \
-	$(SIM_NEW_COMMON_OBJS) \
-	sim-cpu.o \
-	sim-hload.o \
-	sim-hrw.o \
-	sim-model.o \
-	sim-reg.o \
-	cgen-utils.o cgen-trace.o cgen-scache.o \
-	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
-	sim-if.o arch.o \
-	$(M32R_OBJS) \
-	$(M32RX_OBJS) \
-	$(M32R2_OBJS) \
-	$(TRAPS_OBJ) \
-	devices.o \
-	$(CONFIG_DEVICES)
-
-# Extra headers included by sim-main.h.
-SIM_EXTRA_DEPS = \
-	$(CGEN_INCLUDE_DEPS) \
-	arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
-
-SIM_EXTRA_CFLAGS = @sim_extra_cflags@
-
-SIM_RUN_OBJS = nrun.o
-SIM_EXTRA_CLEAN = m32r-clean
-
-# This selects the m32r newlib/libgloss syscall definitions.
-NL_TARGET = -DNL_TARGET_m32r
-
-## COMMON_POST_CONFIG_FRAG
-
-arch = m32r
-
-sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
-
-arch.o: arch.c $(SIM_MAIN_DEPS)
-
-traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
-traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
-devices.o: devices.c $(SIM_MAIN_DEPS)
-
-# M32R objs
-
-M32RBF_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpu.h decode.h eng.h
-
-m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
-
-# FIXME: Use of `mono' is wip.
-mloop.c eng.h: stamp-mloop
-stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh \
-		-mono -fast -pbb -switch sem-switch.c \
-		-cpu m32rbf -infile $(srcdir)/mloop.in
-	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
-	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
-	touch stamp-mloop
-mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
-
-cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
-decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
-sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
-model.o: model.c $(M32RBF_INCLUDE_DEPS)
-
-# M32RX objs
-
-M32RXF_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpux.h decodex.h engx.h
-
-m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
-
-# FIXME: Use of `mono' is wip.
-mloopx.c engx.h: stamp-xmloop
-stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh \
-		-mono -no-fast -pbb -parallel-write -switch semx-switch.c \
-		-cpu m32rxf -infile $(srcdir)/mloopx.in \
-		-outfile-suffix x
-	$(SHELL) $(srcroot)/move-if-change engx.hin engx.h
-	$(SHELL) $(srcroot)/move-if-change mloopx.cin mloopx.c
-	touch stamp-xmloop
-mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
-
-cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
-decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
-semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
-modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
-
-# M32R2 objs
-
-M32R2F_INCLUDE_DEPS = \
-	$(CGEN_MAIN_CPU_DEPS) \
-	cpu2.h decode2.h eng2.h
-
-m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
-
-# FIXME: Use of `mono' is wip.
-mloop2.c eng2.h: stamp-2mloop
-stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh \
-		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
-		-cpu m32r2f -infile $(srcdir)/mloop2.in \
-		-outfile-suffix 2
-	$(SHELL) $(srcroot)/move-if-change eng2.hin eng2.h
-	$(SHELL) $(srcroot)/move-if-change mloop2.cin mloop2.c
-	touch stamp-2mloop
-
-mloop2.o:  mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
-cpu2.o:    cpu2.c    $(M32R2F_INCLUDE_DEPS)
-decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
-sem2.o:    sem2.c    $(M32R2F_INCLUDE_DEPS)
-model2.o:  model2.c  $(M32R2F_INCLUDE_DEPS)
-
-m32r-clean:
-	rm -f mloop.c eng.h stamp-mloop
-	rm -f mloopx.c engx.h stamp-xmloop
-	rm -f mloop2.c eng2.h stamp-2mloop
-	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
-	rm -f tmp-*
-
-# cgen support, enable with --enable-cgen-maint
-CGEN_MAINT = ; @true
-# The following line is commented in or out depending upon --enable-cgen-maint.
-@CGEN_MAINT@CGEN_MAINT =
-
-stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/m32r.cpu
-	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
-	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
-	  FLAGS="with-scache with-profile=fn"
-	touch stamp-arch
-arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
-
-stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
-	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=m32rbf mach=m32r SUFFIX= \
-	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
-	  FLAGS="with-scache with-profile=fn" \
-	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
-	touch stamp-cpu
-cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
-
-stamp-xcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
-	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=m32rxf mach=m32rx SUFFIX=x \
-	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
-	  FLAGS="with-scache with-profile=fn" \
-	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
-	touch stamp-xcpu
-cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
-
-stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
-	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
-	  cpu=m32r2f mach=m32r2 SUFFIX=2 \
-	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
-	  FLAGS="with-scache with-profile=fn" \
-	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
-	touch stamp-2cpu
-cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
diff --git a/sim/m32r/README b/sim/m32r/README
deleted file mode 100644
index bbc3f50..0000000
--- a/sim/m32r/README
+++ /dev/null
@@ -1,14 +0,0 @@
-This is the m32r simulator directory.
-
-It is still work-in-progress.  The current sources are reasonably
-well tested and lots of features are in.  However, there's lots
-more yet to come.
-
-There are lots of machine generated files in the source directory!
-They are only generated if you configure with --enable-cgen-maint,
-similar in behaviour to Makefile.in, configure under automake/autoconf.
-
-For details on the generator, see ../../cgen.
-
-devo/cgen isn't part of the comp-tools module yet.
-You'll need to check it out manually (also akin to automake/autoconf).
diff --git a/sim/m32r/TODO b/sim/m32r/TODO
deleted file mode 100644
index 263daac..0000000
--- a/sim/m32r/TODO
+++ /dev/null
@@ -1,9 +0,0 @@
-- header file dependencies revisit
-- hooks cleanup
-- testsuites
-- FIXME's
-- memory accesses still test if profiling is on even in fast mode
-- fill nop counting done even in fast mode
-- have semantic code use G/SET_H_FOO if not default [incl fun-access]
-- have G/SET_H_FOO macros call function if fun-access
-- --> can always use G/S_H_FOO macros
diff --git a/sim/m32r/acconfig.h b/sim/m32r/acconfig.h
deleted file mode 100644
index f9b87a1..0000000
--- a/sim/m32r/acconfig.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
-#undef HAVE_CATGETS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
diff --git a/sim/m32r/arch.c b/sim/m32r/arch.c
deleted file mode 100644
index cbdcfba..0000000
--- a/sim/m32r/arch.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Simulator support for m32r.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#include "sim-main.h"
-#include "bfd.h"
-
-const MACH *sim_machs[] =
-{
-#ifdef HAVE_CPU_M32RBF
-  & m32r_mach,
-#endif
-#ifdef HAVE_CPU_M32RXF
-  & m32rx_mach,
-#endif
-#ifdef HAVE_CPU_M32R2F
-  & m32r2_mach,
-#endif
-  0
-};
-
diff --git a/sim/m32r/arch.h b/sim/m32r/arch.h
deleted file mode 100644
index a544d47..0000000
--- a/sim/m32r/arch.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Simulator header for m32r.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32R_ARCH_H
-#define M32R_ARCH_H
-
-#define TARGET_BIG_ENDIAN 1
-
-/* Enum declaration for model types.  */
-typedef enum model_type {
-  MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_M32R2
- , MODEL_MAX
-} MODEL_TYPE;
-
-#define MAX_MODELS ((int) MODEL_MAX)
-
-/* Enum declaration for unit types.  */
-typedef enum unit_type {
-  UNIT_NONE, UNIT_M32R_D_U_STORE, UNIT_M32R_D_U_LOAD, UNIT_M32R_D_U_CTI
- , UNIT_M32R_D_U_MAC, UNIT_M32R_D_U_CMP, UNIT_M32R_D_U_EXEC, UNIT_TEST_U_EXEC
- , UNIT_M32RX_U_STORE, UNIT_M32RX_U_LOAD, UNIT_M32RX_U_CTI, UNIT_M32RX_U_MAC
- , UNIT_M32RX_U_CMP, UNIT_M32RX_U_EXEC, UNIT_M32R2_U_STORE, UNIT_M32R2_U_LOAD
- , UNIT_M32R2_U_CTI, UNIT_M32R2_U_MAC, UNIT_M32R2_U_CMP, UNIT_M32R2_U_EXEC
- , UNIT_MAX
-} UNIT_TYPE;
-
-#define MAX_UNITS (2)
-
-#endif /* M32R_ARCH_H */
diff --git a/sim/m32r/config.in b/sim/m32r/config.in
deleted file mode 100644
index 9723b86..0000000
--- a/sim/m32r/config.in
+++ /dev/null
@@ -1,162 +0,0 @@
-/* config.in.  Generated automatically from configure.in by autoheader.  */
-
-/* Define if using alloca.c.  */
-#undef C_ALLOCA
-
-/* Define to empty if the keyword does not work.  */
-#undef const
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define if you have a working `mmap' system call.  */
-#undef HAVE_MMAP
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#undef inline
-
-/* Define to `long' if <sys/types.h> doesn't define.  */
-#undef off_t
-
-/* Define if you need to in order for stat and other things to work.  */
-#undef _POSIX_SOURCE
-
-/* Define as the return type of signal handlers (int or void).  */
-#undef RETSIGTYPE
-
-/* Define to `unsigned' if <sys/types.h> doesn't define.  */
-#undef size_t
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#undef STACK_DIRECTION
-
-/* Define if you have the ANSI C header files.  */
-#undef STDC_HEADERS
-
-/* Define if your processor stores words with the most significant
-   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
-#undef WORDS_BIGENDIAN
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
-
-/* Define if you have the __argz_count function.  */
-#undef HAVE___ARGZ_COUNT
-
-/* Define if you have the __argz_next function.  */
-#undef HAVE___ARGZ_NEXT
-
-/* Define if you have the __argz_stringify function.  */
-#undef HAVE___ARGZ_STRINGIFY
-
-/* Define if you have the __setfpucw function.  */
-#undef HAVE___SETFPUCW
-
-/* Define if you have the dcgettext function.  */
-#undef HAVE_DCGETTEXT
-
-/* Define if you have the getcwd function.  */
-#undef HAVE_GETCWD
-
-/* Define if you have the getpagesize function.  */
-#undef HAVE_GETPAGESIZE
-
-/* Define if you have the getrusage function.  */
-#undef HAVE_GETRUSAGE
-
-/* Define if you have the munmap function.  */
-#undef HAVE_MUNMAP
-
-/* Define if you have the putenv function.  */
-#undef HAVE_PUTENV
-
-/* Define if you have the setenv function.  */
-#undef HAVE_SETENV
-
-/* Define if you have the setlocale function.  */
-#undef HAVE_SETLOCALE
-
-/* Define if you have the sigaction function.  */
-#undef HAVE_SIGACTION
-
-/* Define if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if you have the strcasecmp function.  */
-#undef HAVE_STRCASECMP
-
-/* Define if you have the strchr function.  */
-#undef HAVE_STRCHR
-
-/* Define if you have the time function.  */
-#undef HAVE_TIME
-
-/* Define if you have the <argz.h> header file.  */
-#undef HAVE_ARGZ_H
-
-/* Define if you have the <fcntl.h> header file.  */
-#undef HAVE_FCNTL_H
-
-/* Define if you have the <fpu_control.h> header file.  */
-#undef HAVE_FPU_CONTROL_H
-
-/* Define if you have the <limits.h> header file.  */
-#undef HAVE_LIMITS_H
-
-/* Define if you have the <locale.h> header file.  */
-#undef HAVE_LOCALE_H
-
-/* Define if you have the <malloc.h> header file.  */
-#undef HAVE_MALLOC_H
-
-/* Define if you have the <nl_types.h> header file.  */
-#undef HAVE_NL_TYPES_H
-
-/* Define if you have the <stdlib.h> header file.  */
-#undef HAVE_STDLIB_H
-
-/* Define if you have the <string.h> header file.  */
-#undef HAVE_STRING_H
-
-/* Define if you have the <strings.h> header file.  */
-#undef HAVE_STRINGS_H
-
-/* Define if you have the <sys/param.h> header file.  */
-#undef HAVE_SYS_PARAM_H
-
-/* Define if you have the <sys/resource.h> header file.  */
-#undef HAVE_SYS_RESOURCE_H
-
-/* Define if you have the <sys/time.h> header file.  */
-#undef HAVE_SYS_TIME_H
-
-/* Define if you have the <time.h> header file.  */
-#undef HAVE_TIME_H
-
-/* Define if you have the <unistd.h> header file.  */
-#undef HAVE_UNISTD_H
-
-/* Define if you have the <values.h> header file.  */
-#undef HAVE_VALUES_H
diff --git a/sim/m32r/configure b/sim/m32r/configure
deleted file mode 100755
index efc2dc6..0000000
--- a/sim/m32r/configure
+++ /dev/null
@@ -1,6332 +0,0 @@
-#! /bin/sh
-# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59.
-#
-# Copyright (C) 2003 Free Software Foundation, Inc.
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
-	 /*)
-	   if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
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-rm -f conf$$ conf$$.exe conf$$.file
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-# CDPATH.
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-# Name of the host.
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-exec 6>&1
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-ac_unique_file="Makefile.in"
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-x_includes=NONE
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-# Installation directory options.
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-ac_prev=
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-  -host | --host | --hos | --ho)
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-  -infodir | --infodir | --infodi | --infod | --info | --inf)
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-  -libdir | --libdir | --libdi | --libd)
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-  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
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-  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
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-
-  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
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-  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
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-  -program-suffix | --program-suffix | --program-suffi | --program-suff \
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-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
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-ac_env_build_alias_set=${build_alias+set}
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-ac_cv_env_target_alias_value=$target_alias
-ac_env_CC_set=${CC+set}
-ac_env_CC_value=$CC
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-ac_cv_env_CC_value=$CC
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-\`configure' configures this package to adapt to many kinds of systems.
-
-Usage: $0 [OPTION]... [VAR=VALUE]...
-
-To assign environment variables (e.g., CC, CFLAGS...), specify them as
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-
-Defaults for the options are specified in brackets.
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-Configuration:
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-
-_ACEOF
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-  cat <<_ACEOF
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-			  [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-			  [PREFIX]
-
-By default, \`make install' will install all the files in
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-For better control, use the options below.
-
-Fine tuning of the installation directories:
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-System types:
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-if test -n "$ac_init_help"; then
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-  cat <<\_ACEOF
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-Optional Features:
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-  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator
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-  --enable-sim-endian=endian		Specify target byte endian orientation.
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-  --enable-sim-hostendian=end		Specify host byte endian orientation.
-  --enable-sim-scache=size		Specify simulator execution cache size.
-  --enable-sim-default-model=model	Specify default model to simulate.
-  --enable-sim-environment=environment	Specify mixed, user, virtual or operating environment.
-  --enable-sim-inline=inlines		Specify which functions should be inlined.
-  --enable-cgen-maint=DIR    build cgen generated files
-
-Some influential environment variables:
-  CC          C compiler command
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-  CPP         C preprocessor
-
-Use these variables to override the choices made by `configure' or to help
-it to find libraries and programs with nonstandard names/locations.
-
-_ACEOF
-fi
-
-if test "$ac_init_help" = "recursive"; then
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-# Do not use `cd foo && pwd` to compute absolute paths, because
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-.) ac_abs_builddir="$ac_dir";;
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-  .) ac_abs_builddir=`pwd`;;
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-.) ac_abs_top_builddir=${ac_top_builddir}.;;
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-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
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-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
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-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
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-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
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-    cd $ac_dir
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-      echo
-      $SHELL $ac_srcdir/configure  --help=recursive
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-	   test -f $ac_srcdir/configure.in; then
-      echo
-      $ac_configure --help
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-      echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
-    fi
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-test -n "$ac_init_help" && exit 0
-if $ac_init_version; then
-  cat <<\_ACEOF
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This configure script is free software; the Free Software Foundation
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-_ACEOF
-  exit 0
-fi
-exec 5>config.log
-cat >&5 <<_ACEOF
-This file contains any messages produced by compilers while
-running configure, to aid debugging if configure makes a mistake.
-
-It was created by $as_me, which was
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-  $ $0 $@
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-_ACEOF
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-uname -s = `(uname -s) 2>/dev/null || echo unknown`
-uname -v = `(uname -v) 2>/dev/null || echo unknown`
-
-/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
-/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
-
-/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
-/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
-/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
-hostinfo               = `(hostinfo) 2>/dev/null               || echo unknown`
-/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
-/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
-/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
-
-_ASUNAME
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-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
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-} >&5
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-cat >&5 <<_ACEOF
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-_ACEOF
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-# Predefined preprocessor variables.
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-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_NAME "$PACKAGE_NAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_VERSION "$PACKAGE_VERSION"
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-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_STRING "$PACKAGE_STRING"
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-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
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-# Let the site file select an alternate cache file if it wants to.
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-# Check that the precious variables saved in the cache have kept the same
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-ac_cache_corrupted=false
-for ac_var in `(set) 2>&1 |
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-      ac_cache_corrupted=: ;;
-    ,set)
-      { echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
-echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
-      ac_cache_corrupted=: ;;
-    ,);;
-    *)
-      if test "x$ac_old_val" != "x$ac_new_val"; then
-	{ echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
-echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
-	{ echo "$as_me:$LINENO:   former value:  $ac_old_val" >&5
-echo "$as_me:   former value:  $ac_old_val" >&2;}
-	{ echo "$as_me:$LINENO:   current value: $ac_new_val" >&5
-echo "$as_me:   current value: $ac_new_val" >&2;}
-	ac_cache_corrupted=:
-      fi;;
-  esac
-  # Pass precious variables to config.status.
-  if test "$ac_new_set" = set; then
-    case $ac_new_val in
-    *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
-    *) ac_arg=$ac_var=$ac_new_val ;;
-    esac
-    case " $ac_configure_args " in
-      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
-      *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
-    esac
-  fi
-done
-if $ac_cache_corrupted; then
-  { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
-echo "$as_me: error: changes in the environment can compromise the build" >&2;}
-  { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
-echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-          ac_config_headers="$ac_config_headers config.h:config.in"
-
-
-# This file contains common code used by all simulators.
-#
-# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be invoked before any target specific stuff.
-# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
-# It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# sinclude(../common/aclocal.m4)
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-#
-# SIM_AC_COMMON
-#
-# ... target specific stuff ...
-#
-# SIM_AC_OUTPUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-sim_inline="-DDEFAULT_INLINE=0"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-# intl sister-directory configuration rules.
-#
-
-# The idea behind this macro is that there's no need to repeat all the
-# autoconf probes done by the intl directory - it's already done them
-# for us.  In fact, there's no need even to look at the cache for the
-# answers.  All we need to do is nab a few pieces of information.
-# The intl directory is set up to make this easy, by generating a
-# small file which can be sourced as a shell script; then we produce
-# the necessary substitutions and definitions for this directory.
-
-
-
-
-
-
-
-# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
-# it by inlining the macro's contents.
-# This file contains common code used by all simulators.
-#
-# common.m4 invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be included before any target specific
-# stuff.  SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
-# the Makefile.  It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-# AC_CONFIG_HEADER(config.h:config.in)
-#
-# sinclude(../common/aclocal.m4)
-# sinclude(../common/common.m4)
-#
-# ... target specific stuff ...
-
-ac_aux_dir=
-for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  elif test -f $ac_dir/shtool; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/shtool install -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&5
-echo "$as_me: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-ac_config_guess="$SHELL $ac_aux_dir/config.guess"
-ac_config_sub="$SHELL $ac_aux_dir/config.sub"
-ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
-
-# Make sure we can run config.sub.
-$ac_config_sub sun4 >/dev/null 2>&1 ||
-  { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
-echo "$as_me: error: cannot run $ac_config_sub" >&2;}
-   { (exit 1); exit 1; }; }
-
-echo "$as_me:$LINENO: checking build system type" >&5
-echo $ECHO_N "checking build system type... $ECHO_C" >&6
-if test "${ac_cv_build+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_build_alias=$build_alias
-test -z "$ac_cv_build_alias" &&
-  ac_cv_build_alias=`$ac_config_guess`
-test -z "$ac_cv_build_alias" &&
-  { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
-echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
-   { (exit 1); exit 1; }; }
-ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_build" >&5
-echo "${ECHO_T}$ac_cv_build" >&6
-build=$ac_cv_build
-build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking host system type" >&5
-echo $ECHO_N "checking host system type... $ECHO_C" >&6
-if test "${ac_cv_host+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_host_alias=$host_alias
-test -z "$ac_cv_host_alias" &&
-  ac_cv_host_alias=$ac_cv_build_alias
-ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_host" >&5
-echo "${ECHO_T}$ac_cv_host" >&6
-host=$ac_cv_host
-host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking target system type" >&5
-echo $ECHO_N "checking target system type... $ECHO_C" >&6
-if test "${ac_cv_target+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_target_alias=$target_alias
-test "x$ac_cv_target_alias" = "x" &&
-  ac_cv_target_alias=$ac_cv_host_alias
-ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_target" >&5
-echo "${ECHO_T}$ac_cv_target" >&6
-target=$ac_cv_target
-target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-# The aliases save the names the user supplied, while $host etc.
-# will get canonicalized.
-test -n "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
-  program_prefix=${target_alias}-
-test "$program_prefix" != NONE &&
-  program_transform_name="s,^,$program_prefix,;$program_transform_name"
-# Use a double $ so make ignores it.
-test "$program_suffix" != NONE &&
-  program_transform_name="s,\$,$program_suffix,;$program_transform_name"
-# Double any \ or $.  echo might interpret backslashes.
-# By default was `s,x,x', remove it if useless.
-cat <<\_ACEOF >conftest.sed
-s/[\\$]/&&/g;s/;s,x,x,$//
-_ACEOF
-program_transform_name=`echo $program_transform_name | sed -f conftest.sed`
-rm conftest.sed
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-fi
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  ac_prog_rejected=no
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
-       ac_prog_rejected=yes
-       continue
-     fi
-    ac_cv_prog_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# != 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
-  fi
-fi
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  for ac_prog in cl
-  do
-    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
-set dummy $ac_tool_prefix$ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-    test -n "$CC" && break
-  done
-fi
-if test -z "$CC"; then
-  ac_ct_CC=$CC
-  for ac_prog in cl
-do
-  # Extract the first word of "$ac_prog", so it can be a program name with args.
-set dummy $ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  test -n "$ac_ct_CC" && break
-done
-
-  CC=$ac_ct_CC
-fi
-
-fi
-
-
-test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&5
-echo "$as_me: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-
-# Provide some information about the compiler.
-echo "$as_me:$LINENO:" \
-     "checking for C compiler version" >&5
-ac_compiler=`set X $ac_compile; echo $2`
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
-  (eval $ac_compiler --version </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5
-  (eval $ac_compiler -v </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5
-  (eval $ac_compiler -V </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files a.out a.exe b.out"
-# Try to create an executable without -o first, disregard a.out.
-# It will help us diagnose broken compilers, and finding out an intuition
-# of exeext.
-echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
-echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6
-ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
-if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5
-  (eval $ac_link_default) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # Find the output, starting from the most likely.  This scheme is
-# not robust to junk in `.', hence go to wildcards (a.*) only as a last
-# resort.
-
-# Be careful to initialize this variable, since it used to be cached.
-# Otherwise an old cache value of `no' led to `EXEEXT = no' in a Makefile.
-ac_cv_exeext=
-# b.out is created by i960 compilers.
-for ac_file in a_out.exe a.exe conftest.exe a.out conftest a.* conftest.* b.out
-do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj )
-	;;
-    conftest.$ac_ext )
-	# This is the source file.
-	;;
-    [ab].out )
-	# We found the default executable, but exeext='' is most
-	# certainly right.
-	break;;
-    *.* )
-	ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	# FIXME: I believe we export ac_cv_exeext for Libtool,
-	# but it would be cool to find out if it's true.  Does anybody
-	# maintain Libtool? --akim.
-	export ac_cv_exeext
-	break;;
-    * )
-	break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: C compiler cannot create executables
-See \`config.log' for more details." >&5
-echo "$as_me: error: C compiler cannot create executables
-See \`config.log' for more details." >&2;}
-   { (exit 77); exit 77; }; }
-fi
-
-ac_exeext=$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_file" >&5
-echo "${ECHO_T}$ac_file" >&6
-
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether the C compiler works" >&5
-echo $ECHO_N "checking whether the C compiler works... $ECHO_C" >&6
-# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
-# If not cross compiling, check that we can run a simple program.
-if test "$cross_compiling" != yes; then
-  if { ac_try='./$ac_file'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-    cross_compiling=no
-  else
-    if test "$cross_compiling" = maybe; then
-	cross_compiling=yes
-    else
-	{ { echo "$as_me:$LINENO: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-    fi
-  fi
-fi
-echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-
-rm -f a.out a.exe conftest$ac_cv_exeext b.out
-ac_clean_files=$ac_clean_files_save
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
-echo $ECHO_N "checking whether we are cross compiling... $ECHO_C" >&6
-echo "$as_me:$LINENO: result: $cross_compiling" >&5
-echo "${ECHO_T}$cross_compiling" >&6
-
-echo "$as_me:$LINENO: checking for suffix of executables" >&5
-echo $ECHO_N "checking for suffix of executables... $ECHO_C" >&6
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # If both `conftest.exe' and `conftest' are `present' (well, observable)
-# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
-# work properly (i.e., refer to `conftest.exe'), while it won't with
-# `rm'.
-for ac_file in conftest.exe conftest conftest.*; do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;;
-    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	  export ac_cv_exeext
-	  break;;
-    * ) break;;
-  esac
-done
-else
-  { { echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
-echo "${ECHO_T}$ac_cv_exeext" >&6
-
-rm -f conftest.$ac_ext
-EXEEXT=$ac_cv_exeext
-ac_exeext=$EXEEXT
-echo "$as_me:$LINENO: checking for suffix of object files" >&5
-echo $ECHO_N "checking for suffix of object files... $ECHO_C" >&6
-if test "${ac_cv_objext+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.o conftest.obj
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  for ac_file in `(ls conftest.o conftest.obj; ls conftest.*) 2>/dev/null`; do
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg ) ;;
-    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
-       break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest.$ac_cv_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
-echo "${ECHO_T}$ac_cv_objext" >&6
-OBJEXT=$ac_cv_objext
-ac_objext=$OBJEXT
-echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
-echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6
-if test "${ac_cv_c_compiler_gnu+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-#ifndef __GNUC__
-       choke me
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_compiler_gnu=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_compiler_gnu=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_cv_c_compiler_gnu=$ac_compiler_gnu
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
-echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6
-GCC=`test $ac_compiler_gnu = yes && echo yes`
-ac_test_CFLAGS=${CFLAGS+set}
-ac_save_CFLAGS=$CFLAGS
-CFLAGS="-g"
-echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
-echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_g+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_g=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_prog_cc_g=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_g" >&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS=$ac_save_CFLAGS
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5
-echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_prog_cc_stdc=no
-ac_save_CC=$CC
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdarg.h>
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
-struct buf { int x; };
-FILE * (*rcsopen) (struct buf *, struct stat *, int);
-static char *e (p, i)
-     char **p;
-     int i;
-{
-  return p[i];
-}
-static char *f (char * (*g) (char **, int), char **p, ...)
-{
-  char *s;
-  va_list v;
-  va_start (v,p);
-  s = g (p, va_arg (v,int));
-  va_end (v);
-  return s;
-}
-
-/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
-   function prototypes and stuff, but not '\xHH' hex character constants.
-   These don't provoke an error unfortunately, instead are silently treated
-   as 'x'.  The following induces an error, until -std1 is added to get
-   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
-   array size at least.  It's necessary to write '\x00'==0 to get something
-   that's true only with -std1.  */
-int osf4_cc_array ['\x00' == 0 ? 1 : -1];
-
-int test (int i, double x);
-struct s1 {int (*f) (int a);};
-struct s2 {int (*f) (double a);};
-int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
-int argc;
-char **argv;
-int
-main ()
-{
-return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
-  ;
-  return 0;
-}
-_ACEOF
-# Don't try gcc -ansi; that turns off useful extensions and
-# breaks some systems' header files.
-# AIX			-qlanglvl=ansi
-# Ultrix and OSF/1	-std1
-# HP-UX 10.20 and later	-Ae
-# HP-UX older versions	-Aa -D_HPUX_SOURCE
-# SVR4			-Xc -D__EXTENSIONS__
-for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
-do
-  CC="$ac_save_CC $ac_arg"
-  rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_stdc=$ac_arg
-break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext
-done
-rm -f conftest.$ac_ext conftest.$ac_objext
-CC=$ac_save_CC
-
-fi
-
-case "x$ac_cv_prog_cc_stdc" in
-  x|xno)
-    echo "$as_me:$LINENO: result: none needed" >&5
-echo "${ECHO_T}none needed" >&6 ;;
-  *)
-    echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6
-    CC="$CC $ac_cv_prog_cc_stdc" ;;
-esac
-
-# Some people use a C++ compiler to compile C.  Since we use `exit',
-# in C++ we need to declare it.  In case someone uses the same compiler
-# for both compiling C and C++ we need to have the C++ compiler decide
-# the declaration of exit, since it's the most demanding environment.
-cat >conftest.$ac_ext <<_ACEOF
-#ifndef __cplusplus
-  choke me
-#endif
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  for ac_declaration in \
-   '' \
-   'extern "C" void std::exit (int) throw (); using std::exit;' \
-   'extern "C" void std::exit (int); using std::exit;' \
-   'extern "C" void exit (int) throw ();' \
-   'extern "C" void exit (int);' \
-   'void exit (int);'
-do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-#include <stdlib.h>
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-continue
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
-rm -f conftest*
-if test -n "$ac_declaration"; then
-  echo '#ifdef __cplusplus' >>confdefs.h
-  echo $ac_declaration      >>confdefs.h
-  echo '#endif'             >>confdefs.h
-fi
-
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-# Find a good install program.  We prefer a C program (faster),
-# so one script is as good as another.  But avoid the broken or
-# incompatible versions:
-# SysV /etc/install, /usr/sbin/install
-# SunOS /usr/etc/install
-# IRIX /sbin/install
-# AIX /bin/install
-# AmigaOS /C/install, which installs bootblocks on floppy discs
-# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
-# AFS /usr/afsws/bin/install, which mishandles nonexistent args
-# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
-# OS/2's system install, which has a completely different semantic
-# ./install, which can be erroneously created by make from ./install.sh.
-echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
-echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6
-if test -z "$INSTALL"; then
-if test "${ac_cv_path_install+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  # Account for people who put trailing slashes in PATH elements.
-case $as_dir/ in
-  ./ | .// | /cC/* | \
-  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
-  ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
-  /usr/ucb/* ) ;;
-  *)
-    # OSF1 and SCO ODT 3.0 have their own names for install.
-    # Don't use installbsd from OSF since it installs stuff as root
-    # by default.
-    for ac_prog in ginstall scoinst install; do
-      for ac_exec_ext in '' $ac_executable_extensions; do
-	if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
-	  if test $ac_prog = install &&
-	    grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # AIX install.  It has an incompatible calling convention.
-	    :
-	  elif test $ac_prog = install &&
-	    grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # program-specific install script used by HP pwplus--don't use.
-	    :
-	  else
-	    ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
-	    break 3
-	  fi
-	fi
-      done
-    done
-    ;;
-esac
-done
-
-
-fi
-  if test "${ac_cv_path_install+set}" = set; then
-    INSTALL=$ac_cv_path_install
-  else
-    # As a last resort, use the slow shell script.  We don't cache a
-    # path for INSTALL within a source directory, because that will
-    # break other packages using the cache if that directory is
-    # removed, or if the path is relative.
-    INSTALL=$ac_install_sh
-  fi
-fi
-echo "$as_me:$LINENO: result: $INSTALL" >&5
-echo "${ECHO_T}$INSTALL" >&6
-
-# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
-# It thinks the first close brace ends the variable substitution.
-test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
-
-test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
-
-test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
-
-
-# Put a plausible default for CC_FOR_BUILD in Makefile.
-if test "x$cross_compiling" = "xno"; then
-  CC_FOR_BUILD='$(CC)'
-else
-  CC_FOR_BUILD=gcc
-fi
-
-
-
-
-AR=${AR-ar}
-
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
-fi
-fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  RANLIB=$ac_ct_RANLIB
-else
-  RANLIB="$ac_cv_prog_RANLIB"
-fi
-
-
-ALL_LINGUAS=
-# If we haven't got the data from the intl directory,
-# assume NLS is disabled.
-USE_NLS=no
-LIBINTL=
-LIBINTL_DEP=
-INCINTL=
-XGETTEXT=
-GMSGFMT=
-POSUB=
-
-if test -f  ../../intl/config.intl; then
-  .  ../../intl/config.intl
-fi
-echo "$as_me:$LINENO: checking whether NLS is requested" >&5
-echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
-if test x"$USE_NLS" != xyes; then
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-else
-  echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-
-cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
-
-  echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
-echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
-  # Look for .po and .gmo files in the source directory.
-  CATALOGS=
-  XLINGUAS=
-  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
-    # If there aren't any .gmo files the shell will give us the
-    # literal string "../path/to/srcdir/po/*.gmo" which has to be
-    # weeded out.
-    case "$cat" in *\**)
-      continue;;
-    esac
-    # The quadruple backslash is collapsed to a double backslash
-    # by the backticks, then collapsed again by the double quotes,
-    # leaving us with one backslash in the sed expression (right
-    # before the dot that mustn't act as a wildcard).
-    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
-    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
-    # The user is allowed to set LINGUAS to a list of languages to
-    # install catalogs for.  If it's empty that means "all of them."
-    if test "x$LINGUAS" = x; then
-      CATALOGS="$CATALOGS $cat"
-      XLINGUAS="$XLINGUAS $lang"
-    else
-      case "$LINGUAS" in *$lang*)
-        CATALOGS="$CATALOGS $cat"
-        XLINGUAS="$XLINGUAS $lang"
-        ;;
-      esac
-    fi
-  done
-  LINGUAS="$XLINGUAS"
-  echo "$as_me:$LINENO: result: $LINGUAS" >&5
-echo "${ECHO_T}$LINGUAS" >&6
-
-
-    DATADIRNAME=share
-
-  INSTOBJEXT=.mo
-
-  GENCAT=gencat
-
-  CATOBJEXT=.gmo
-
-fi
-
-# Check for common headers.
-# FIXME: Seems to me this can cause problems for i386-windows hosts.
-# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
-echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-  if test "${ac_cv_prog_CPP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-      # Double quotes because CPP needs to be expanded
-    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
-    do
-      ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  break
-fi
-
-    done
-    ac_cv_prog_CPP=$CPP
-
-fi
-  CPP=$ac_cv_prog_CPP
-else
-  ac_cv_prog_CPP=$CPP
-fi
-echo "$as_me:$LINENO: result: $CPP" >&5
-echo "${ECHO_T}$CPP" >&6
-ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  :
-else
-  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&5
-echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-echo "$as_me:$LINENO: checking for egrep" >&5
-echo $ECHO_N "checking for egrep... $ECHO_C" >&6
-if test "${ac_cv_prog_egrep+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
-    then ac_cv_prog_egrep='grep -E'
-    else ac_cv_prog_egrep='egrep'
-    fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
-echo "${ECHO_T}$ac_cv_prog_egrep" >&6
- EGREP=$ac_cv_prog_egrep
-
-
-echo "$as_me:$LINENO: checking for ANSI C header files" >&5
-echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
-if test "${ac_cv_header_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_header_stdc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_header_stdc=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <string.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "memchr" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "free" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-  if test "$cross_compiling" = yes; then
-  :
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ctype.h>
-#if ((' ' & 0x0FF) == 0x020)
-# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#else
-# define ISLOWER(c) \
-		   (('a' <= (c) && (c) <= 'i') \
-		     || ('j' <= (c) && (c) <= 'r') \
-		     || ('s' <= (c) && (c) <= 'z'))
-# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
-#endif
-
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int
-main ()
-{
-  int i;
-  for (i = 0; i < 256; i++)
-    if (XOR (islower (i), ISLOWER (i))
-	|| toupper (i) != TOUPPER (i))
-      exit(2);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_header_stdc=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
-echo "${ECHO_T}$ac_cv_header_stdc" >&6
-if test $ac_cv_header_stdc = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define STDC_HEADERS 1
-_ACEOF
-
-fi
-
-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-
-
-
-
-
-
-
-
-
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-		  inttypes.h stdint.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_Header=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_Header=no"
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-
-
-for ac_header in stdlib.h string.h strings.h unistd.h time.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in sys/time.h sys/resource.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in fcntl.h fpu_control.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-for ac_header in dlfcn.h errno.h sys/stat.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-for ac_func in getrusage time sigaction __setfpucw
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-# Check for socket libraries
-
-echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
-echo $ECHO_N "checking for bind in -lsocket... $ECHO_C" >&6
-if test "${ac_cv_lib_socket_bind+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lsocket  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bind ();
-int
-main ()
-{
-bind ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_socket_bind=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_socket_bind=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
-echo "${ECHO_T}$ac_cv_lib_socket_bind" >&6
-if test $ac_cv_lib_socket_bind = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBSOCKET 1
-_ACEOF
-
-  LIBS="-lsocket $LIBS"
-
-fi
-
-
-echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
-echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6
-if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lnsl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char gethostbyname ();
-int
-main ()
-{
-gethostbyname ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_nsl_gethostbyname=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_nsl_gethostbyname=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
-echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6
-if test $ac_cv_lib_nsl_gethostbyname = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBNSL 1
-_ACEOF
-
-  LIBS="-lnsl $LIBS"
-
-fi
-
-
-. ${srcdir}/../../bfd/configure.host
-
-
-
-USE_MAINTAINER_MODE=no
-# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
-if test "${enable_maintainer_mode+set}" = set; then
-  enableval="$enable_maintainer_mode"
-  case "${enableval}" in
-  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
-  no)	MAINT="#" ;;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
-echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; MAINT="#" ;;
-esac
-if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
-  echo "Setting maintainer mode" 6>&1
-fi
-else
-  MAINT="#"
-fi;
-
-
-# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
-if test "${enable_sim_bswap+set}" = set; then
-  enableval="$enable_sim_bswap"
-  case "${enableval}" in
-  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
-  no)	sim_bswap="-DWITH_BSWAP=0";;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
-echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_bswap="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
-  echo "Setting bswap flags = $sim_bswap" 6>&1
-fi
-else
-  sim_bswap=""
-fi;
-
-
-# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
-if test "${enable_sim_cflags+set}" = set; then
-  enableval="$enable_sim_cflags"
-  case "${enableval}" in
-  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
-  trace) { { echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
-echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_cflags="";;
-  no)	 sim_cflags="";;
-  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
-  echo "Setting sim cflags = $sim_cflags" 6>&1
-fi
-else
-  sim_cflags=""
-fi;
-
-
-# Check whether --enable-sim-debug or --disable-sim-debug was given.
-if test "${enable_sim_debug+set}" = set; then
-  enableval="$enable_sim_debug"
-  case "${enableval}" in
-  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
-  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
-  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
-  echo "Setting sim debug = $sim_debug" 6>&1
-fi
-else
-  sim_debug=""
-fi;
-
-
-# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
-if test "${enable_sim_stdio+set}" = set; then
-  enableval="$enable_sim_stdio"
-  case "${enableval}" in
-  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
-  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
-  *)	{ { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_stdio="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
-  echo "Setting stdio flags = $sim_stdio" 6>&1
-fi
-else
-  sim_stdio=""
-fi;
-
-
-# Check whether --enable-sim-trace or --disable-sim-trace was given.
-if test "${enable_sim_trace+set}" = set; then
-  enableval="$enable_sim_trace"
-  case "${enableval}" in
-  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
-  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
-  [-0-9]*)
-	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
-  [a-z]*)
-	sim_trace=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_trace" = x; then
-	    sim_trace="-DWITH_TRACE='(TRACE_$x"
-	  else
-	    sim_trace="${sim_trace}|TRACE_$x"
-	  fi
-	done
-	sim_trace="$sim_trace)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
-  echo "Setting sim trace = $sim_trace" 6>&1
-fi
-else
-  sim_trace=""
-fi;
-
-
-# Check whether --enable-sim-profile or --disable-sim-profile was given.
-if test "${enable_sim_profile+set}" = set; then
-  enableval="$enable_sim_profile"
-  case "${enableval}" in
-  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
-  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
-  [-0-9]*)
-	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
-  [a-z]*)
-	sim_profile=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_profile" = x; then
-	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
-	  else
-	    sim_profile="${sim_profile}|PROFILE_$x"
-	  fi
-	done
-	sim_profile="$sim_profile)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
-  echo "Setting sim profile = $sim_profile" 6>&1
-fi
-else
-  sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
-fi;
-
-
-echo "$as_me:$LINENO: checking return type of signal handlers" >&5
-echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6
-if test "${ac_cv_type_signal+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <signal.h>
-#ifdef signal
-# undef signal
-#endif
-#ifdef __cplusplus
-extern "C" void (*signal (int, void (*)(int)))(int);
-#else
-void (*signal ()) ();
-#endif
-
-int
-main ()
-{
-int i;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_signal=void
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_signal=int
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
-echo "${ECHO_T}$ac_cv_type_signal" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define RETSIGTYPE $ac_cv_type_signal
-_ACEOF
-
-
-
-
-
-sim_link_files=
-sim_link_links=
-
-sim_link_links=tconfig.h
-if test -f ${srcdir}/tconfig.in
-then
-  sim_link_files=tconfig.in
-else
-  sim_link_files=../common/tconfig.in
-fi
-
-# targ-vals.def points to the libc macro description file.
-case "${target}" in
-*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
-esac
-sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
-sim_link_links="${sim_link_links} targ-vals.def"
-
-
-
-wire_endian="BIG_ENDIAN"
-default_endian=""
-# Check whether --enable-sim-endian or --disable-sim-endian was given.
-if test "${enable_sim_endian+set}" = set; then
-  enableval="$enable_sim_endian"
-  case "${enableval}" in
-  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
-  yes)	 if test x"$wire_endian" != x; then
-	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-	 else
-           if test x"$default_endian" != x; then
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
-	   else
-	     echo "No hard-wired endian for target $target" 1>&6
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  no)	 if test x"$default_endian" != x; then
-	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-	 else
-	   if test x"$wire_endian" != x; then
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
-	   else
-	     echo "No default endian for target $target" 1>&6
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-endian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-endian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_endian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
-  echo "Setting endian flags = $sim_endian" 6>&1
-fi
-else
-  if test x"$default_endian" != x; then
-  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-else
-  if test x"$wire_endian" != x; then
-    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-  else
-    sim_endian=
-  fi
-fi
-fi;
-wire_alignment="STRICT_ALIGNMENT"
-default_alignment=""
-
-# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
-if test "${enable_sim_alignment+set}" = set; then
-  enableval="$enable_sim_alignment"
-  case "${enableval}" in
-  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
-  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
-  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
-  yes) if test x"$wire_alignment" != x; then
-	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-       else
-         if test x"$default_alignment" != x; then
-           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
-         else
-	   echo "No hard-wired alignment for target $target" 1>&6
-	   sim_alignment="-DWITH_ALIGNMENT=0"
-         fi
-       fi;;
-  no)  if test x"$default_alignment" != x; then
-	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-       else
-         if test x"$wire_alignment" != x; then
-	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
-         else
-           echo "No default alignment for target $target" 1>&6
-           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
-         fi
-       fi;;
-  *)   { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_alignment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
-  echo "Setting alignment flags = $sim_alignment" 6>&1
-fi
-else
-  if test x"$default_alignment" != x; then
-  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-else
-  if test x"$wire_alignment" != x; then
-    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-  else
-    sim_alignment=
-  fi
-fi
-fi;
-
-# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
-if test "${enable_sim_hostendian+set}" = set; then
-  enableval="$enable_sim_hostendian"
-  case "${enableval}" in
-  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
-  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_hostendian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
-  echo "Setting hostendian flags = $sim_hostendian" 6>&1
-fi
-else
-
-if test "x$cross_compiling" = "xno"; then
-  echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
-echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
-if test "${ac_cv_c_bigendian+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  # See if sys/param.h defines the BYTE_ORDER macro.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
- bogus endian macros
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  # It does; now see whether it defined to BIG_ENDIAN or not.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if BYTE_ORDER != BIG_ENDIAN
- not big endian
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_bigendian=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-# It does not; compile a test program.
-if test "$cross_compiling" = yes; then
-  # try to guess the endianness by grepping values into an object file
-  ac_cv_c_bigendian=unknown
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
-short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
-void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
-short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
-short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
-void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
-int
-main ()
-{
- _ascii (); _ebcdic ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
-  ac_cv_c_bigendian=yes
-fi
-if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
-  if test "$ac_cv_c_bigendian" = unknown; then
-    ac_cv_c_bigendian=no
-  else
-    # finding both strings is unlikely to happen, but who knows?
-    ac_cv_c_bigendian=unknown
-  fi
-fi
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-main ()
-{
-  /* Are we little or big endian?  From Harbison&Steele.  */
-  union
-  {
-    long l;
-    char c[sizeof (long)];
-  } u;
-  u.l = 1;
-  exit (u.c[sizeof (long) - 1] == 1);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=no
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_bigendian=yes
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
-echo "${ECHO_T}$ac_cv_c_bigendian" >&6
-case $ac_cv_c_bigendian in
-  yes)
-
-cat >>confdefs.h <<\_ACEOF
-#define WORDS_BIGENDIAN 1
-_ACEOF
- ;;
-  no)
-     ;;
-  *)
-    { { echo "$as_me:$LINENO: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&5
-echo "$as_me: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-
-  if test $ac_cv_c_bigendian = yes; then
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
-  else
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
-  fi
-else
-  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
-fi
-fi;
-
-default_sim_scache="16384"
-# Check whether --enable-sim-scache or --disable-sim-scache was given.
-if test "${enable_sim_scache+set}" = set; then
-  enableval="$enable_sim_scache"
-  case "${enableval}" in
-  yes)	sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
-  no)	sim_scache="-DWITH_SCACHE=0" ;;
-  [0-9]*) sim_scache="-DWITH_SCACHE=${enableval}";;
-  *)	{ { echo "$as_me:$LINENO: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&5
-echo "$as_me: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&2;}
-   { (exit 1); exit 1; }; };
-	sim_scache="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
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-cat >>$CONFIG_STATUS <<\_ACEOF
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-    ac_cs_recheck=: ;;
-  --version | --vers* | -V )
-    echo "$ac_cs_version"; exit 0 ;;
-  --he | --h)
-    # Conflict between --help and --header
-    { { echo "$as_me:$LINENO: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; };;
-  --help | --hel | -h )
-    echo "$ac_cs_usage"; exit 0 ;;
-  --debug | --d* | -d )
-    debug=: ;;
-  --file | --fil | --fi | --f )
-    $ac_shift
-    CONFIG_FILES="$CONFIG_FILES $ac_optarg"
-    ac_need_defaults=false;;
-  --header | --heade | --head | --hea )
-    $ac_shift
-    CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
-    ac_need_defaults=false;;
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-  | -silent | --silent | --silen | --sile | --sil | --si | --s)
-    ac_cs_silent=: ;;
-
-  # This is an error.
-  -*) { { echo "$as_me:$LINENO: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; } ;;
-
-  *) ac_config_targets="$ac_config_targets $1" ;;
-
-  esac
-  shift
-done
-
-ac_configure_extra_args=
-
-if $ac_cs_silent; then
-  exec 6>/dev/null
-  ac_configure_extra_args="$ac_configure_extra_args --silent"
-fi
-
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-if \$ac_cs_recheck; then
-  echo "running $SHELL $0 " $ac_configure_args \$ac_configure_extra_args " --no-create --no-recursion" >&6
-  exec $SHELL $0 $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
-fi
-
-_ACEOF
-
-
-
-
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_config_target in $ac_config_targets
-do
-  case "$ac_config_target" in
-  # Handling of arguments.
-  "Makefile.sim" ) CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
-  "Make-common.sim" ) CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
-  ".gdbinit" ) CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
-  "$ac_config_links_1" ) CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
-  "Makefile" ) CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
-  "stamp-h" ) CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
-  "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
-  *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
-echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# If the user did not use the arguments to specify the items to instantiate,
-# then the envvar interface is used.  Set only those that are not.
-# We use the long form for the default assignment because of an extremely
-# bizarre bug on SunOS 4.1.3.
-if $ac_need_defaults; then
-  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
-  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
-  test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
-  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
-fi
-
-# Have a temporary directory for convenience.  Make it in the build tree
-# simply because there is no reason to put it here, and in addition,
-# creating and moving files from /tmp can sometimes cause problems.
-# Create a temporary directory, and hook for its removal unless debugging.
-$debug ||
-{
-  trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
-  trap '{ (exit 1); exit 1; }' 1 2 13 15
-}
-
-# Create a (secure) tmp directory for tmp files.
-
-{
-  tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
-  test -n "$tmp" && test -d "$tmp"
-}  ||
-{
-  tmp=./confstat$$-$RANDOM
-  (umask 077 && mkdir $tmp)
-} ||
-{
-   echo "$me: cannot create a temporary directory in ." >&2
-   { (exit 1); exit 1; }
-}
-
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-
-#
-# CONFIG_FILES section.
-#
-
-# No need to generate the scripts if there are no CONFIG_FILES.
-# This happens for instance when ./config.status config.h
-if test -n "\$CONFIG_FILES"; then
-  # Protect against being on the right side of a sed subst in config.status.
-  sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g;
-   s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF
-s,@SHELL@,$SHELL,;t t
-s,@PATH_SEPARATOR@,$PATH_SEPARATOR,;t t
-s,@PACKAGE_NAME@,$PACKAGE_NAME,;t t
-s,@PACKAGE_TARNAME@,$PACKAGE_TARNAME,;t t
-s,@PACKAGE_VERSION@,$PACKAGE_VERSION,;t t
-s,@PACKAGE_STRING@,$PACKAGE_STRING,;t t
-s,@PACKAGE_BUGREPORT@,$PACKAGE_BUGREPORT,;t t
-s,@exec_prefix@,$exec_prefix,;t t
-s,@prefix@,$prefix,;t t
-s,@program_transform_name@,$program_transform_name,;t t
-s,@bindir@,$bindir,;t t
-s,@sbindir@,$sbindir,;t t
-s,@libexecdir@,$libexecdir,;t t
-s,@datadir@,$datadir,;t t
-s,@sysconfdir@,$sysconfdir,;t t
-s,@sharedstatedir@,$sharedstatedir,;t t
-s,@localstatedir@,$localstatedir,;t t
-s,@libdir@,$libdir,;t t
-s,@includedir@,$includedir,;t t
-s,@oldincludedir@,$oldincludedir,;t t
-s,@infodir@,$infodir,;t t
-s,@mandir@,$mandir,;t t
-s,@build_alias@,$build_alias,;t t
-s,@host_alias@,$host_alias,;t t
-s,@target_alias@,$target_alias,;t t
-s,@DEFS@,$DEFS,;t t
-s,@ECHO_C@,$ECHO_C,;t t
-s,@ECHO_N@,$ECHO_N,;t t
-s,@ECHO_T@,$ECHO_T,;t t
-s,@LIBS@,$LIBS,;t t
-s,@sim_environment@,$sim_environment,;t t
-s,@sim_alignment@,$sim_alignment,;t t
-s,@sim_assert@,$sim_assert,;t t
-s,@sim_bitsize@,$sim_bitsize,;t t
-s,@sim_endian@,$sim_endian,;t t
-s,@sim_hostendian@,$sim_hostendian,;t t
-s,@sim_float@,$sim_float,;t t
-s,@sim_scache@,$sim_scache,;t t
-s,@sim_default_model@,$sim_default_model,;t t
-s,@sim_hw_cflags@,$sim_hw_cflags,;t t
-s,@sim_hw_objs@,$sim_hw_objs,;t t
-s,@sim_hw@,$sim_hw,;t t
-s,@sim_inline@,$sim_inline,;t t
-s,@sim_packages@,$sim_packages,;t t
-s,@sim_regparm@,$sim_regparm,;t t
-s,@sim_reserved_bits@,$sim_reserved_bits,;t t
-s,@sim_smp@,$sim_smp,;t t
-s,@sim_stdcall@,$sim_stdcall,;t t
-s,@sim_xor_endian@,$sim_xor_endian,;t t
-s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
-s,@WERROR_CFLAGS@,$WERROR_CFLAGS,;t t
-s,@build@,$build,;t t
-s,@build_cpu@,$build_cpu,;t t
-s,@build_vendor@,$build_vendor,;t t
-s,@build_os@,$build_os,;t t
-s,@host@,$host,;t t
-s,@host_cpu@,$host_cpu,;t t
-s,@host_vendor@,$host_vendor,;t t
-s,@host_os@,$host_os,;t t
-s,@target@,$target,;t t
-s,@target_cpu@,$target_cpu,;t t
-s,@target_vendor@,$target_vendor,;t t
-s,@target_os@,$target_os,;t t
-s,@CC@,$CC,;t t
-s,@CFLAGS@,$CFLAGS,;t t
-s,@LDFLAGS@,$LDFLAGS,;t t
-s,@CPPFLAGS@,$CPPFLAGS,;t t
-s,@ac_ct_CC@,$ac_ct_CC,;t t
-s,@EXEEXT@,$EXEEXT,;t t
-s,@OBJEXT@,$OBJEXT,;t t
-s,@INSTALL_PROGRAM@,$INSTALL_PROGRAM,;t t
-s,@INSTALL_SCRIPT@,$INSTALL_SCRIPT,;t t
-s,@INSTALL_DATA@,$INSTALL_DATA,;t t
-s,@CC_FOR_BUILD@,$CC_FOR_BUILD,;t t
-s,@HDEFINES@,$HDEFINES,;t t
-s,@AR@,$AR,;t t
-s,@RANLIB@,$RANLIB,;t t
-s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
-s,@USE_NLS@,$USE_NLS,;t t
-s,@LIBINTL@,$LIBINTL,;t t
-s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t
-s,@INCINTL@,$INCINTL,;t t
-s,@XGETTEXT@,$XGETTEXT,;t t
-s,@GMSGFMT@,$GMSGFMT,;t t
-s,@POSUB@,$POSUB,;t t
-s,@CATALOGS@,$CATALOGS,;t t
-s,@DATADIRNAME@,$DATADIRNAME,;t t
-s,@INSTOBJEXT@,$INSTOBJEXT,;t t
-s,@GENCAT@,$GENCAT,;t t
-s,@CATOBJEXT@,$CATOBJEXT,;t t
-s,@CPP@,$CPP,;t t
-s,@EGREP@,$EGREP,;t t
-s,@MAINT@,$MAINT,;t t
-s,@sim_bswap@,$sim_bswap,;t t
-s,@sim_cflags@,$sim_cflags,;t t
-s,@sim_debug@,$sim_debug,;t t
-s,@sim_stdio@,$sim_stdio,;t t
-s,@sim_trace@,$sim_trace,;t t
-s,@sim_profile@,$sim_profile,;t t
-s,@CGEN_MAINT@,$CGEN_MAINT,;t t
-s,@cgendir@,$cgendir,;t t
-s,@cgen@,$cgen,;t t
-s,@traps_obj@,$traps_obj,;t t
-s,@sim_extra_cflags@,$sim_extra_cflags,;t t
-s,@cgen_breaks@,$cgen_breaks,;t t
-s,@LIBOBJS@,$LIBOBJS,;t t
-s,@LTLIBOBJS@,$LTLIBOBJS,;t t
-CEOF
-
-_ACEOF
-
-  cat >>$CONFIG_STATUS <<\_ACEOF
-  # Split the substitutions into bite-sized pieces for seds with
-  # small command number limits, like on Digital OSF/1 and HP-UX.
-  ac_max_sed_lines=48
-  ac_sed_frag=1 # Number of current file.
-  ac_beg=1 # First line for current file.
-  ac_end=$ac_max_sed_lines # Line after last line for current file.
-  ac_more_lines=:
-  ac_sed_cmds=
-  while $ac_more_lines; do
-    if test $ac_beg -gt 1; then
-      sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    else
-      sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    fi
-    if test ! -s $tmp/subs.frag; then
-      ac_more_lines=false
-    else
-      # The purpose of the label and of the branching condition is to
-      # speed up the sed processing (if there are no `@' at all, there
-      # is no need to browse any of the substitutions).
-      # These are the two extra sed commands mentioned above.
-      (echo ':t
-  /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
-      if test -z "$ac_sed_cmds"; then
-	ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
-      else
-	ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
-      fi
-      ac_sed_frag=`expr $ac_sed_frag + 1`
-      ac_beg=$ac_end
-      ac_end=`expr $ac_end + $ac_max_sed_lines`
-    fi
-  done
-  if test -z "$ac_sed_cmds"; then
-    ac_sed_cmds=cat
-  fi
-fi # test -n "$CONFIG_FILES"
-
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
-  ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_file" : 'X\(//\)[^/]' \| \
-	 X"$ac_file" : 'X\(//\)$' \| \
-	 X"$ac_file" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $INSTALL in
-  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
-  *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
-  esac
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    configure_input=
-  else
-    configure_input="$ac_file.  "
-  fi
-  configure_input=$configure_input"Generated from `echo $ac_file_in |
-				     sed 's,.*/,,'` by configure."
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 echo "$f";;
-      *) # Relative
-	 if test -f "$f"; then
-	   # Build tree
-	   echo "$f"
-	 elif test -f "$srcdir/$f"; then
-	   # Source tree
-	   echo "$srcdir/$f"
-	 else
-	   # /dev/null tree
-	   { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-  sed "$ac_vpsub
-$extrasub
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-:t
-/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
-s,@configure_input@,$configure_input,;t t
-s,@srcdir@,$ac_srcdir,;t t
-s,@abs_srcdir@,$ac_abs_srcdir,;t t
-s,@top_srcdir@,$ac_top_srcdir,;t t
-s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
-s,@builddir@,$ac_builddir,;t t
-s,@abs_builddir@,$ac_abs_builddir,;t t
-s,@top_builddir@,$ac_top_builddir,;t t
-s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
-s,@INSTALL@,$ac_INSTALL,;t t
-" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
-  rm -f $tmp/stdin
-  if test x"$ac_file" != x-; then
-    mv $tmp/out $ac_file
-  else
-    cat $tmp/out
-    rm -f $tmp/out
-  fi
-
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_HEADER section.
-#
-
-# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
-# NAME is the cpp macro being defined and VALUE is the value it is being given.
-#
-# ac_d sets the value in "#define NAME VALUE" lines.
-ac_dA='s,^\([	 ]*\)#\([	 ]*define[	 ][	 ]*\)'
-ac_dB='[	 ].*$,\1#\2'
-ac_dC=' '
-ac_dD=',;t'
-# ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
-ac_uA='s,^\([	 ]*\)#\([	 ]*\)undef\([	 ][	 ]*\)'
-ac_uB='$,\1#\2define\3'
-ac_uC=' '
-ac_uD=',;t'
-
-for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  test x"$ac_file" != x- && { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
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-	   # /dev/null tree
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-echo "$as_me: error: cannot find input file: $f" >&2;}
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-
-# Transform confdefs.h into two sed scripts, `conftest.defines' and
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-s/[\\&,]/\\&/g
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-	 X"$as_dir" : 'X\(/\)' \| \
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-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
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-
-      rm -f $ac_file
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-#
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-	 X"$ac_dest" : 'X\(/\)' \| \
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-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
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-    mkdir -p "$ac_dest_dir"
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-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
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-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
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-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
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-# Do not use `cd foo && pwd` to compute absolute paths, because
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-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
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-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $srcdir in
-  [\\/$]* | ?:[\\/]* ) ac_rel_source=$srcdir/$ac_source ;;
-      *) ac_rel_source=$ac_top_builddir$srcdir/$ac_source ;;
-  esac
-
-  # Try a symlink, then a hard link, then a copy.
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-    cp -p $srcdir/$ac_source $ac_dest ||
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-echo "$as_me: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&2;}
-   { (exit 1); exit 1; }; }
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_COMMANDS section.
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-	 X"$ac_dest" : 'X\(//\)$' \| \
-	 X"$ac_dest" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
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-  ac_dir_suffix= ac_top_builddir=
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-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
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-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
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-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
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-
-# Do not use `cd foo && pwd` to compute absolute paths, because
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-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
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-esac
-
-
-  { echo "$as_me:$LINENO: executing $ac_dest commands" >&5
-echo "$as_me: executing $ac_dest commands" >&6;}
-  case $ac_dest in
-    Makefile ) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
- rm -f Makesim1.tmp Makesim2.tmp Makefile
- sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
- sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
- sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
-	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
-	<Makefile.sim >Makefile
- rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
- ;;
-    stamp-h ) echo > stamp-h ;;
-  esac
-done
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-{ (exit 0); exit 0; }
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-chmod +x $CONFIG_STATUS
-ac_clean_files=$ac_clean_files_save
-
-
-# configure is writing to config.log, and then calls config.status.
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-# by configure, so config.status won't be able to write to it; its
-# output is simply discarded.  So we exec the FD to /dev/null,
-# effectively closing config.log, so it can be properly (re)opened and
-# appended to by config.status.  When coming back to configure, we
-# need to make the FD available again.
-if test "$no_create" != yes; then
-  ac_cs_success=:
-  ac_config_status_args=
-  test "$silent" = yes &&
-    ac_config_status_args="$ac_config_status_args --quiet"
-  exec 5>/dev/null
-  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
-  exec 5>>config.log
-  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
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-  $ac_cs_success || { (exit 1); exit 1; }
-fi
-
-
diff --git a/sim/m32r/configure.ac b/sim/m32r/configure.ac
deleted file mode 100644
index 1a4307d..0000000
--- a/sim/m32r/configure.ac
+++ /dev/null
@@ -1,35 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-AC_PREREQ(2.59)dnl
-AC_INIT(Makefile.in)
-AC_CONFIG_HEADER(config.h:config.in)
-
-sinclude(../common/aclocal.m4)
-
-# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
-# it by inlining the macro's contents.
-sinclude(../common/common.m4)
-
-SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
-SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
-SIM_AC_OPTION_HOSTENDIAN
-SIM_AC_OPTION_SCACHE(16384)
-SIM_AC_OPTION_DEFAULT_MODEL(m32r/d)
-SIM_AC_OPTION_ENVIRONMENT
-SIM_AC_OPTION_INLINE()
-SIM_AC_OPTION_CGEN_MAINT
-
-  case "${target_alias}" in
-  m32r*-linux*)
-    traps_obj=traps-linux.o
-    sim_extra_cflags="-DM32R_LINUX"
-    ;;
-  *)
-    traps_obj=traps.o
-    sim_extra_cflags="-DM32R_ELF"
-    ;;
-  esac
-AC_SUBST(traps_obj)
-AC_SUBST(sim_extra_cflags)
-
-
-SIM_AC_OUTPUT
diff --git a/sim/m32r/cpu.c b/sim/m32r/cpu.c
deleted file mode 100644
index 197ea43..0000000
--- a/sim/m32r/cpu.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* Misc. support for CPU family m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "cgen-ops.h"
-
-/* Get the value of h-pc.  */
-
-USI
-m32rbf_h_pc_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_pc);
-}
-
-/* Set a value for h-pc.  */
-
-void
-m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  CPU (h_pc) = newval;
-}
-
-/* Get the value of h-gr.  */
-
-SI
-m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_gr[regno]);
-}
-
-/* Set a value for h-gr.  */
-
-void
-m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  CPU (h_gr[regno]) = newval;
-}
-
-/* Get the value of h-cr.  */
-
-USI
-m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-accum.  */
-
-DI
-m32rbf_h_accum_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ACCUM ();
-}
-
-/* Set a value for h-accum.  */
-
-void
-m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  SET_H_ACCUM (newval);
-}
-
-/* Get the value of h-cond.  */
-
-BI
-m32rbf_h_cond_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_cond);
-}
-
-/* Set a value for h-cond.  */
-
-void
-m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_cond) = newval;
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-m32rbf_h_psw_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PSW ();
-}
-
-/* Set a value for h-psw.  */
-
-void
-m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  SET_H_PSW (newval);
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bpsw);
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bpsw) = newval;
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bbpsw);
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bbpsw) = newval;
-}
-
-/* Get the value of h-lock.  */
-
-BI
-m32rbf_h_lock_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_lock);
-}
-
-/* Set a value for h-lock.  */
-
-void
-m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_lock) = newval;
-}
-
-/* Record trace results for INSN.  */
-
-void
-m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
deleted file mode 100644
index a5ecbe3..0000000
--- a/sim/m32r/cpu.h
+++ /dev/null
@@ -1,691 +0,0 @@
-/* CPU family header for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_M32RBF_H
-#define CPU_M32RBF_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 2
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 1
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* program counter */
-  USI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) (CPU (h_pc) = (x))
-  /* general registers */
-  SI h_gr[16];
-#define GET_H_GR(a1) CPU (h_gr)[a1]
-#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
-  /* control registers */
-  USI h_cr[16];
-#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
-#define SET_H_CR(index, x) \
-do { \
-m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
-;} while (0)
-  /* accumulator */
-  DI h_accum;
-#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
-#define SET_H_ACCUM(x) \
-do { \
-m32rbf_h_accum_set_handler (current_cpu, (x));\
-;} while (0)
-  /* condition bit */
-  BI h_cond;
-#define GET_H_COND() CPU (h_cond)
-#define SET_H_COND(x) (CPU (h_cond) = (x))
-  /* psw part of psw */
-  UQI h_psw;
-#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
-#define SET_H_PSW(x) \
-do { \
-m32rbf_h_psw_set_handler (current_cpu, (x));\
-;} while (0)
-  /* backup psw */
-  UQI h_bpsw;
-#define GET_H_BPSW() CPU (h_bpsw)
-#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
-  /* backup bpsw */
-  UQI h_bbpsw;
-#define GET_H_BBPSW() CPU (h_bbpsw)
-#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
-  /* lock */
-  BI h_lock;
-#define GET_H_LOCK() CPU (h_lock)
-#define SET_H_LOCK(x) (CPU (h_lock) = (x))
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} M32RBF_CPU_DATA;
-
-/* Cover fns for register access.  */
-USI m32rbf_h_pc_get (SIM_CPU *);
-void m32rbf_h_pc_set (SIM_CPU *, USI);
-SI m32rbf_h_gr_get (SIM_CPU *, UINT);
-void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32rbf_h_cr_get (SIM_CPU *, UINT);
-void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32rbf_h_accum_get (SIM_CPU *);
-void m32rbf_h_accum_set (SIM_CPU *, DI);
-BI m32rbf_h_cond_get (SIM_CPU *);
-void m32rbf_h_cond_set (SIM_CPU *, BI);
-UQI m32rbf_h_psw_get (SIM_CPU *);
-void m32rbf_h_psw_set (SIM_CPU *, UQI);
-UQI m32rbf_h_bpsw_get (SIM_CPU *);
-void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
-UQI m32rbf_h_bbpsw_get (SIM_CPU *);
-void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
-BI m32rbf_h_lock_get (SIM_CPU *);
-void m32rbf_h_lock_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN m32rbf_fetch_register;
-extern CPUREG_STORE_FN m32rbf_store_register;
-
-typedef struct {
-  UINT h_gr;
-} MODEL_M32R_D_DATA;
-
-typedef struct {
-  int empty;
-} MODEL_TEST_DATA;
-
-/* Instruction argument buffer.  */
-
-union sem_fields {
-  struct { /* no operands */
-    int empty;
-  } fmt_empty;
-  struct { /*  */
-    UINT f_uimm8;
-  } sfmt_clrpsw;
-  struct { /*  */
-    UINT f_uimm4;
-  } sfmt_trap;
-  struct { /*  */
-    IADDR i_disp24;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl24;
-  struct { /*  */
-    IADDR i_disp8;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl8;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_hi16;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_seth;
-  struct { /*  */
-    ADDR i_uimm24;
-    SI* i_dr;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_ld24;
-  struct { /*  */
-    SI* i_sr;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_jl;
-  struct { /*  */
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r2;
-    UINT f_uimm3;
-    unsigned char in_sr;
-  } sfmt_bset;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_r1;
-    UINT f_uimm5;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_slli;
-  struct { /*  */
-    SI* i_dr;
-    INT f_simm8;
-    UINT f_r1;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_addi;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-    unsigned char out_src2;
-  } sfmt_st_plus;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_st_d;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-    unsigned char out_sr;
-  } sfmt_ld_plus;
-  struct { /*  */
-    IADDR i_disp16;
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_beq;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_and3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_dr;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-    SCACHE *branch_target;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_ADD3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_AND3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_OR3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_OR3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  INT f_simm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_ADDV3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDV3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BC8_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC8_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-
-#define EXTRACT_IFMT_BC24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp24; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQZ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQZ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_CMP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CMPI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPI_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_DIV_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_DIV_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_JL_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_JL_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_LD24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm24; \
-  unsigned int length;
-#define EXTRACT_IFMT_LD24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
-
-#define EXTRACT_IFMT_LDI16_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDI16_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_MVFACHI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVFC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTACHI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_NOP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_NOP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_SETH_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_hi16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SETH_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_SLLI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_shift_op2; \
-  UINT f_uimm5; \
-  unsigned int length;
-#define EXTRACT_IFMT_SLLI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
-
-#define EXTRACT_IFMT_ST_D_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ST_D_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_TRAP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_uimm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CLRPSW_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_CLRPSW_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_BSET_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BSET_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BTST_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_BTST_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_M32RBF_H */
diff --git a/sim/m32r/cpu2.c b/sim/m32r/cpu2.c
deleted file mode 100644
index 1749880..0000000
--- a/sim/m32r/cpu2.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Misc. support for CPU family m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32r2f
-#define WANT_CPU_M32R2F
-
-#include "sim-main.h"
-#include "cgen-ops.h"
-
-/* Get the value of h-pc.  */
-
-USI
-m32r2f_h_pc_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_pc);
-}
-
-/* Set a value for h-pc.  */
-
-void
-m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  CPU (h_pc) = newval;
-}
-
-/* Get the value of h-gr.  */
-
-SI
-m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_gr[regno]);
-}
-
-/* Set a value for h-gr.  */
-
-void
-m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  CPU (h_gr[regno]) = newval;
-}
-
-/* Get the value of h-cr.  */
-
-USI
-m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-accum.  */
-
-DI
-m32r2f_h_accum_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ACCUM ();
-}
-
-/* Set a value for h-accum.  */
-
-void
-m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  SET_H_ACCUM (newval);
-}
-
-/* Get the value of h-accums.  */
-
-DI
-m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_ACCUMS (regno);
-}
-
-/* Set a value for h-accums.  */
-
-void
-m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_ACCUMS (regno, newval);
-}
-
-/* Get the value of h-cond.  */
-
-BI
-m32r2f_h_cond_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_cond);
-}
-
-/* Set a value for h-cond.  */
-
-void
-m32r2f_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_cond) = newval;
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-m32r2f_h_psw_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PSW ();
-}
-
-/* Set a value for h-psw.  */
-
-void
-m32r2f_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  SET_H_PSW (newval);
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-m32r2f_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bpsw);
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-m32r2f_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bpsw) = newval;
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-m32r2f_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bbpsw);
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-m32r2f_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bbpsw) = newval;
-}
-
-/* Get the value of h-lock.  */
-
-BI
-m32r2f_h_lock_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_lock);
-}
-
-/* Set a value for h-lock.  */
-
-void
-m32r2f_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_lock) = newval;
-}
-
-/* Record trace results for INSN.  */
-
-void
-m32r2f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/m32r/cpu2.h b/sim/m32r/cpu2.h
deleted file mode 100644
index 8ae49e4..0000000
--- a/sim/m32r/cpu2.h
+++ /dev/null
@@ -1,1046 +0,0 @@
-/* CPU family header for m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_M32R2F_H
-#define CPU_M32R2F_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 2
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 2
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* program counter */
-  USI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) (CPU (h_pc) = (x))
-  /* general registers */
-  SI h_gr[16];
-#define GET_H_GR(a1) CPU (h_gr)[a1]
-#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
-  /* control registers */
-  USI h_cr[16];
-#define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)
-#define SET_H_CR(index, x) \
-do { \
-m32r2f_h_cr_set_handler (current_cpu, (index), (x));\
-;} while (0)
-  /* accumulator */
-  DI h_accum;
-#define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)
-#define SET_H_ACCUM(x) \
-do { \
-m32r2f_h_accum_set_handler (current_cpu, (x));\
-;} while (0)
-  /* accumulators */
-  DI h_accums[2];
-#define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index)
-#define SET_H_ACCUMS(index, x) \
-do { \
-m32r2f_h_accums_set_handler (current_cpu, (index), (x));\
-;} while (0)
-  /* condition bit */
-  BI h_cond;
-#define GET_H_COND() CPU (h_cond)
-#define SET_H_COND(x) (CPU (h_cond) = (x))
-  /* psw part of psw */
-  UQI h_psw;
-#define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)
-#define SET_H_PSW(x) \
-do { \
-m32r2f_h_psw_set_handler (current_cpu, (x));\
-;} while (0)
-  /* backup psw */
-  UQI h_bpsw;
-#define GET_H_BPSW() CPU (h_bpsw)
-#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
-  /* backup bpsw */
-  UQI h_bbpsw;
-#define GET_H_BBPSW() CPU (h_bbpsw)
-#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
-  /* lock */
-  BI h_lock;
-#define GET_H_LOCK() CPU (h_lock)
-#define SET_H_LOCK(x) (CPU (h_lock) = (x))
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} M32R2F_CPU_DATA;
-
-/* Cover fns for register access.  */
-USI m32r2f_h_pc_get (SIM_CPU *);
-void m32r2f_h_pc_set (SIM_CPU *, USI);
-SI m32r2f_h_gr_get (SIM_CPU *, UINT);
-void m32r2f_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32r2f_h_cr_get (SIM_CPU *, UINT);
-void m32r2f_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32r2f_h_accum_get (SIM_CPU *);
-void m32r2f_h_accum_set (SIM_CPU *, DI);
-DI m32r2f_h_accums_get (SIM_CPU *, UINT);
-void m32r2f_h_accums_set (SIM_CPU *, UINT, DI);
-BI m32r2f_h_cond_get (SIM_CPU *);
-void m32r2f_h_cond_set (SIM_CPU *, BI);
-UQI m32r2f_h_psw_get (SIM_CPU *);
-void m32r2f_h_psw_set (SIM_CPU *, UQI);
-UQI m32r2f_h_bpsw_get (SIM_CPU *);
-void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
-UQI m32r2f_h_bbpsw_get (SIM_CPU *);
-void m32r2f_h_bbpsw_set (SIM_CPU *, UQI);
-BI m32r2f_h_lock_get (SIM_CPU *);
-void m32r2f_h_lock_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN m32r2f_fetch_register;
-extern CPUREG_STORE_FN m32r2f_store_register;
-
-typedef struct {
-  int empty;
-} MODEL_M32R2_DATA;
-
-/* Instruction argument buffer.  */
-
-union sem_fields {
-  struct { /* no operands */
-    int empty;
-  } fmt_empty;
-  struct { /*  */
-    UINT f_uimm8;
-  } sfmt_clrpsw;
-  struct { /*  */
-    UINT f_uimm4;
-  } sfmt_trap;
-  struct { /*  */
-    IADDR i_disp24;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl24;
-  struct { /*  */
-    IADDR i_disp8;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl8;
-  struct { /*  */
-    SI f_imm1;
-    UINT f_accd;
-    UINT f_accs;
-  } sfmt_rac_dsi;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_hi16;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_seth;
-  struct { /*  */
-    SI* i_src1;
-    UINT f_accs;
-    UINT f_r1;
-    unsigned char in_src1;
-  } sfmt_mvtachi_a;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_accs;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_mvfachi_a;
-  struct { /*  */
-    ADDR i_uimm24;
-    SI* i_dr;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_ld24;
-  struct { /*  */
-    SI* i_sr;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_jl;
-  struct { /*  */
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r2;
-    UINT f_uimm3;
-    unsigned char in_sr;
-  } sfmt_bset;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_r1;
-    UINT f_uimm5;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_slli;
-  struct { /*  */
-    SI* i_dr;
-    INT f_simm8;
-    UINT f_r1;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_addi;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-    unsigned char out_src2;
-  } sfmt_st_plus;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_st_d;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_acc;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_machi_a;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-    unsigned char out_sr;
-  } sfmt_ld_plus;
-  struct { /*  */
-    IADDR i_disp16;
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_beq;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_and3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_dr;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-    SCACHE *branch_target;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_ADD3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_AND3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_OR3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_OR3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  INT f_simm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_ADDV3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDV3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BC8_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC8_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-
-#define EXTRACT_IFMT_BC24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp24; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQZ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQZ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_CMP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CMPI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPI_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_CMPZ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPZ_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_DIV_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_DIV_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_JC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_JC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_LD24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm24; \
-  unsigned int length;
-#define EXTRACT_IFMT_LD24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
-
-#define EXTRACT_IFMT_LDI16_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDI16_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_MACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_acc; \
-  UINT f_op23; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVFACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVFC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVTC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_NOP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_NOP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_RAC_DSI_VARS \
-  UINT f_op1; \
-  UINT f_accd; \
-  UINT f_bits67; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_bit14; \
-  SI f_imm1; \
-  unsigned int length;
-#define EXTRACT_IFMT_RAC_DSI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
-  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
-  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
-
-#define EXTRACT_IFMT_SETH_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_hi16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SETH_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_SLLI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_shift_op2; \
-  UINT f_uimm5; \
-  unsigned int length;
-#define EXTRACT_IFMT_SLLI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
-
-#define EXTRACT_IFMT_ST_D_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ST_D_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_TRAP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_uimm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_SATB_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SATB_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_CLRPSW_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_CLRPSW_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_BSET_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BSET_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BTST_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_BTST_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-/* Queued output values of an instruction.  */
-
-struct parexec {
-  union {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } sfmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI dr;
-    } sfmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      SI dr;
-    } sfmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      SI dr;
-    } sfmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      SI dr;
-    } sfmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      SI dr;
-    } sfmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      BI condbit;
-      SI dr;
-    } sfmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      BI condbit;
-      SI dr;
-    } sfmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      BI condbit;
-      SI dr;
-    } sfmt_addx;
-    struct { /* e.g. bc.s $disp8 */
-      USI pc;
-    } sfmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      USI pc;
-    } sfmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      USI pc;
-    } sfmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      USI pc;
-    } sfmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bl24;
-    struct { /* e.g. bcl.s $disp8 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bcl8;
-    struct { /* e.g. bcl.l $disp24 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bcl24;
-    struct { /* e.g. bra.s $disp8 */
-      USI pc;
-    } sfmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      USI pc;
-    } sfmt_bra24;
-    struct { /* e.g. cmp $src1,$src2 */
-      BI condbit;
-    } sfmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      BI condbit;
-    } sfmt_cmpi;
-    struct { /* e.g. cmpz $src2 */
-      BI condbit;
-    } sfmt_cmpz;
-    struct { /* e.g. div $dr,$sr */
-      SI dr;
-    } sfmt_div;
-    struct { /* e.g. jc $sr */
-      USI pc;
-    } sfmt_jc;
-    struct { /* e.g. jl $sr */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_jl;
-    struct { /* e.g. jmp $sr */
-      USI pc;
-    } sfmt_jmp;
-    struct { /* e.g. ld $dr,@$sr */
-      SI dr;
-    } sfmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI dr;
-    } sfmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI dr;
-    } sfmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI dr;
-      SI sr;
-    } sfmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      SI dr;
-    } sfmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      SI dr;
-    } sfmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      SI dr;
-    } sfmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI dr;
-      BI h_lock_BI;
-    } sfmt_lock;
-    struct { /* e.g. machi $src1,$src2,$acc */
-      DI acc;
-    } sfmt_machi_a;
-    struct { /* e.g. mulhi $src1,$src2,$acc */
-      DI acc;
-    } sfmt_mulhi_a;
-    struct { /* e.g. mv $dr,$sr */
-      SI dr;
-    } sfmt_mv;
-    struct { /* e.g. mvfachi $dr,$accs */
-      SI dr;
-    } sfmt_mvfachi_a;
-    struct { /* e.g. mvfc $dr,$scr */
-      SI dr;
-    } sfmt_mvfc;
-    struct { /* e.g. mvtachi $src1,$accs */
-      DI accs;
-    } sfmt_mvtachi_a;
-    struct { /* e.g. mvtc $sr,$dcr */
-      USI dcr;
-    } sfmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } sfmt_nop;
-    struct { /* e.g. rac $accd,$accs,$imm1 */
-      DI accd;
-    } sfmt_rac_dsi;
-    struct { /* e.g. rte */
-      UQI h_bpsw_UQI;
-      USI h_cr_USI_6;
-      UQI h_psw_UQI;
-      USI pc;
-    } sfmt_rte;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      SI dr;
-    } sfmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      SI dr;
-    } sfmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      SI dr;
-    } sfmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI h_memory_SI_src2;
-      USI h_memory_SI_src2_idx;
-    } sfmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_SI_add__DFLT_src2_slo16;
-      USI h_memory_SI_add__DFLT_src2_slo16_idx;
-    } sfmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      QI h_memory_QI_src2;
-      USI h_memory_QI_src2_idx;
-    } sfmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_QI_add__DFLT_src2_slo16;
-      USI h_memory_QI_add__DFLT_src2_slo16_idx;
-    } sfmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      HI h_memory_HI_src2;
-      USI h_memory_HI_src2_idx;
-    } sfmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_HI_add__DFLT_src2_slo16;
-      USI h_memory_HI_add__DFLT_src2_slo16_idx;
-    } sfmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI h_memory_SI_new_src2;
-      USI h_memory_SI_new_src2_idx;
-      SI src2;
-    } sfmt_st_plus;
-    struct { /* e.g. sth $src1,@$src2+ */
-      HI h_memory_HI_new_src2;
-      USI h_memory_HI_new_src2_idx;
-      SI src2;
-    } sfmt_sth_plus;
-    struct { /* e.g. stb $src1,@$src2+ */
-      QI h_memory_QI_new_src2;
-      USI h_memory_QI_new_src2_idx;
-      SI src2;
-    } sfmt_stb_plus;
-    struct { /* e.g. trap $uimm4 */
-      UQI h_bbpsw_UQI;
-      UQI h_bpsw_UQI;
-      USI h_cr_USI_14;
-      USI h_cr_USI_6;
-      UQI h_psw_UQI;
-      SI pc;
-    } sfmt_trap;
-    struct { /* e.g. unlock $src1,@$src2 */
-      BI h_lock_BI;
-      SI h_memory_SI_src2;
-      USI h_memory_SI_src2_idx;
-    } sfmt_unlock;
-    struct { /* e.g. satb $dr,$sr */
-      SI dr;
-    } sfmt_satb;
-    struct { /* e.g. sat $dr,$sr */
-      SI dr;
-    } sfmt_sat;
-    struct { /* e.g. sadd */
-      DI h_accums_DI_0;
-    } sfmt_sadd;
-    struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums_DI_1;
-    } sfmt_macwu1;
-    struct { /* e.g. msblo $src1,$src2 */
-      DI accum;
-    } sfmt_msblo;
-    struct { /* e.g. mulwu1 $src1,$src2 */
-      DI h_accums_DI_1;
-    } sfmt_mulwu1;
-    struct { /* e.g. sc */
-      int empty;
-    } sfmt_sc;
-    struct { /* e.g. clrpsw $uimm8 */
-      USI h_cr_USI_0;
-    } sfmt_clrpsw;
-    struct { /* e.g. setpsw $uimm8 */
-      USI h_cr_USI_0;
-    } sfmt_setpsw;
-    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
-      QI h_memory_QI_add__DFLT_sr_slo16;
-      USI h_memory_QI_add__DFLT_sr_slo16_idx;
-    } sfmt_bset;
-    struct { /* e.g. btst $uimm3,$sr */
-      BI condbit;
-    } sfmt_btst;
-  } operands;
-  /* For conditionally written operands, bitmask of which ones were.  */
-  int written;
-};
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_M32R2F_H */
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
deleted file mode 100644
index 1985846..0000000
--- a/sim/m32r/cpuall.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Simulator CPU header for m32r.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32R_CPUALL_H
-#define M32R_CPUALL_H
-
-/* Include files for each cpu family.  */
-
-#ifdef WANT_CPU_M32RBF
-#include "eng.h"
-#include "cgen-engine.h"
-#include "cpu.h"
-#include "decode.h"
-#endif
-
-#ifdef WANT_CPU_M32RXF
-#include "engx.h"
-#include "cgen-engine.h"
-#include "cpux.h"
-#include "decodex.h"
-#endif
-
-#ifdef WANT_CPU_M32R2F
-#include "eng2.h"
-#include "cgen-engine.h"
-#include "cpu2.h"
-#include "decode2.h"
-#endif
-
-extern const MACH m32r_mach;
-extern const MACH m32rx_mach;
-extern const MACH m32r2_mach;
-
-#ifndef WANT_CPU
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-};
-#endif
-
-#ifndef WANT_CPU
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-#endif
-
-#endif /* M32R_CPUALL_H */
diff --git a/sim/m32r/cpux.c b/sim/m32r/cpux.c
deleted file mode 100644
index f460961..0000000
--- a/sim/m32r/cpux.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* Misc. support for CPU family m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-#include "cgen-ops.h"
-
-/* Get the value of h-pc.  */
-
-USI
-m32rxf_h_pc_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_pc);
-}
-
-/* Set a value for h-pc.  */
-
-void
-m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
-{
-  CPU (h_pc) = newval;
-}
-
-/* Get the value of h-gr.  */
-
-SI
-m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return CPU (h_gr[regno]);
-}
-
-/* Set a value for h-gr.  */
-
-void
-m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
-{
-  CPU (h_gr[regno]) = newval;
-}
-
-/* Get the value of h-cr.  */
-
-USI
-m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_CR (regno);
-}
-
-/* Set a value for h-cr.  */
-
-void
-m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
-{
-  SET_H_CR (regno, newval);
-}
-
-/* Get the value of h-accum.  */
-
-DI
-m32rxf_h_accum_get (SIM_CPU *current_cpu)
-{
-  return GET_H_ACCUM ();
-}
-
-/* Set a value for h-accum.  */
-
-void
-m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
-{
-  SET_H_ACCUM (newval);
-}
-
-/* Get the value of h-accums.  */
-
-DI
-m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
-{
-  return GET_H_ACCUMS (regno);
-}
-
-/* Set a value for h-accums.  */
-
-void
-m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  SET_H_ACCUMS (regno, newval);
-}
-
-/* Get the value of h-cond.  */
-
-BI
-m32rxf_h_cond_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_cond);
-}
-
-/* Set a value for h-cond.  */
-
-void
-m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_cond) = newval;
-}
-
-/* Get the value of h-psw.  */
-
-UQI
-m32rxf_h_psw_get (SIM_CPU *current_cpu)
-{
-  return GET_H_PSW ();
-}
-
-/* Set a value for h-psw.  */
-
-void
-m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  SET_H_PSW (newval);
-}
-
-/* Get the value of h-bpsw.  */
-
-UQI
-m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bpsw);
-}
-
-/* Set a value for h-bpsw.  */
-
-void
-m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bpsw) = newval;
-}
-
-/* Get the value of h-bbpsw.  */
-
-UQI
-m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_bbpsw);
-}
-
-/* Set a value for h-bbpsw.  */
-
-void
-m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_bbpsw) = newval;
-}
-
-/* Get the value of h-lock.  */
-
-BI
-m32rxf_h_lock_get (SIM_CPU *current_cpu)
-{
-  return CPU (h_lock);
-}
-
-/* Set a value for h-lock.  */
-
-void
-m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
-{
-  CPU (h_lock) = newval;
-}
-
-/* Record trace results for INSN.  */
-
-void
-m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
-			    int *indices, TRACE_RECORD *tr)
-{
-}
diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
deleted file mode 100644
index 1f0390c..0000000
--- a/sim/m32r/cpux.h
+++ /dev/null
@@ -1,1046 +0,0 @@
-/* CPU family header for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef CPU_M32RXF_H
-#define CPU_M32RXF_H
-
-/* Maximum number of instructions that are fetched at a time.
-   This is for LIW type instructions sets (e.g. m32r).  */
-#define MAX_LIW_INSNS 2
-
-/* Maximum number of instructions that can be executed in parallel.  */
-#define MAX_PARALLEL_INSNS 2
-
-/* CPU state information.  */
-typedef struct {
-  /* Hardware elements.  */
-  struct {
-  /* program counter */
-  USI h_pc;
-#define GET_H_PC() CPU (h_pc)
-#define SET_H_PC(x) (CPU (h_pc) = (x))
-  /* general registers */
-  SI h_gr[16];
-#define GET_H_GR(a1) CPU (h_gr)[a1]
-#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
-  /* control registers */
-  USI h_cr[16];
-#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
-#define SET_H_CR(index, x) \
-do { \
-m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
-;} while (0)
-  /* accumulator */
-  DI h_accum;
-#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
-#define SET_H_ACCUM(x) \
-do { \
-m32rxf_h_accum_set_handler (current_cpu, (x));\
-;} while (0)
-  /* accumulators */
-  DI h_accums[2];
-#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
-#define SET_H_ACCUMS(index, x) \
-do { \
-m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
-;} while (0)
-  /* condition bit */
-  BI h_cond;
-#define GET_H_COND() CPU (h_cond)
-#define SET_H_COND(x) (CPU (h_cond) = (x))
-  /* psw part of psw */
-  UQI h_psw;
-#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
-#define SET_H_PSW(x) \
-do { \
-m32rxf_h_psw_set_handler (current_cpu, (x));\
-;} while (0)
-  /* backup psw */
-  UQI h_bpsw;
-#define GET_H_BPSW() CPU (h_bpsw)
-#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
-  /* backup bpsw */
-  UQI h_bbpsw;
-#define GET_H_BBPSW() CPU (h_bbpsw)
-#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
-  /* lock */
-  BI h_lock;
-#define GET_H_LOCK() CPU (h_lock)
-#define SET_H_LOCK(x) (CPU (h_lock) = (x))
-  } hardware;
-#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
-} M32RXF_CPU_DATA;
-
-/* Cover fns for register access.  */
-USI m32rxf_h_pc_get (SIM_CPU *);
-void m32rxf_h_pc_set (SIM_CPU *, USI);
-SI m32rxf_h_gr_get (SIM_CPU *, UINT);
-void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
-USI m32rxf_h_cr_get (SIM_CPU *, UINT);
-void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
-DI m32rxf_h_accum_get (SIM_CPU *);
-void m32rxf_h_accum_set (SIM_CPU *, DI);
-DI m32rxf_h_accums_get (SIM_CPU *, UINT);
-void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
-BI m32rxf_h_cond_get (SIM_CPU *);
-void m32rxf_h_cond_set (SIM_CPU *, BI);
-UQI m32rxf_h_psw_get (SIM_CPU *);
-void m32rxf_h_psw_set (SIM_CPU *, UQI);
-UQI m32rxf_h_bpsw_get (SIM_CPU *);
-void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
-UQI m32rxf_h_bbpsw_get (SIM_CPU *);
-void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
-BI m32rxf_h_lock_get (SIM_CPU *);
-void m32rxf_h_lock_set (SIM_CPU *, BI);
-
-/* These must be hand-written.  */
-extern CPUREG_FETCH_FN m32rxf_fetch_register;
-extern CPUREG_STORE_FN m32rxf_store_register;
-
-typedef struct {
-  int empty;
-} MODEL_M32RX_DATA;
-
-/* Instruction argument buffer.  */
-
-union sem_fields {
-  struct { /* no operands */
-    int empty;
-  } fmt_empty;
-  struct { /*  */
-    UINT f_uimm8;
-  } sfmt_clrpsw;
-  struct { /*  */
-    UINT f_uimm4;
-  } sfmt_trap;
-  struct { /*  */
-    IADDR i_disp24;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl24;
-  struct { /*  */
-    IADDR i_disp8;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_bl8;
-  struct { /*  */
-    SI f_imm1;
-    UINT f_accd;
-    UINT f_accs;
-  } sfmt_rac_dsi;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_hi16;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_seth;
-  struct { /*  */
-    SI* i_src1;
-    UINT f_accs;
-    UINT f_r1;
-    unsigned char in_src1;
-  } sfmt_mvtachi_a;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_accs;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_mvfachi_a;
-  struct { /*  */
-    ADDR i_uimm24;
-    SI* i_dr;
-    UINT f_r1;
-    unsigned char out_dr;
-  } sfmt_ld24;
-  struct { /*  */
-    SI* i_sr;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_h_gr_SI_14;
-  } sfmt_jl;
-  struct { /*  */
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r2;
-    UINT f_uimm3;
-    unsigned char in_sr;
-  } sfmt_bset;
-  struct { /*  */
-    SI* i_dr;
-    UINT f_r1;
-    UINT f_uimm5;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_slli;
-  struct { /*  */
-    SI* i_dr;
-    INT f_simm8;
-    UINT f_r1;
-    unsigned char in_dr;
-    unsigned char out_dr;
-  } sfmt_addi;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-    unsigned char out_src2;
-  } sfmt_st_plus;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_st_d;
-  struct { /*  */
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_acc;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_machi_a;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-    unsigned char out_sr;
-  } sfmt_ld_plus;
-  struct { /*  */
-    IADDR i_disp16;
-    SI* i_src1;
-    SI* i_src2;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_src1;
-    unsigned char in_src2;
-  } sfmt_beq;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_and3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    INT f_simm16;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add3;
-  struct { /*  */
-    SI* i_dr;
-    SI* i_sr;
-    UINT f_r1;
-    UINT f_r2;
-    unsigned char in_dr;
-    unsigned char in_sr;
-    unsigned char out_dr;
-  } sfmt_add;
-#if WITH_SCACHE_PBB
-  /* Writeback handler.  */
-  struct {
-    /* Pointer to argbuf entry for insn whose results need writing back.  */
-    const struct argbuf *abuf;
-  } write;
-  /* x-before handler */
-  struct {
-    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
-    int first_p;
-  } before;
-  /* x-after handler */
-  struct {
-    int empty;
-  } after;
-  /* This entry is used to terminate each pbb.  */
-  struct {
-    /* Number of insns in pbb.  */
-    int insn_count;
-    /* Next pbb to execute.  */
-    SCACHE *next;
-    SCACHE *branch_target;
-  } chain;
-#endif
-};
-
-/* The ARGBUF struct.  */
-struct argbuf {
-  /* These are the baseclass definitions.  */
-  IADDR addr;
-  const IDESC *idesc;
-  char trace_p;
-  char profile_p;
-  /* ??? Temporary hack for skip insns.  */
-  char skip_count;
-  char unused;
-  /* cpu specific data follows */
-  union sem semantic;
-  int written;
-  union sem_fields fields;
-};
-
-/* A cached insn.
-
-   ??? SCACHE used to contain more than just argbuf.  We could delete the
-   type entirely and always just use ARGBUF, but for future concerns and as
-   a level of abstraction it is left in.  */
-
-struct scache {
-  struct argbuf argbuf;
-};
-
-/* Macros to simplify extraction, reading and semantic code.
-   These define and assign the local vars that contain the insn's fields.  */
-
-#define EXTRACT_IFMT_EMPTY_VARS \
-  unsigned int length;
-#define EXTRACT_IFMT_EMPTY_CODE \
-  length = 0; \
-
-#define EXTRACT_IFMT_ADD_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_ADD3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADD3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_AND3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_AND3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_OR3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_OR3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_ADDI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  INT f_simm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_ADDV3_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ADDV3_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BC8_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp8; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC8_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
-
-#define EXTRACT_IFMT_BC24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  SI f_disp24; \
-  unsigned int length;
-#define EXTRACT_IFMT_BC24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_BEQZ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  SI f_disp16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BEQZ_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
-
-#define EXTRACT_IFMT_CMP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_CMPI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPI_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_CMPZ_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_CMPZ_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_DIV_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_DIV_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_JC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_JC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_LD24_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm24; \
-  unsigned int length;
-#define EXTRACT_IFMT_LD24_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
-
-#define EXTRACT_IFMT_LDI16_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_LDI16_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_MACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_acc; \
-  UINT f_op23; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
-  f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVFACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVFC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_MVTACHI_A_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTACHI_A_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
-
-#define EXTRACT_IFMT_MVTC_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_MVTC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_NOP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_NOP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_RAC_DSI_VARS \
-  UINT f_op1; \
-  UINT f_accd; \
-  UINT f_bits67; \
-  UINT f_op2; \
-  UINT f_accs; \
-  UINT f_bit14; \
-  SI f_imm1; \
-  unsigned int length;
-#define EXTRACT_IFMT_RAC_DSI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
-  f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
-  f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
-  f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
-
-#define EXTRACT_IFMT_SETH_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_hi16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SETH_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_SLLI_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_shift_op2; \
-  UINT f_uimm5; \
-  unsigned int length;
-#define EXTRACT_IFMT_SLLI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
-
-#define EXTRACT_IFMT_ST_D_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_ST_D_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_TRAP_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_uimm4; \
-  unsigned int length;
-#define EXTRACT_IFMT_TRAP_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-#define EXTRACT_IFMT_SATB_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_SATB_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_CLRPSW_VARS \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_uimm8; \
-  unsigned int length;
-#define EXTRACT_IFMT_CLRPSW_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
-  f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
-
-#define EXTRACT_IFMT_BSET_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  INT f_simm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_BSET_CODE \
-  length = 4; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
-
-#define EXTRACT_IFMT_BTST_VARS \
-  UINT f_op1; \
-  UINT f_bit4; \
-  UINT f_uimm3; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_IFMT_BTST_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
-  f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
-  f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
-  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
-
-/* Queued output values of an instruction.  */
-
-struct parexec {
-  union {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } sfmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI dr;
-    } sfmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      SI dr;
-    } sfmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      SI dr;
-    } sfmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      SI dr;
-    } sfmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      SI dr;
-    } sfmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      BI condbit;
-      SI dr;
-    } sfmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      BI condbit;
-      SI dr;
-    } sfmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      BI condbit;
-      SI dr;
-    } sfmt_addx;
-    struct { /* e.g. bc.s $disp8 */
-      USI pc;
-    } sfmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      USI pc;
-    } sfmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      USI pc;
-    } sfmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      USI pc;
-    } sfmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bl24;
-    struct { /* e.g. bcl.s $disp8 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bcl8;
-    struct { /* e.g. bcl.l $disp24 */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_bcl24;
-    struct { /* e.g. bra.s $disp8 */
-      USI pc;
-    } sfmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      USI pc;
-    } sfmt_bra24;
-    struct { /* e.g. cmp $src1,$src2 */
-      BI condbit;
-    } sfmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      BI condbit;
-    } sfmt_cmpi;
-    struct { /* e.g. cmpz $src2 */
-      BI condbit;
-    } sfmt_cmpz;
-    struct { /* e.g. div $dr,$sr */
-      SI dr;
-    } sfmt_div;
-    struct { /* e.g. jc $sr */
-      USI pc;
-    } sfmt_jc;
-    struct { /* e.g. jl $sr */
-      SI h_gr_SI_14;
-      USI pc;
-    } sfmt_jl;
-    struct { /* e.g. jmp $sr */
-      USI pc;
-    } sfmt_jmp;
-    struct { /* e.g. ld $dr,@$sr */
-      SI dr;
-    } sfmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI dr;
-    } sfmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI dr;
-    } sfmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      SI dr;
-    } sfmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI dr;
-      SI sr;
-    } sfmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      SI dr;
-    } sfmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      SI dr;
-    } sfmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      SI dr;
-    } sfmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI dr;
-      BI h_lock_BI;
-    } sfmt_lock;
-    struct { /* e.g. machi $src1,$src2,$acc */
-      DI acc;
-    } sfmt_machi_a;
-    struct { /* e.g. mulhi $src1,$src2,$acc */
-      DI acc;
-    } sfmt_mulhi_a;
-    struct { /* e.g. mv $dr,$sr */
-      SI dr;
-    } sfmt_mv;
-    struct { /* e.g. mvfachi $dr,$accs */
-      SI dr;
-    } sfmt_mvfachi_a;
-    struct { /* e.g. mvfc $dr,$scr */
-      SI dr;
-    } sfmt_mvfc;
-    struct { /* e.g. mvtachi $src1,$accs */
-      DI accs;
-    } sfmt_mvtachi_a;
-    struct { /* e.g. mvtc $sr,$dcr */
-      USI dcr;
-    } sfmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } sfmt_nop;
-    struct { /* e.g. rac $accd,$accs,$imm1 */
-      DI accd;
-    } sfmt_rac_dsi;
-    struct { /* e.g. rte */
-      UQI h_bpsw_UQI;
-      USI h_cr_USI_6;
-      UQI h_psw_UQI;
-      USI pc;
-    } sfmt_rte;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      SI dr;
-    } sfmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      SI dr;
-    } sfmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      SI dr;
-    } sfmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI h_memory_SI_src2;
-      USI h_memory_SI_src2_idx;
-    } sfmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      SI h_memory_SI_add__DFLT_src2_slo16;
-      USI h_memory_SI_add__DFLT_src2_slo16_idx;
-    } sfmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      QI h_memory_QI_src2;
-      USI h_memory_QI_src2_idx;
-    } sfmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      QI h_memory_QI_add__DFLT_src2_slo16;
-      USI h_memory_QI_add__DFLT_src2_slo16_idx;
-    } sfmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      HI h_memory_HI_src2;
-      USI h_memory_HI_src2_idx;
-    } sfmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      HI h_memory_HI_add__DFLT_src2_slo16;
-      USI h_memory_HI_add__DFLT_src2_slo16_idx;
-    } sfmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI h_memory_SI_new_src2;
-      USI h_memory_SI_new_src2_idx;
-      SI src2;
-    } sfmt_st_plus;
-    struct { /* e.g. sth $src1,@$src2+ */
-      HI h_memory_HI_new_src2;
-      USI h_memory_HI_new_src2_idx;
-      SI src2;
-    } sfmt_sth_plus;
-    struct { /* e.g. stb $src1,@$src2+ */
-      QI h_memory_QI_new_src2;
-      USI h_memory_QI_new_src2_idx;
-      SI src2;
-    } sfmt_stb_plus;
-    struct { /* e.g. trap $uimm4 */
-      UQI h_bbpsw_UQI;
-      UQI h_bpsw_UQI;
-      USI h_cr_USI_14;
-      USI h_cr_USI_6;
-      UQI h_psw_UQI;
-      SI pc;
-    } sfmt_trap;
-    struct { /* e.g. unlock $src1,@$src2 */
-      BI h_lock_BI;
-      SI h_memory_SI_src2;
-      USI h_memory_SI_src2_idx;
-    } sfmt_unlock;
-    struct { /* e.g. satb $dr,$sr */
-      SI dr;
-    } sfmt_satb;
-    struct { /* e.g. sat $dr,$sr */
-      SI dr;
-    } sfmt_sat;
-    struct { /* e.g. sadd */
-      DI h_accums_DI_0;
-    } sfmt_sadd;
-    struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums_DI_1;
-    } sfmt_macwu1;
-    struct { /* e.g. msblo $src1,$src2 */
-      DI accum;
-    } sfmt_msblo;
-    struct { /* e.g. mulwu1 $src1,$src2 */
-      DI h_accums_DI_1;
-    } sfmt_mulwu1;
-    struct { /* e.g. sc */
-      int empty;
-    } sfmt_sc;
-    struct { /* e.g. clrpsw $uimm8 */
-      USI h_cr_USI_0;
-    } sfmt_clrpsw;
-    struct { /* e.g. setpsw $uimm8 */
-      USI h_cr_USI_0;
-    } sfmt_setpsw;
-    struct { /* e.g. bset $uimm3,@($slo16,$sr) */
-      QI h_memory_QI_add__DFLT_sr_slo16;
-      USI h_memory_QI_add__DFLT_sr_slo16_idx;
-    } sfmt_bset;
-    struct { /* e.g. btst $uimm3,$sr */
-      BI condbit;
-    } sfmt_btst;
-  } operands;
-  /* For conditionally written operands, bitmask of which ones were.  */
-  int written;
-};
-
-/* Collection of various things for the trace handler to use.  */
-
-typedef struct trace_record {
-  IADDR pc;
-  /* FIXME:wip */
-} TRACE_RECORD;
-
-#endif /* CPU_M32RXF_H */
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
deleted file mode 100644
index 0831af4..0000000
--- a/sim/m32r/decode.c
+++ /dev/null
@@ -1,2113 +0,0 @@
-/* Simulator instruction decoder for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem m32rbf_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
-  { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD },
-  { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 },
-  { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD },
-  { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 },
-  { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD },
-  { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 },
-  { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD },
-  { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 },
-  { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI },
-  { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV },
-  { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 },
-  { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX },
-  { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 },
-  { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 },
-  { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ },
-  { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ },
-  { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 },
-  { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 },
-  { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 },
-  { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 },
-  { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ },
-  { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 },
-  { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 },
-  { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP },
-  { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI },
-  { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP },
-  { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI },
-  { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV },
-  { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV },
-  { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV },
-  { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV },
-  { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL },
-  { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP },
-  { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD },
-  { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D },
-  { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LDB },
-  { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LDB_D },
-  { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LDH },
-  { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LDH_D },
-  { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LDB },
-  { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LDB_D },
-  { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LDH },
-  { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LDH_D },
-  { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS },
-  { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 },
-  { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 },
-  { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 },
-  { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK },
-  { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI },
-  { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI },
-  { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI },
-  { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI },
-  { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD },
-  { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI },
-  { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI },
-  { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI },
-  { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI },
-  { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV },
-  { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI },
-  { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI },
-  { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI },
-  { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC },
-  { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI },
-  { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI },
-  { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC },
-  { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV },
-  { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP },
-  { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV },
-  { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC },
-  { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC },
-  { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE },
-  { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH },
-  { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD },
-  { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 },
-  { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI },
-  { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD },
-  { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 },
-  { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI },
-  { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD },
-  { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 },
-  { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI },
-  { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST },
-  { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D },
-  { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB },
-  { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D },
-  { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH },
-  { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D },
-  { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS },
-  { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS },
-  { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD },
-  { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV },
-  { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX },
-  { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP },
-  { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK },
-  { M32R_INSN_CLRPSW, M32RBF_INSN_CLRPSW, M32RBF_SFMT_CLRPSW },
-  { M32R_INSN_SETPSW, M32RBF_INSN_SETPSW, M32RBF_SFMT_SETPSW },
-  { M32R_INSN_BSET, M32RBF_INSN_BSET, M32RBF_SFMT_BSET },
-  { M32R_INSN_BCLR, M32RBF_INSN_BCLR, M32RBF_SFMT_BSET },
-  { M32R_INSN_BTST, M32RBF_INSN_BTST, M32RBF_SFMT_BTST },
-};
-
-static const struct insn_sem m32rbf_insn_sem_invalid = {
-  VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
-};
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
-
-  id->num = t->index;
-  id->sfmt = t->sfmt;
-  if ((int) t->type <= 0)
-    id->idata = & cgen_virtual_insn_table[- (int) t->type];
-  else
-    id->idata = & insn_table[t->type];
-  id->attrs = CGEN_INSN_ATTRS (id->idata);
-  /* Oh my god, a magic number.  */
-  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-
-  /* Semantic pointers are initialized elsewhere.  */
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-m32rbf_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = M32RBF_INSN__MAX;
-  IDESC *table = m32rbf_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & m32rbf_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder.  */
-  M32RBF_INSN_TYPE itype;
-
-  {
-    CGEN_INSN_INT insn = base_insn;
-
-    {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
-      {
-      case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;
-      case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;
-      case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add;
-      case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv;
-      case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp;
-      case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp;
-      case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv;
-      case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx;
-      case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add;
-      case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv;
-      case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;
-      case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
-      case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32RBF_INSN_BTST; goto extract_sfmt_btst;
-      case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
-      case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
-      case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
-      case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add;
-      case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv;
-      case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc;
-      case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;
-      case 28 :
-        {
-          unsigned int val = (((insn >> 8) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl;
-          case 1 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap;
-      case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb;
-      case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth;
-      case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st;
-      case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock;
-      case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
-      case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
-      case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ldb;
-      case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ldb;
-      case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ldh;
-      case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ldh;
-      case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld;
-      case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock;
-      case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
-      case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi;
-      case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi;
-      case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi;
-      case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi;
-      case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi;
-      case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi;
-      case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi;
-      case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi;
-      case 64 : /* fall through */
-      case 65 : /* fall through */
-      case 66 : /* fall through */
-      case 67 : /* fall through */
-      case 68 : /* fall through */
-      case 69 : /* fall through */
-      case 70 : /* fall through */
-      case 71 : /* fall through */
-      case 72 : /* fall through */
-      case 73 : /* fall through */
-      case 74 : /* fall through */
-      case 75 : /* fall through */
-      case 76 : /* fall through */
-      case 77 : /* fall through */
-      case 78 : /* fall through */
-      case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi;
-      case 80 : /* fall through */
-      case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli;
-      case 82 : /* fall through */
-      case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli;
-      case 84 : /* fall through */
-      case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;
-      case 87 :
-        {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi;
-          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac;
-      case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac;
-      case 95 :
-        {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi;
-          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi;
-          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 96 : /* fall through */
-      case 97 : /* fall through */
-      case 98 : /* fall through */
-      case 99 : /* fall through */
-      case 100 : /* fall through */
-      case 101 : /* fall through */
-      case 102 : /* fall through */
-      case 103 : /* fall through */
-      case 104 : /* fall through */
-      case 105 : /* fall through */
-      case 106 : /* fall through */
-      case 107 : /* fall through */
-      case 108 : /* fall through */
-      case 109 : /* fall through */
-      case 110 : /* fall through */
-      case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;
-      case 112 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;
-          case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
-          case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
-          case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
-          case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 113 : /* fall through */
-      case 114 : /* fall through */
-      case 115 : /* fall through */
-      case 116 : /* fall through */
-      case 117 : /* fall through */
-      case 118 : /* fall through */
-      case 119 : /* fall through */
-      case 120 : /* fall through */
-      case 121 : /* fall through */
-      case 122 : /* fall through */
-      case 123 : /* fall through */
-      case 124 : /* fall through */
-      case 125 : /* fall through */
-      case 126 : /* fall through */
-      case 127 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
-          case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
-          case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
-          case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi;
-      case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;
-      case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;
-      case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;
-      case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;
-      case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;
-      case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div;
-      case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div;
-      case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div;
-      case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div;
-      case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;
-      case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;
-      case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16;
-      case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
-      case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
-      case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32RBF_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset;
-      case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d;
-      case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
-      case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d;
-      case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ldh_d;
-      case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;
-      case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;
-      case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth;
-      case 224 : /* fall through */
-      case 225 : /* fall through */
-      case 226 : /* fall through */
-      case 227 : /* fall through */
-      case 228 : /* fall through */
-      case 229 : /* fall through */
-      case 230 : /* fall through */
-      case 231 : /* fall through */
-      case 232 : /* fall through */
-      case 233 : /* fall through */
-      case 234 : /* fall through */
-      case 235 : /* fall through */
-      case 236 : /* fall through */
-      case 237 : /* fall through */
-      case 238 : /* fall through */
-      case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24;
-      case 240 : /* fall through */
-      case 241 : /* fall through */
-      case 242 : /* fall through */
-      case 243 : /* fall through */
-      case 244 : /* fall through */
-      case 245 : /* fall through */
-      case 246 : /* fall through */
-      case 247 : /* fall through */
-      case 248 : /* fall through */
-      case 249 : /* fall through */
-      case 250 : /* fall through */
-      case 251 : /* fall through */
-      case 252 : /* fall through */
-      case 253 : /* fall through */
-      case 254 : /* fall through */
-      case 255 :
-        {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24;
-          case 1 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24;
-          case 2 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24;
-          case 3 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
-      }
-    }
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract_sfmt_empty:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add3:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_and3:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_or3:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv3:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addx:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc8:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc24:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beq:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r1;
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beqz:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl8:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl24:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra8:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra24:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmp:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jl:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jmp:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_plus:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-      FLD (out_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld24:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld24.f
-    UINT f_r1;
-    UINT f_uimm24;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_uimm24) = f_uimm24;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi8:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi16:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lock:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_machi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mulhi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mv:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfachi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_seth.f
-    UINT f_r1;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfc:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtachi:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtc:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_nop:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rac:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rte:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_seth:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_seth.f
-    UINT f_r1;
-    UINT f_hi16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_hi16) = f_hi16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sll3:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_slli:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_slli.f
-    UINT f_r1;
-    UINT f_uimm5;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_uimm5) = f_uimm5;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_plus:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_trap:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_trap.f
-    UINT f_uimm4;
-
-    f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm4) = f_uimm4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_unlock:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrpsw:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_setpsw:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bset:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_btst:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
-}
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
deleted file mode 100644
index 00a411c..0000000
--- a/sim/m32r/decode.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* Decode header for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32RBF_DECODE_H
-#define M32RBF_DECODE_H
-
-extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-extern void m32rbf_init_idesc_table (SIM_CPU *);
-extern void m32rbf_sem_init_idesc_table (SIM_CPU *);
-extern void m32rbf_semf_init_idesc_table (SIM_CPU *);
-
-/* Enum declaration for instructions in cpu family m32rbf.  */
-typedef enum m32rbf_insn_type {
-  M32RBF_INSN_X_INVALID, M32RBF_INSN_X_AFTER, M32RBF_INSN_X_BEFORE, M32RBF_INSN_X_CTI_CHAIN
- , M32RBF_INSN_X_CHAIN, M32RBF_INSN_X_BEGIN, M32RBF_INSN_ADD, M32RBF_INSN_ADD3
- , M32RBF_INSN_AND, M32RBF_INSN_AND3, M32RBF_INSN_OR, M32RBF_INSN_OR3
- , M32RBF_INSN_XOR, M32RBF_INSN_XOR3, M32RBF_INSN_ADDI, M32RBF_INSN_ADDV
- , M32RBF_INSN_ADDV3, M32RBF_INSN_ADDX, M32RBF_INSN_BC8, M32RBF_INSN_BC24
- , M32RBF_INSN_BEQ, M32RBF_INSN_BEQZ, M32RBF_INSN_BGEZ, M32RBF_INSN_BGTZ
- , M32RBF_INSN_BLEZ, M32RBF_INSN_BLTZ, M32RBF_INSN_BNEZ, M32RBF_INSN_BL8
- , M32RBF_INSN_BL24, M32RBF_INSN_BNC8, M32RBF_INSN_BNC24, M32RBF_INSN_BNE
- , M32RBF_INSN_BRA8, M32RBF_INSN_BRA24, M32RBF_INSN_CMP, M32RBF_INSN_CMPI
- , M32RBF_INSN_CMPU, M32RBF_INSN_CMPUI, M32RBF_INSN_DIV, M32RBF_INSN_DIVU
- , M32RBF_INSN_REM, M32RBF_INSN_REMU, M32RBF_INSN_JL, M32RBF_INSN_JMP
- , M32RBF_INSN_LD, M32RBF_INSN_LD_D, M32RBF_INSN_LDB, M32RBF_INSN_LDB_D
- , M32RBF_INSN_LDH, M32RBF_INSN_LDH_D, M32RBF_INSN_LDUB, M32RBF_INSN_LDUB_D
- , M32RBF_INSN_LDUH, M32RBF_INSN_LDUH_D, M32RBF_INSN_LD_PLUS, M32RBF_INSN_LD24
- , M32RBF_INSN_LDI8, M32RBF_INSN_LDI16, M32RBF_INSN_LOCK, M32RBF_INSN_MACHI
- , M32RBF_INSN_MACLO, M32RBF_INSN_MACWHI, M32RBF_INSN_MACWLO, M32RBF_INSN_MUL
- , M32RBF_INSN_MULHI, M32RBF_INSN_MULLO, M32RBF_INSN_MULWHI, M32RBF_INSN_MULWLO
- , M32RBF_INSN_MV, M32RBF_INSN_MVFACHI, M32RBF_INSN_MVFACLO, M32RBF_INSN_MVFACMI
- , M32RBF_INSN_MVFC, M32RBF_INSN_MVTACHI, M32RBF_INSN_MVTACLO, M32RBF_INSN_MVTC
- , M32RBF_INSN_NEG, M32RBF_INSN_NOP, M32RBF_INSN_NOT, M32RBF_INSN_RAC
- , M32RBF_INSN_RACH, M32RBF_INSN_RTE, M32RBF_INSN_SETH, M32RBF_INSN_SLL
- , M32RBF_INSN_SLL3, M32RBF_INSN_SLLI, M32RBF_INSN_SRA, M32RBF_INSN_SRA3
- , M32RBF_INSN_SRAI, M32RBF_INSN_SRL, M32RBF_INSN_SRL3, M32RBF_INSN_SRLI
- , M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
- , M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
- , M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
- , M32RBF_INSN_UNLOCK, M32RBF_INSN_CLRPSW, M32RBF_INSN_SETPSW, M32RBF_INSN_BSET
- , M32RBF_INSN_BCLR, M32RBF_INSN_BTST, M32RBF_INSN__MAX
-} M32RBF_INSN_TYPE;
-
-/* Enum declaration for semantic formats in cpu family m32rbf.  */
-typedef enum m32rbf_sfmt_type {
-  M32RBF_SFMT_EMPTY, M32RBF_SFMT_ADD, M32RBF_SFMT_ADD3, M32RBF_SFMT_AND3
- , M32RBF_SFMT_OR3, M32RBF_SFMT_ADDI, M32RBF_SFMT_ADDV, M32RBF_SFMT_ADDV3
- , M32RBF_SFMT_ADDX, M32RBF_SFMT_BC8, M32RBF_SFMT_BC24, M32RBF_SFMT_BEQ
- , M32RBF_SFMT_BEQZ, M32RBF_SFMT_BL8, M32RBF_SFMT_BL24, M32RBF_SFMT_BRA8
- , M32RBF_SFMT_BRA24, M32RBF_SFMT_CMP, M32RBF_SFMT_CMPI, M32RBF_SFMT_DIV
- , M32RBF_SFMT_JL, M32RBF_SFMT_JMP, M32RBF_SFMT_LD, M32RBF_SFMT_LD_D
- , M32RBF_SFMT_LDB, M32RBF_SFMT_LDB_D, M32RBF_SFMT_LDH, M32RBF_SFMT_LDH_D
- , M32RBF_SFMT_LD_PLUS, M32RBF_SFMT_LD24, M32RBF_SFMT_LDI8, M32RBF_SFMT_LDI16
- , M32RBF_SFMT_LOCK, M32RBF_SFMT_MACHI, M32RBF_SFMT_MULHI, M32RBF_SFMT_MV
- , M32RBF_SFMT_MVFACHI, M32RBF_SFMT_MVFC, M32RBF_SFMT_MVTACHI, M32RBF_SFMT_MVTC
- , M32RBF_SFMT_NOP, M32RBF_SFMT_RAC, M32RBF_SFMT_RTE, M32RBF_SFMT_SETH
- , M32RBF_SFMT_SLL3, M32RBF_SFMT_SLLI, M32RBF_SFMT_ST, M32RBF_SFMT_ST_D
- , M32RBF_SFMT_STB, M32RBF_SFMT_STB_D, M32RBF_SFMT_STH, M32RBF_SFMT_STH_D
- , M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK, M32RBF_SFMT_CLRPSW
- , M32RBF_SFMT_SETPSW, M32RBF_SFMT_BSET, M32RBF_SFMT_BTST
-} M32RBF_SFMT_TYPE;
-
-/* Function unit handlers (user written).  */
-
-extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
-extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
-extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
-extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void m32rbf_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void m32rbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* M32RBF_DECODE_H */
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
deleted file mode 100644
index d98db5e..0000000
--- a/sim/m32r/decode2.c
+++ /dev/null
@@ -1,2609 +0,0 @@
-/* Simulator instruction decoder for m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32r2f
-#define WANT_CPU_M32R2F
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* Insn can't be executed in parallel.
-   Or is that "do NOt Pass to Air defense Radar"? :-) */
-#define NOPAR (-1)
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem m32r2f_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD },
-  { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR  },
-  { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
-  { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR  },
-  { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R2F_INSN_WRITE_OR },
-  { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR  },
-  { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR },
-  { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR  },
-  { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADDI, M32R2F_INSN_WRITE_ADDI },
-  { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV },
-  { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR  },
-  { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADDX, M32R2F_INSN_WRITE_ADDX },
-  { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8 },
-  { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR  },
-  { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR  },
-  { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M32R2F_INSN_WRITE_BL8 },
-  { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR  },
-  { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8 },
-  { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR  },
-  { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8, M32R2F_INSN_WRITE_BNC8 },
-  { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR  },
-  { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR  },
-  { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8 },
-  { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR  },
-  { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BNCL8, M32R2F_INSN_WRITE_BNCL8 },
-  { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR  },
-  { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP },
-  { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR  },
-  { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU, M32R2F_INSN_WRITE_CMPU },
-  { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR  },
-  { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ },
-  { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMPZ, M32R2F_INSN_WRITE_CMPZ },
-  { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC },
-  { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M32R2F_INSN_WRITE_JNC },
-  { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL },
-  { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M32R2F_INSN_WRITE_JMP },
-  { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD },
-  { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M32R2F_INSN_WRITE_LDB },
-  { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH },
-  { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB, M32R2F_INSN_WRITE_LDUB },
-  { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH },
-  { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR  },
-  { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INSN_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS },
-  { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR  },
-  { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8 },
-  { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR  },
-  { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOCK, M32R2F_INSN_WRITE_LOCK },
-  { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A },
-  { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A },
-  { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A },
-  { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A },
-  { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL },
-  { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A },
-  { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A },
-  { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A },
-  { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A },
-  { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2F_INSN_WRITE_MV },
-  { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A },
-  { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A },
-  { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A },
-  { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVFC, M32R2F_INSN_WRITE_MVFC },
-  { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A },
-  { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A },
-  { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC },
-  { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M32R2F_INSN_WRITE_NEG },
-  { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP },
-  { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M32R2F_INSN_WRITE_NOT },
-  { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI },
-  { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI },
-  { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE },
-  { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR  },
-  { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M32R2F_INSN_WRITE_SLL },
-  { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI },
-  { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M32R2F_INSN_WRITE_SRA },
-  { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI },
-  { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M32R2F_INSN_WRITE_SRL },
-  { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI },
-  { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2F_INSN_WRITE_ST },
-  { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR  },
-  { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB },
-  { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR  },
-  { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M32R2F_INSN_WRITE_STH },
-  { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR  },
-  { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS },
-  { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS },
-  { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS },
-  { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_INSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS },
-  { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB },
-  { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUBV, M32R2F_INSN_WRITE_SUBV },
-  { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX },
-  { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRAP, M32R2F_INSN_WRITE_TRAP },
-  { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK },
-  { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR  },
-  { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR  },
-  { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR  },
-  { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ },
-  { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD },
-  { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACWU1, M32R2F_INSN_WRITE_MACWU1 },
-  { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO },
-  { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_PAR_MULWU1, M32R2F_INSN_WRITE_MULWU1 },
-  { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1 },
-  { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2F_INSN_WRITE_SC },
-  { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC },
-  { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_PAR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW },
-  { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW },
-  { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR  },
-  { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR  },
-  { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTST, M32R2F_INSN_WRITE_BTST },
-};
-
-static const struct insn_sem m32r2f_insn_sem_invalid = {
-  VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
-};
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
-
-  id->num = t->index;
-  id->sfmt = t->sfmt;
-  if ((int) t->type <= 0)
-    id->idata = & cgen_virtual_insn_table[- (int) t->type];
-  else
-    id->idata = & insn_table[t->type];
-  id->attrs = CGEN_INSN_ATTRS (id->idata);
-  /* Oh my god, a magic number.  */
-  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-
-  /* Semantic pointers are initialized elsewhere.  */
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-m32r2f_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = M32R2F_INSN__MAX;
-  IDESC *table = m32r2f_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & m32r2f_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = m32r2f_insn_sem, tend = t + sizeof (m32r2f_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->par_index], t);
-	  table[t->index].par_idesc = &table[t->par_index];
-	}
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->write_index], t);
-	  table[t->par_index].par_idesc = &table[t->write_index];
-	}
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder.  */
-  M32R2F_INSN_TYPE itype;
-
-  {
-    CGEN_INSN_INT insn = base_insn;
-
-    {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
-      {
-      case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv;
-      case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx;
-      case 2 : itype = M32R2F_INSN_SUB; goto extract_sfmt_add;
-      case 3 : itype = M32R2F_INSN_NEG; goto extract_sfmt_mv;
-      case 4 : itype = M32R2F_INSN_CMP; goto extract_sfmt_cmp;
-      case 5 : itype = M32R2F_INSN_CMPU; goto extract_sfmt_cmp;
-      case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;
-      case 7 :
-        {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz;
-          case 3 : itype = M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 8 : itype = M32R2F_INSN_ADDV; goto extract_sfmt_addv;
-      case 9 : itype = M32R2F_INSN_ADDX; goto extract_sfmt_addx;
-      case 10 : itype = M32R2F_INSN_ADD; goto extract_sfmt_add;
-      case 11 : itype = M32R2F_INSN_NOT; goto extract_sfmt_mv;
-      case 12 : itype = M32R2F_INSN_AND; goto extract_sfmt_add;
-      case 13 : itype = M32R2F_INSN_XOR; goto extract_sfmt_add;
-      case 14 : itype = M32R2F_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32R2F_INSN_BTST; goto extract_sfmt_btst;
-      case 16 : itype = M32R2F_INSN_SRL; goto extract_sfmt_add;
-      case 18 : itype = M32R2F_INSN_SRA; goto extract_sfmt_add;
-      case 20 : itype = M32R2F_INSN_SLL; goto extract_sfmt_add;
-      case 22 : itype = M32R2F_INSN_MUL; goto extract_sfmt_add;
-      case 24 : itype = M32R2F_INSN_MV; goto extract_sfmt_mv;
-      case 25 : itype = M32R2F_INSN_MVFC; goto extract_sfmt_mvfc;
-      case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;
-      case 28 :
-        {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_JC; goto extract_sfmt_jc;
-          case 1 : itype = M32R2F_INSN_JNC; goto extract_sfmt_jc;
-          case 2 : itype = M32R2F_INSN_JL; goto extract_sfmt_jl;
-          case 3 : itype = M32R2F_INSN_JMP; goto extract_sfmt_jmp;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 29 : itype = M32R2F_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32R2F_INSN_TRAP; goto extract_sfmt_trap;
-      case 32 : itype = M32R2F_INSN_STB; goto extract_sfmt_stb;
-      case 33 : itype = M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
-      case 34 : itype = M32R2F_INSN_STH; goto extract_sfmt_sth;
-      case 35 : itype = M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
-      case 36 : itype = M32R2F_INSN_ST; goto extract_sfmt_st;
-      case 37 : itype = M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock;
-      case 38 : itype = M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus;
-      case 39 : itype = M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus;
-      case 40 : itype = M32R2F_INSN_LDB; goto extract_sfmt_ldb;
-      case 41 : itype = M32R2F_INSN_LDUB; goto extract_sfmt_ldb;
-      case 42 : itype = M32R2F_INSN_LDH; goto extract_sfmt_ldh;
-      case 43 : itype = M32R2F_INSN_LDUH; goto extract_sfmt_ldh;
-      case 44 : itype = M32R2F_INSN_LD; goto extract_sfmt_ld;
-      case 45 : itype = M32R2F_INSN_LOCK; goto extract_sfmt_lock;
-      case 46 : itype = M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
-      case 48 : /* fall through */
-      case 56 : itype = M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
-      case 49 : /* fall through */
-      case 57 : itype = M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
-      case 50 : /* fall through */
-      case 58 : itype = M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
-      case 51 : /* fall through */
-      case 59 : itype = M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
-      case 52 : /* fall through */
-      case 60 : itype = M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a;
-      case 53 : /* fall through */
-      case 61 : itype = M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a;
-      case 54 : /* fall through */
-      case 62 : itype = M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a;
-      case 55 : /* fall through */
-      case 63 : itype = M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a;
-      case 64 : /* fall through */
-      case 65 : /* fall through */
-      case 66 : /* fall through */
-      case 67 : /* fall through */
-      case 68 : /* fall through */
-      case 69 : /* fall through */
-      case 70 : /* fall through */
-      case 71 : /* fall through */
-      case 72 : /* fall through */
-      case 73 : /* fall through */
-      case 74 : /* fall through */
-      case 75 : /* fall through */
-      case 76 : /* fall through */
-      case 77 : /* fall through */
-      case 78 : /* fall through */
-      case 79 : itype = M32R2F_INSN_ADDI; goto extract_sfmt_addi;
-      case 80 : /* fall through */
-      case 81 : itype = M32R2F_INSN_SRLI; goto extract_sfmt_slli;
-      case 82 : /* fall through */
-      case 83 : itype = M32R2F_INSN_SRAI; goto extract_sfmt_slli;
-      case 84 : /* fall through */
-      case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli;
-      case 87 :
-        {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
-          case 1 : itype = M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 88 : itype = M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
-      case 89 : itype = M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
-      case 90 : itype = M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;
-      case 91 : itype = M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;
-      case 92 : itype = M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;
-      case 93 : itype = M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;
-      case 94 : itype = M32R2F_INSN_SADD; goto extract_sfmt_sadd;
-      case 95 :
-        {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
-          case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
-          case 2 : itype = M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 96 : /* fall through */
-      case 97 : /* fall through */
-      case 98 : /* fall through */
-      case 99 : /* fall through */
-      case 100 : /* fall through */
-      case 101 : /* fall through */
-      case 102 : /* fall through */
-      case 103 : /* fall through */
-      case 104 : /* fall through */
-      case 105 : /* fall through */
-      case 106 : /* fall through */
-      case 107 : /* fall through */
-      case 108 : /* fall through */
-      case 109 : /* fall through */
-      case 110 : /* fall through */
-      case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;
-      case 112 :
-        {
-          unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_NOP; goto extract_sfmt_nop;
-          case 2 : /* fall through */
-          case 3 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 4 : /* fall through */
-          case 5 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 9 : itype = M32R2F_INSN_SC; goto extract_sfmt_sc;
-          case 11 : itype = M32R2F_INSN_SNC; goto extract_sfmt_sc;
-          case 16 : /* fall through */
-          case 17 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
-          case 18 : /* fall through */
-          case 19 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
-          case 24 : /* fall through */
-          case 25 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
-          case 26 : /* fall through */
-          case 27 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
-          case 28 : /* fall through */
-          case 29 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
-          case 30 : /* fall through */
-          case 31 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 113 : /* fall through */
-      case 114 : /* fall through */
-      case 115 : /* fall through */
-      case 116 : /* fall through */
-      case 117 : /* fall through */
-      case 118 : /* fall through */
-      case 119 : /* fall through */
-      case 120 : /* fall through */
-      case 121 : /* fall through */
-      case 122 : /* fall through */
-      case 123 : /* fall through */
-      case 124 : /* fall through */
-      case 125 : /* fall through */
-      case 126 : /* fall through */
-      case 127 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 8 : itype = M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;
-          case 9 : itype = M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;
-          case 12 : itype = M32R2F_INSN_BC8; goto extract_sfmt_bc8;
-          case 13 : itype = M32R2F_INSN_BNC8; goto extract_sfmt_bc8;
-          case 14 : itype = M32R2F_INSN_BL8; goto extract_sfmt_bl8;
-          case 15 : itype = M32R2F_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 132 : itype = M32R2F_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi;
-      case 134 :
-        {
-          unsigned int val = (((insn >> -8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_SAT; goto extract_sfmt_sat;
-          case 2 : itype = M32R2F_INSN_SATH; goto extract_sfmt_satb;
-          case 3 : itype = M32R2F_INSN_SATB; goto extract_sfmt_satb;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 136 : itype = M32R2F_INSN_ADDV3; goto extract_sfmt_addv3;
-      case 138 : itype = M32R2F_INSN_ADD3; goto extract_sfmt_add3;
-      case 140 : itype = M32R2F_INSN_AND3; goto extract_sfmt_and3;
-      case 141 : itype = M32R2F_INSN_XOR3; goto extract_sfmt_and3;
-      case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
-      case 144 :
-        {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_DIV; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_DIVH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_DIVB; goto extract_sfmt_div;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 145 :
-        {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_DIVU; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_DIVUH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_DIVUB; goto extract_sfmt_div;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 146 :
-        {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_REM; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_REMH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_REMB; goto extract_sfmt_div;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 147 :
-        {
-          unsigned int val = (((insn >> -13) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_REMU; goto extract_sfmt_div;
-          case 2 : itype = M32R2F_INSN_REMUH; goto extract_sfmt_div;
-          case 3 : itype = M32R2F_INSN_REMUB; goto extract_sfmt_div;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 152 : itype = M32R2F_INSN_SRL3; goto extract_sfmt_sll3;
-      case 154 : itype = M32R2F_INSN_SRA3; goto extract_sfmt_sll3;
-      case 156 : itype = M32R2F_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32R2F_INSN_LDI16; goto extract_sfmt_ldi16;
-      case 160 : itype = M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;
-      case 162 : itype = M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;
-      case 164 : itype = M32R2F_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32R2F_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32R2F_INSN_BCLR; goto extract_sfmt_bset;
-      case 168 : itype = M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;
-      case 169 : itype = M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;
-      case 170 : itype = M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;
-      case 171 : itype = M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d;
-      case 172 : itype = M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;
-      case 176 : itype = M32R2F_INSN_BEQ; goto extract_sfmt_beq;
-      case 177 : itype = M32R2F_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32R2F_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32R2F_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32R2F_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32R2F_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32R2F_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32R2F_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32R2F_INSN_SETH; goto extract_sfmt_seth;
-      case 224 : /* fall through */
-      case 225 : /* fall through */
-      case 226 : /* fall through */
-      case 227 : /* fall through */
-      case 228 : /* fall through */
-      case 229 : /* fall through */
-      case 230 : /* fall through */
-      case 231 : /* fall through */
-      case 232 : /* fall through */
-      case 233 : /* fall through */
-      case 234 : /* fall through */
-      case 235 : /* fall through */
-      case 236 : /* fall through */
-      case 237 : /* fall through */
-      case 238 : /* fall through */
-      case 239 : itype = M32R2F_INSN_LD24; goto extract_sfmt_ld24;
-      case 240 : /* fall through */
-      case 241 : /* fall through */
-      case 242 : /* fall through */
-      case 243 : /* fall through */
-      case 244 : /* fall through */
-      case 245 : /* fall through */
-      case 246 : /* fall through */
-      case 247 : /* fall through */
-      case 248 : /* fall through */
-      case 249 : /* fall through */
-      case 250 : /* fall through */
-      case 251 : /* fall through */
-      case 252 : /* fall through */
-      case 253 : /* fall through */
-      case 254 : /* fall through */
-      case 255 :
-        {
-          unsigned int val = (((insn >> 8) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32R2F_INSN_BCL24; goto extract_sfmt_bcl24;
-          case 1 : itype = M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24;
-          case 4 : itype = M32R2F_INSN_BC24; goto extract_sfmt_bc24;
-          case 5 : itype = M32R2F_INSN_BNC24; goto extract_sfmt_bc24;
-          case 6 : itype = M32R2F_INSN_BL24; goto extract_sfmt_bl24;
-          case 7 : itype = M32R2F_INSN_BRA24; goto extract_sfmt_bra24;
-          default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      default : itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
-      }
-    }
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract_sfmt_empty:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add3:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_and3:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_or3:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addi:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv3:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addx:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc8:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc24:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beq:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r1;
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beqz:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl8:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl24:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bcl8:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bcl24:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra8:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra24:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmp:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpi:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpz:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jc:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jl:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jmp:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_plus:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-      FLD (out_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld24:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld24.f
-    UINT f_r1;
-    UINT f_uimm24;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_uimm24) = f_uimm24;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi8:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi16:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lock:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_machi_a:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-    UINT f_r1;
-    UINT f_acc;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_acc) = f_acc;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mulhi_a:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-    UINT f_r1;
-    UINT f_acc;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (f_acc) = f_acc;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mv:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfachi_a:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-    UINT f_r1;
-    UINT f_accs;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfc:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtachi_a:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-    UINT f_r1;
-    UINT f_accs;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_r1) = f_r1;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtc:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_nop:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rac_dsi:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-    UINT f_accd;
-    UINT f_accs;
-    SI f_imm1;
-
-    f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-    f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_imm1) = f_imm1;
-  FLD (f_accd) = f_accd;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rte:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_seth:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_seth.f
-    UINT f_r1;
-    UINT f_hi16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_hi16) = f_hi16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sll3:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_slli:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_slli.f
-    UINT f_r1;
-    UINT f_uimm5;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_uimm5) = f_uimm5;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth_d:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_plus:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth_plus:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb_plus:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_trap:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_trap.f
-    UINT f_uimm4;
-
-    f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm4) = f_uimm4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_unlock:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_satb:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sat:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sadd:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_macwu1:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_msblo:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mulwu1:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sc:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrpsw:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_setpsw:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bset:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_btst:
-  {
-    const IDESC *idesc = &m32r2f_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
-}
diff --git a/sim/m32r/decode2.h b/sim/m32r/decode2.h
deleted file mode 100644
index 280247e..0000000
--- a/sim/m32r/decode2.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Decode header for m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32R2F_DECODE_H
-#define M32R2F_DECODE_H
-
-extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-extern void m32r2f_init_idesc_table (SIM_CPU *);
-extern void m32r2f_sem_init_idesc_table (SIM_CPU *);
-extern void m32r2f_semf_init_idesc_table (SIM_CPU *);
-
-/* Enum declaration for instructions in cpu family m32r2f.  */
-typedef enum m32r2f_insn_type {
-  M32R2F_INSN_X_INVALID, M32R2F_INSN_X_AFTER, M32R2F_INSN_X_BEFORE, M32R2F_INSN_X_CTI_CHAIN
- , M32R2F_INSN_X_CHAIN, M32R2F_INSN_X_BEGIN, M32R2F_INSN_ADD, M32R2F_INSN_ADD3
- , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3
- , M32R2F_INSN_XOR, M32R2F_INSN_XOR3, M32R2F_INSN_ADDI, M32R2F_INSN_ADDV
- , M32R2F_INSN_ADDV3, M32R2F_INSN_ADDX, M32R2F_INSN_BC8, M32R2F_INSN_BC24
- , M32R2F_INSN_BEQ, M32R2F_INSN_BEQZ, M32R2F_INSN_BGEZ, M32R2F_INSN_BGTZ
- , M32R2F_INSN_BLEZ, M32R2F_INSN_BLTZ, M32R2F_INSN_BNEZ, M32R2F_INSN_BL8
- , M32R2F_INSN_BL24, M32R2F_INSN_BCL8, M32R2F_INSN_BCL24, M32R2F_INSN_BNC8
- , M32R2F_INSN_BNC24, M32R2F_INSN_BNE, M32R2F_INSN_BRA8, M32R2F_INSN_BRA24
- , M32R2F_INSN_BNCL8, M32R2F_INSN_BNCL24, M32R2F_INSN_CMP, M32R2F_INSN_CMPI
- , M32R2F_INSN_CMPU, M32R2F_INSN_CMPUI, M32R2F_INSN_CMPEQ, M32R2F_INSN_CMPZ
- , M32R2F_INSN_DIV, M32R2F_INSN_DIVU, M32R2F_INSN_REM, M32R2F_INSN_REMU
- , M32R2F_INSN_REMH, M32R2F_INSN_REMUH, M32R2F_INSN_REMB, M32R2F_INSN_REMUB
- , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH
- , M32R2F_INSN_JC, M32R2F_INSN_JNC, M32R2F_INSN_JL, M32R2F_INSN_JMP
- , M32R2F_INSN_LD, M32R2F_INSN_LD_D, M32R2F_INSN_LDB, M32R2F_INSN_LDB_D
- , M32R2F_INSN_LDH, M32R2F_INSN_LDH_D, M32R2F_INSN_LDUB, M32R2F_INSN_LDUB_D
- , M32R2F_INSN_LDUH, M32R2F_INSN_LDUH_D, M32R2F_INSN_LD_PLUS, M32R2F_INSN_LD24
- , M32R2F_INSN_LDI8, M32R2F_INSN_LDI16, M32R2F_INSN_LOCK, M32R2F_INSN_MACHI_A
- , M32R2F_INSN_MACLO_A, M32R2F_INSN_MACWHI_A, M32R2F_INSN_MACWLO_A, M32R2F_INSN_MUL
- , M32R2F_INSN_MULHI_A, M32R2F_INSN_MULLO_A, M32R2F_INSN_MULWHI_A, M32R2F_INSN_MULWLO_A
- , M32R2F_INSN_MV, M32R2F_INSN_MVFACHI_A, M32R2F_INSN_MVFACLO_A, M32R2F_INSN_MVFACMI_A
- , M32R2F_INSN_MVFC, M32R2F_INSN_MVTACHI_A, M32R2F_INSN_MVTACLO_A, M32R2F_INSN_MVTC
- , M32R2F_INSN_NEG, M32R2F_INSN_NOP, M32R2F_INSN_NOT, M32R2F_INSN_RAC_DSI
- , M32R2F_INSN_RACH_DSI, M32R2F_INSN_RTE, M32R2F_INSN_SETH, M32R2F_INSN_SLL
- , M32R2F_INSN_SLL3, M32R2F_INSN_SLLI, M32R2F_INSN_SRA, M32R2F_INSN_SRA3
- , M32R2F_INSN_SRAI, M32R2F_INSN_SRL, M32R2F_INSN_SRL3, M32R2F_INSN_SRLI
- , M32R2F_INSN_ST, M32R2F_INSN_ST_D, M32R2F_INSN_STB, M32R2F_INSN_STB_D
- , M32R2F_INSN_STH, M32R2F_INSN_STH_D, M32R2F_INSN_ST_PLUS, M32R2F_INSN_STH_PLUS
- , M32R2F_INSN_STB_PLUS, M32R2F_INSN_ST_MINUS, M32R2F_INSN_SUB, M32R2F_INSN_SUBV
- , M32R2F_INSN_SUBX, M32R2F_INSN_TRAP, M32R2F_INSN_UNLOCK, M32R2F_INSN_SATB
- , M32R2F_INSN_SATH, M32R2F_INSN_SAT, M32R2F_INSN_PCMPBZ, M32R2F_INSN_SADD
- , M32R2F_INSN_MACWU1, M32R2F_INSN_MSBLO, M32R2F_INSN_MULWU1, M32R2F_INSN_MACLH1
- , M32R2F_INSN_SC, M32R2F_INSN_SNC, M32R2F_INSN_CLRPSW, M32R2F_INSN_SETPSW
- , M32R2F_INSN_BSET, M32R2F_INSN_BCLR, M32R2F_INSN_BTST, M32R2F_INSN_PAR_ADD
- , M32R2F_INSN_WRITE_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND, M32R2F_INSN_PAR_OR
- , M32R2F_INSN_WRITE_OR, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR, M32R2F_INSN_PAR_ADDI
- , M32R2F_INSN_WRITE_ADDI, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV, M32R2F_INSN_PAR_ADDX
- , M32R2F_INSN_WRITE_ADDX, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8, M32R2F_INSN_PAR_BL8
- , M32R2F_INSN_WRITE_BL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8, M32R2F_INSN_PAR_BNC8
- , M32R2F_INSN_WRITE_BNC8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8, M32R2F_INSN_PAR_BNCL8
- , M32R2F_INSN_WRITE_BNCL8, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP, M32R2F_INSN_PAR_CMPU
- , M32R2F_INSN_WRITE_CMPU, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ, M32R2F_INSN_PAR_CMPZ
- , M32R2F_INSN_WRITE_CMPZ, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC, M32R2F_INSN_PAR_JNC
- , M32R2F_INSN_WRITE_JNC, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL, M32R2F_INSN_PAR_JMP
- , M32R2F_INSN_WRITE_JMP, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD, M32R2F_INSN_PAR_LDB
- , M32R2F_INSN_WRITE_LDB, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH, M32R2F_INSN_PAR_LDUB
- , M32R2F_INSN_WRITE_LDUB, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH, M32R2F_INSN_PAR_LD_PLUS
- , M32R2F_INSN_WRITE_LD_PLUS, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8, M32R2F_INSN_PAR_LOCK
- , M32R2F_INSN_WRITE_LOCK, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A, M32R2F_INSN_PAR_MACLO_A
- , M32R2F_INSN_WRITE_MACLO_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A, M32R2F_INSN_PAR_MACWLO_A
- , M32R2F_INSN_WRITE_MACWLO_A, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL, M32R2F_INSN_PAR_MULHI_A
- , M32R2F_INSN_WRITE_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A, M32R2F_INSN_PAR_MULWHI_A
- , M32R2F_INSN_WRITE_MULWHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A, M32R2F_INSN_PAR_MV
- , M32R2F_INSN_WRITE_MV, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A, M32R2F_INSN_PAR_MVFACLO_A
- , M32R2F_INSN_WRITE_MVFACLO_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A, M32R2F_INSN_PAR_MVFC
- , M32R2F_INSN_WRITE_MVFC, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A, M32R2F_INSN_PAR_MVTACLO_A
- , M32R2F_INSN_WRITE_MVTACLO_A, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVTC, M32R2F_INSN_PAR_NEG
- , M32R2F_INSN_WRITE_NEG, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP, M32R2F_INSN_PAR_NOT
- , M32R2F_INSN_WRITE_NOT, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI, M32R2F_INSN_PAR_RACH_DSI
- , M32R2F_INSN_WRITE_RACH_DSI, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE, M32R2F_INSN_PAR_SLL
- , M32R2F_INSN_WRITE_SLL, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI, M32R2F_INSN_PAR_SRA
- , M32R2F_INSN_WRITE_SRA, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI, M32R2F_INSN_PAR_SRL
- , M32R2F_INSN_WRITE_SRL, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI, M32R2F_INSN_PAR_ST
- , M32R2F_INSN_WRITE_ST, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB, M32R2F_INSN_PAR_STH
- , M32R2F_INSN_WRITE_STH, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS, M32R2F_INSN_PAR_STH_PLUS
- , M32R2F_INSN_WRITE_STH_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS, M32R2F_INSN_PAR_ST_MINUS
- , M32R2F_INSN_WRITE_ST_MINUS, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB, M32R2F_INSN_PAR_SUBV
- , M32R2F_INSN_WRITE_SUBV, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX, M32R2F_INSN_PAR_TRAP
- , M32R2F_INSN_WRITE_TRAP, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK, M32R2F_INSN_PAR_PCMPBZ
- , M32R2F_INSN_WRITE_PCMPBZ, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD, M32R2F_INSN_PAR_MACWU1
- , M32R2F_INSN_WRITE_MACWU1, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO, M32R2F_INSN_PAR_MULWU1
- , M32R2F_INSN_WRITE_MULWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACLH1, M32R2F_INSN_PAR_SC
- , M32R2F_INSN_WRITE_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC, M32R2F_INSN_PAR_CLRPSW
- , M32R2F_INSN_WRITE_CLRPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETPSW, M32R2F_INSN_PAR_BTST
- , M32R2F_INSN_WRITE_BTST, M32R2F_INSN__MAX
-} M32R2F_INSN_TYPE;
-
-/* Enum declaration for semantic formats in cpu family m32r2f.  */
-typedef enum m32r2f_sfmt_type {
-  M32R2F_SFMT_EMPTY, M32R2F_SFMT_ADD, M32R2F_SFMT_ADD3, M32R2F_SFMT_AND3
- , M32R2F_SFMT_OR3, M32R2F_SFMT_ADDI, M32R2F_SFMT_ADDV, M32R2F_SFMT_ADDV3
- , M32R2F_SFMT_ADDX, M32R2F_SFMT_BC8, M32R2F_SFMT_BC24, M32R2F_SFMT_BEQ
- , M32R2F_SFMT_BEQZ, M32R2F_SFMT_BL8, M32R2F_SFMT_BL24, M32R2F_SFMT_BCL8
- , M32R2F_SFMT_BCL24, M32R2F_SFMT_BRA8, M32R2F_SFMT_BRA24, M32R2F_SFMT_CMP
- , M32R2F_SFMT_CMPI, M32R2F_SFMT_CMPZ, M32R2F_SFMT_DIV, M32R2F_SFMT_JC
- , M32R2F_SFMT_JL, M32R2F_SFMT_JMP, M32R2F_SFMT_LD, M32R2F_SFMT_LD_D
- , M32R2F_SFMT_LDB, M32R2F_SFMT_LDB_D, M32R2F_SFMT_LDH, M32R2F_SFMT_LDH_D
- , M32R2F_SFMT_LD_PLUS, M32R2F_SFMT_LD24, M32R2F_SFMT_LDI8, M32R2F_SFMT_LDI16
- , M32R2F_SFMT_LOCK, M32R2F_SFMT_MACHI_A, M32R2F_SFMT_MULHI_A, M32R2F_SFMT_MV
- , M32R2F_SFMT_MVFACHI_A, M32R2F_SFMT_MVFC, M32R2F_SFMT_MVTACHI_A, M32R2F_SFMT_MVTC
- , M32R2F_SFMT_NOP, M32R2F_SFMT_RAC_DSI, M32R2F_SFMT_RTE, M32R2F_SFMT_SETH
- , M32R2F_SFMT_SLL3, M32R2F_SFMT_SLLI, M32R2F_SFMT_ST, M32R2F_SFMT_ST_D
- , M32R2F_SFMT_STB, M32R2F_SFMT_STB_D, M32R2F_SFMT_STH, M32R2F_SFMT_STH_D
- , M32R2F_SFMT_ST_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_SFMT_TRAP
- , M32R2F_SFMT_UNLOCK, M32R2F_SFMT_SATB, M32R2F_SFMT_SAT, M32R2F_SFMT_SADD
- , M32R2F_SFMT_MACWU1, M32R2F_SFMT_MSBLO, M32R2F_SFMT_MULWU1, M32R2F_SFMT_SC
- , M32R2F_SFMT_CLRPSW, M32R2F_SFMT_SETPSW, M32R2F_SFMT_BSET, M32R2F_SFMT_BTST
-} M32R2F_SFMT_TYPE;
-
-/* Function unit handlers (user written).  */
-
-extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
-extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
-extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void m32r2f_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void m32r2f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* M32R2F_DECODE_H */
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
deleted file mode 100644
index 893abc9..0000000
--- a/sim/m32r/decodex.c
+++ /dev/null
@@ -1,2571 +0,0 @@
-/* Simulator instruction decoder for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-/* Insn can't be executed in parallel.
-   Or is that "do NOt Pass to Air defense Radar"? :-) */
-#define NOPAR (-1)
-
-/* The instruction descriptor array.
-   This is computed at runtime.  Space for it is not malloc'd to save a
-   teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
-   but won't be done until necessary (we don't currently support the runtime
-   addition of instructions nor an SMP machine with different cpus).  */
-static IDESC m32rxf_insn_data[M32RXF_INSN__MAX];
-
-/* Commas between elements are contained in the macros.
-   Some of these are conditionally compiled out.  */
-
-static const struct insn_sem m32rxf_insn_sem[] =
-{
-  { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
-  { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR  },
-  { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
-  { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR  },
-  { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
-  { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR  },
-  { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
-  { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR  },
-  { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
-  { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
-  { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR  },
-  { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
-  { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
-  { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR  },
-  { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR  },
-  { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
-  { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
-  { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR  },
-  { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
-  { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR  },
-  { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
-  { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR  },
-  { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR  },
-  { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
-  { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR  },
-  { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
-  { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR  },
-  { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
-  { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR  },
-  { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
-  { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR  },
-  { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
-  { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
-  { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
-  { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
-  { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
-  { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
-  { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
-  { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
-  { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
-  { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
-  { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
-  { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR  },
-  { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
-  { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR  },
-  { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
-  { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR  },
-  { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
-  { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR  },
-  { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
-  { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
-  { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
-  { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
-  { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
-  { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
-  { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
-  { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
-  { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
-  { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
-  { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
-  { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
-  { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
-  { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
-  { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
-  { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
-  { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
-  { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
-  { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
-  { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
-  { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
-  { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
-  { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
-  { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
-  { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR  },
-  { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
-  { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
-  { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
-  { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
-  { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
-  { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
-  { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
-  { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
-  { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR  },
-  { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
-  { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR  },
-  { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
-  { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR  },
-  { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
-  { M32R_INSN_STH_PLUS, M32RXF_INSN_STH_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS },
-  { M32R_INSN_STB_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS },
-  { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
-  { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
-  { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
-  { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
-  { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
-  { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
-  { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR  },
-  { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR  },
-  { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR  },
-  { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
-  { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
-  { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
-  { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
-  { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
-  { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
-  { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
-  { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
-  { M32R_INSN_CLRPSW, M32RXF_INSN_CLRPSW, M32RXF_SFMT_CLRPSW, M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW },
-  { M32R_INSN_SETPSW, M32RXF_INSN_SETPSW, M32RXF_SFMT_SETPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW },
-  { M32R_INSN_BSET, M32RXF_INSN_BSET, M32RXF_SFMT_BSET, NOPAR, NOPAR  },
-  { M32R_INSN_BCLR, M32RXF_INSN_BCLR, M32RXF_SFMT_BSET, NOPAR, NOPAR  },
-  { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST },
-};
-
-static const struct insn_sem m32rxf_insn_sem_invalid = {
-  VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
-};
-
-/* Initialize an IDESC from the compile-time computable parts.  */
-
-static INLINE void
-init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
-{
-  const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
-
-  id->num = t->index;
-  id->sfmt = t->sfmt;
-  if ((int) t->type <= 0)
-    id->idata = & cgen_virtual_insn_table[- (int) t->type];
-  else
-    id->idata = & insn_table[t->type];
-  id->attrs = CGEN_INSN_ATTRS (id->idata);
-  /* Oh my god, a magic number.  */
-  id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-
-#if WITH_PROFILE_MODEL_P
-  id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
-  {
-    SIM_DESC sd = CPU_STATE (cpu);
-    SIM_ASSERT (t->index == id->timing->num);
-  }
-#endif
-
-  /* Semantic pointers are initialized elsewhere.  */
-}
-
-/* Initialize the instruction descriptor table.  */
-
-void
-m32rxf_init_idesc_table (SIM_CPU *cpu)
-{
-  IDESC *id,*tabend;
-  const struct insn_sem *t,*tend;
-  int tabsize = M32RXF_INSN__MAX;
-  IDESC *table = m32rxf_insn_data;
-
-  memset (table, 0, tabsize * sizeof (IDESC));
-
-  /* First set all entries to the `invalid insn'.  */
-  t = & m32rxf_insn_sem_invalid;
-  for (id = table, tabend = table + tabsize; id < tabend; ++id)
-    init_idesc (cpu, id, t);
-
-  /* Now fill in the values for the chosen cpu.  */
-  for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
-       t != tend; ++t)
-    {
-      init_idesc (cpu, & table[t->index], t);
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->par_index], t);
-	  table[t->index].par_idesc = &table[t->par_index];
-	}
-      if (t->par_index != NOPAR)
-	{
-	  init_idesc (cpu, &table[t->write_index], t);
-	  table[t->par_index].par_idesc = &table[t->write_index];
-	}
-    }
-
-  /* Link the IDESC table into the cpu.  */
-  CPU_IDESC (cpu) = table;
-}
-
-/* Given an instruction, return a pointer to its IDESC entry.  */
-
-const IDESC *
-m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
-              ARGBUF *abuf)
-{
-  /* Result of decoder.  */
-  M32RXF_INSN_TYPE itype;
-
-  {
-    CGEN_INSN_INT insn = base_insn;
-
-    {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
-      {
-      case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
-      case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
-      case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
-      case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
-      case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
-      case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
-      case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
-      case 7 :
-        {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
-          case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
-      case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
-      case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
-      case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
-      case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
-      case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
-      case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32RXF_INSN_BTST; goto extract_sfmt_btst;
-      case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
-      case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
-      case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
-      case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
-      case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
-      case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
-      case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
-      case 28 :
-        {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
-          case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
-          case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
-          case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
-      case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
-      case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
-      case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
-      case 35 : itype = M32RXF_INSN_STH_PLUS; goto extract_sfmt_sth_plus;
-      case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
-      case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
-      case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
-      case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
-      case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ldb;
-      case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ldb;
-      case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ldh;
-      case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ldh;
-      case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
-      case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
-      case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
-      case 48 : /* fall through */
-      case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
-      case 49 : /* fall through */
-      case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
-      case 50 : /* fall through */
-      case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
-      case 51 : /* fall through */
-      case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
-      case 52 : /* fall through */
-      case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
-      case 53 : /* fall through */
-      case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
-      case 54 : /* fall through */
-      case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
-      case 55 : /* fall through */
-      case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
-      case 64 : /* fall through */
-      case 65 : /* fall through */
-      case 66 : /* fall through */
-      case 67 : /* fall through */
-      case 68 : /* fall through */
-      case 69 : /* fall through */
-      case 70 : /* fall through */
-      case 71 : /* fall through */
-      case 72 : /* fall through */
-      case 73 : /* fall through */
-      case 74 : /* fall through */
-      case 75 : /* fall through */
-      case 76 : /* fall through */
-      case 77 : /* fall through */
-      case 78 : /* fall through */
-      case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
-      case 80 : /* fall through */
-      case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
-      case 82 : /* fall through */
-      case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
-      case 84 : /* fall through */
-      case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
-      case 87 :
-        {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
-          case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
-      case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
-      case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
-      case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
-      case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
-      case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
-      case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
-      case 95 :
-        {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
-          case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
-          case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 96 : /* fall through */
-      case 97 : /* fall through */
-      case 98 : /* fall through */
-      case 99 : /* fall through */
-      case 100 : /* fall through */
-      case 101 : /* fall through */
-      case 102 : /* fall through */
-      case 103 : /* fall through */
-      case 104 : /* fall through */
-      case 105 : /* fall through */
-      case 106 : /* fall through */
-      case 107 : /* fall through */
-      case 108 : /* fall through */
-      case 109 : /* fall through */
-      case 110 : /* fall through */
-      case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
-      case 112 :
-        {
-          unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
-          case 2 : /* fall through */
-          case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 4 : /* fall through */
-          case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
-          case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
-          case 16 : /* fall through */
-          case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
-          case 18 : /* fall through */
-          case 19 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
-          case 24 : /* fall through */
-          case 25 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
-          case 26 : /* fall through */
-          case 27 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
-          case 28 : /* fall through */
-          case 29 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
-          case 30 : /* fall through */
-          case 31 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 113 : /* fall through */
-      case 114 : /* fall through */
-      case 115 : /* fall through */
-      case 116 : /* fall through */
-      case 117 : /* fall through */
-      case 118 : /* fall through */
-      case 119 : /* fall through */
-      case 120 : /* fall through */
-      case 121 : /* fall through */
-      case 122 : /* fall through */
-      case 123 : /* fall through */
-      case 124 : /* fall through */
-      case 125 : /* fall through */
-      case 126 : /* fall through */
-      case 127 :
-        {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
-          {
-          case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
-          case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
-          case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
-          case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
-          case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
-          case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
-          case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
-      case 134 :
-        {
-          unsigned int val = (((insn >> -8) & (3 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
-          case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
-          case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
-      case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
-      case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
-      case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
-      case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
-      case 144 :
-        {
-          unsigned int val = (((insn >> -12) & (1 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
-          case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
-      case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
-      case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
-      case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
-      case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
-      case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
-      case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
-      case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
-      case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32RXF_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset;
-      case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
-      case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
-      case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
-      case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ldh_d;
-      case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
-      case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
-      case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
-      case 224 : /* fall through */
-      case 225 : /* fall through */
-      case 226 : /* fall through */
-      case 227 : /* fall through */
-      case 228 : /* fall through */
-      case 229 : /* fall through */
-      case 230 : /* fall through */
-      case 231 : /* fall through */
-      case 232 : /* fall through */
-      case 233 : /* fall through */
-      case 234 : /* fall through */
-      case 235 : /* fall through */
-      case 236 : /* fall through */
-      case 237 : /* fall through */
-      case 238 : /* fall through */
-      case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
-      case 240 : /* fall through */
-      case 241 : /* fall through */
-      case 242 : /* fall through */
-      case 243 : /* fall through */
-      case 244 : /* fall through */
-      case 245 : /* fall through */
-      case 246 : /* fall through */
-      case 247 : /* fall through */
-      case 248 : /* fall through */
-      case 249 : /* fall through */
-      case 250 : /* fall through */
-      case 251 : /* fall through */
-      case 252 : /* fall through */
-      case 253 : /* fall through */
-      case 254 : /* fall through */
-      case 255 :
-        {
-          unsigned int val = (((insn >> 8) & (7 << 0)));
-          switch (val)
-          {
-          case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
-          case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
-          case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
-          case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
-          case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
-          case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
-          default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-          }
-        }
-      default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
-      }
-    }
-  }
-
-  /* The instruction has been decoded, now extract the fields.  */
-
- extract_sfmt_empty:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_add3:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_and3:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_or3:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_and3.f
-    UINT f_r1;
-    UINT f_r2;
-    UINT f_uimm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm16) = f_uimm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addi:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_simm8) = f_simm8;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addv3:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_addx:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc8:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bc24:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beq:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r1;
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_beqz:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_beq.f
-    UINT f_r2;
-    SI f_disp16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_disp16) = f_disp16;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl8:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bl24:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bcl8:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bcl24:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra8:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-    SI f_disp8;
-
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bra24:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bl24.f
-    SI f_disp24;
-
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmp:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpi:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_cmpz:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_div:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jc:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jl:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_h_gr_SI_14) = 14;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_jmp:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_jl.f
-    UINT f_r2;
-
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldb_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldh_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld_plus:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-      FLD (out_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ld24:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld24.f
-    UINT f_r1;
-    UINT f_uimm24;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (i_uimm24) = f_uimm24;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi8:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_addi.f
-    UINT f_r1;
-    INT f_simm8;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm8) = f_simm8;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_ldi16:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_lock:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_machi_a:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-    UINT f_r1;
-    UINT f_acc;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_acc) = f_acc;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mulhi_a:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-    UINT f_r1;
-    UINT f_acc;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (f_acc) = f_acc;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mv:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfachi_a:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-    UINT f_r1;
-    UINT f_accs;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvfc:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtachi_a:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-    UINT f_r1;
-    UINT f_accs;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_r1) = f_r1;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mvtc:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_nop:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rac_dsi:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-    UINT f_accd;
-    UINT f_accs;
-    SI f_imm1;
-
-    f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
-    f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
-    f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_accs) = f_accs;
-  FLD (f_imm1) = f_imm1;
-  FLD (f_accd) = f_accd;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_rte:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_seth:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_seth.f
-    UINT f_r1;
-    UINT f_hi16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_hi16) = f_hi16;
-  FLD (f_r1) = f_r1;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sll3:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_add3.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_slli:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_slli.f
-    UINT f_r1;
-    UINT f_uimm5;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_uimm5) = f_uimm5;
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_dr) = f_r1;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth_d:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_d.f
-    UINT f_r1;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_st_plus:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sth_plus:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_stb_plus:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-      FLD (out_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_trap:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_trap.f
-    UINT f_uimm4;
-
-    f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm4) = f_uimm4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_unlock:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_satb:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sat:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_r1) = f_r1;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sadd:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_macwu1:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_msblo:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_mulwu1:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-    UINT f_r1;
-    UINT f_r2;
-
-    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r1) = f_r1;
-  FLD (f_r2) = f_r2;
-  FLD (i_src1) = & CPU (h_gr)[f_r1];
-  FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_src1) = f_r1;
-      FLD (in_src2) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_sc:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
-
-
-  /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_clrpsw:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_setpsw:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-    UINT f_uimm8;
-
-    f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
-
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_bset:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-    INT f_simm16;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_sfmt_btst:
-  {
-    const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_bset.f
-    UINT f_uimm3;
-    UINT f_r2;
-
-    f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
-    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_r2) = f_r2;
-  FLD (f_uimm3) = f_uimm3;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
-}
diff --git a/sim/m32r/decodex.h b/sim/m32r/decodex.h
deleted file mode 100644
index e8de9a8..0000000
--- a/sim/m32r/decodex.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* Decode header for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifndef M32RXF_DECODE_H
-#define M32RXF_DECODE_H
-
-extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
-                                  ARGBUF *);
-extern void m32rxf_init_idesc_table (SIM_CPU *);
-extern void m32rxf_sem_init_idesc_table (SIM_CPU *);
-extern void m32rxf_semf_init_idesc_table (SIM_CPU *);
-
-/* Enum declaration for instructions in cpu family m32rxf.  */
-typedef enum m32rxf_insn_type {
-  M32RXF_INSN_X_INVALID, M32RXF_INSN_X_AFTER, M32RXF_INSN_X_BEFORE, M32RXF_INSN_X_CTI_CHAIN
- , M32RXF_INSN_X_CHAIN, M32RXF_INSN_X_BEGIN, M32RXF_INSN_ADD, M32RXF_INSN_ADD3
- , M32RXF_INSN_AND, M32RXF_INSN_AND3, M32RXF_INSN_OR, M32RXF_INSN_OR3
- , M32RXF_INSN_XOR, M32RXF_INSN_XOR3, M32RXF_INSN_ADDI, M32RXF_INSN_ADDV
- , M32RXF_INSN_ADDV3, M32RXF_INSN_ADDX, M32RXF_INSN_BC8, M32RXF_INSN_BC24
- , M32RXF_INSN_BEQ, M32RXF_INSN_BEQZ, M32RXF_INSN_BGEZ, M32RXF_INSN_BGTZ
- , M32RXF_INSN_BLEZ, M32RXF_INSN_BLTZ, M32RXF_INSN_BNEZ, M32RXF_INSN_BL8
- , M32RXF_INSN_BL24, M32RXF_INSN_BCL8, M32RXF_INSN_BCL24, M32RXF_INSN_BNC8
- , M32RXF_INSN_BNC24, M32RXF_INSN_BNE, M32RXF_INSN_BRA8, M32RXF_INSN_BRA24
- , M32RXF_INSN_BNCL8, M32RXF_INSN_BNCL24, M32RXF_INSN_CMP, M32RXF_INSN_CMPI
- , M32RXF_INSN_CMPU, M32RXF_INSN_CMPUI, M32RXF_INSN_CMPEQ, M32RXF_INSN_CMPZ
- , M32RXF_INSN_DIV, M32RXF_INSN_DIVU, M32RXF_INSN_REM, M32RXF_INSN_REMU
- , M32RXF_INSN_DIVH, M32RXF_INSN_JC, M32RXF_INSN_JNC, M32RXF_INSN_JL
- , M32RXF_INSN_JMP, M32RXF_INSN_LD, M32RXF_INSN_LD_D, M32RXF_INSN_LDB
- , M32RXF_INSN_LDB_D, M32RXF_INSN_LDH, M32RXF_INSN_LDH_D, M32RXF_INSN_LDUB
- , M32RXF_INSN_LDUB_D, M32RXF_INSN_LDUH, M32RXF_INSN_LDUH_D, M32RXF_INSN_LD_PLUS
- , M32RXF_INSN_LD24, M32RXF_INSN_LDI8, M32RXF_INSN_LDI16, M32RXF_INSN_LOCK
- , M32RXF_INSN_MACHI_A, M32RXF_INSN_MACLO_A, M32RXF_INSN_MACWHI_A, M32RXF_INSN_MACWLO_A
- , M32RXF_INSN_MUL, M32RXF_INSN_MULHI_A, M32RXF_INSN_MULLO_A, M32RXF_INSN_MULWHI_A
- , M32RXF_INSN_MULWLO_A, M32RXF_INSN_MV, M32RXF_INSN_MVFACHI_A, M32RXF_INSN_MVFACLO_A
- , M32RXF_INSN_MVFACMI_A, M32RXF_INSN_MVFC, M32RXF_INSN_MVTACHI_A, M32RXF_INSN_MVTACLO_A
- , M32RXF_INSN_MVTC, M32RXF_INSN_NEG, M32RXF_INSN_NOP, M32RXF_INSN_NOT
- , M32RXF_INSN_RAC_DSI, M32RXF_INSN_RACH_DSI, M32RXF_INSN_RTE, M32RXF_INSN_SETH
- , M32RXF_INSN_SLL, M32RXF_INSN_SLL3, M32RXF_INSN_SLLI, M32RXF_INSN_SRA
- , M32RXF_INSN_SRA3, M32RXF_INSN_SRAI, M32RXF_INSN_SRL, M32RXF_INSN_SRL3
- , M32RXF_INSN_SRLI, M32RXF_INSN_ST, M32RXF_INSN_ST_D, M32RXF_INSN_STB
- , M32RXF_INSN_STB_D, M32RXF_INSN_STH, M32RXF_INSN_STH_D, M32RXF_INSN_ST_PLUS
- , M32RXF_INSN_STH_PLUS, M32RXF_INSN_STB_PLUS, M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB
- , M32RXF_INSN_SUBV, M32RXF_INSN_SUBX, M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK
- , M32RXF_INSN_SATB, M32RXF_INSN_SATH, M32RXF_INSN_SAT, M32RXF_INSN_PCMPBZ
- , M32RXF_INSN_SADD, M32RXF_INSN_MACWU1, M32RXF_INSN_MSBLO, M32RXF_INSN_MULWU1
- , M32RXF_INSN_MACLH1, M32RXF_INSN_SC, M32RXF_INSN_SNC, M32RXF_INSN_CLRPSW
- , M32RXF_INSN_SETPSW, M32RXF_INSN_BSET, M32RXF_INSN_BCLR, M32RXF_INSN_BTST
- , M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND
- , M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR
- , M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV
- , M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8
- , M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8
- , M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8
- , M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP
- , M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ
- , M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC
- , M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL
- , M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD
- , M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH
- , M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH
- , M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8
- , M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A
- , M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A
- , M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL
- , M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A
- , M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A
- , M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A
- , M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A
- , M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A
- , M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC
- , M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP
- , M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI
- , M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE
- , M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI
- , M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI
- , M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI
- , M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB
- , M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS
- , M32RXF_INSN_PAR_STH_PLUS, M32RXF_INSN_WRITE_STH_PLUS, M32RXF_INSN_PAR_STB_PLUS, M32RXF_INSN_WRITE_STB_PLUS
- , M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB
- , M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX
- , M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK
- , M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD
- , M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO
- , M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1
- , M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC
- , M32RXF_INSN_PAR_CLRPSW, M32RXF_INSN_WRITE_CLRPSW, M32RXF_INSN_PAR_SETPSW, M32RXF_INSN_WRITE_SETPSW
- , M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST, M32RXF_INSN__MAX
-} M32RXF_INSN_TYPE;
-
-/* Enum declaration for semantic formats in cpu family m32rxf.  */
-typedef enum m32rxf_sfmt_type {
-  M32RXF_SFMT_EMPTY, M32RXF_SFMT_ADD, M32RXF_SFMT_ADD3, M32RXF_SFMT_AND3
- , M32RXF_SFMT_OR3, M32RXF_SFMT_ADDI, M32RXF_SFMT_ADDV, M32RXF_SFMT_ADDV3
- , M32RXF_SFMT_ADDX, M32RXF_SFMT_BC8, M32RXF_SFMT_BC24, M32RXF_SFMT_BEQ
- , M32RXF_SFMT_BEQZ, M32RXF_SFMT_BL8, M32RXF_SFMT_BL24, M32RXF_SFMT_BCL8
- , M32RXF_SFMT_BCL24, M32RXF_SFMT_BRA8, M32RXF_SFMT_BRA24, M32RXF_SFMT_CMP
- , M32RXF_SFMT_CMPI, M32RXF_SFMT_CMPZ, M32RXF_SFMT_DIV, M32RXF_SFMT_JC
- , M32RXF_SFMT_JL, M32RXF_SFMT_JMP, M32RXF_SFMT_LD, M32RXF_SFMT_LD_D
- , M32RXF_SFMT_LDB, M32RXF_SFMT_LDB_D, M32RXF_SFMT_LDH, M32RXF_SFMT_LDH_D
- , M32RXF_SFMT_LD_PLUS, M32RXF_SFMT_LD24, M32RXF_SFMT_LDI8, M32RXF_SFMT_LDI16
- , M32RXF_SFMT_LOCK, M32RXF_SFMT_MACHI_A, M32RXF_SFMT_MULHI_A, M32RXF_SFMT_MV
- , M32RXF_SFMT_MVFACHI_A, M32RXF_SFMT_MVFC, M32RXF_SFMT_MVTACHI_A, M32RXF_SFMT_MVTC
- , M32RXF_SFMT_NOP, M32RXF_SFMT_RAC_DSI, M32RXF_SFMT_RTE, M32RXF_SFMT_SETH
- , M32RXF_SFMT_SLL3, M32RXF_SFMT_SLLI, M32RXF_SFMT_ST, M32RXF_SFMT_ST_D
- , M32RXF_SFMT_STB, M32RXF_SFMT_STB_D, M32RXF_SFMT_STH, M32RXF_SFMT_STH_D
- , M32RXF_SFMT_ST_PLUS, M32RXF_SFMT_STH_PLUS, M32RXF_SFMT_STB_PLUS, M32RXF_SFMT_TRAP
- , M32RXF_SFMT_UNLOCK, M32RXF_SFMT_SATB, M32RXF_SFMT_SAT, M32RXF_SFMT_SADD
- , M32RXF_SFMT_MACWU1, M32RXF_SFMT_MSBLO, M32RXF_SFMT_MULWU1, M32RXF_SFMT_SC
- , M32RXF_SFMT_CLRPSW, M32RXF_SFMT_SETPSW, M32RXF_SFMT_BSET, M32RXF_SFMT_BTST
-} M32RXF_SFMT_TYPE;
-
-/* Function unit handlers (user written).  */
-
-extern int m32rxf_model_m32rx_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
-extern int m32rxf_model_m32rx_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
-extern int m32rxf_model_m32rx_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
-extern int m32rxf_model_m32rx_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
-
-/* Profiling before/after handlers (user written) */
-
-extern void m32rxf_model_insn_before (SIM_CPU *, int /*first_p*/);
-extern void m32rxf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
-
-#endif /* M32RXF_DECODE_H */
diff --git a/sim/m32r/devices.c b/sim/m32r/devices.c
deleted file mode 100644
index 032c8e7..0000000
--- a/sim/m32r/devices.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* m32r device support
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-
-#ifdef HAVE_DV_SOCKSER
-#include "dv-sockser.h"
-#endif
-
-/* Handling the MSPR register is done by creating a device in the core
-   mapping that winds up here.  */
-
-device m32r_devices;
-
-int
-device_io_read_buffer (device *me, void *source, int space,
-		       address_word addr, unsigned nr_bytes,
-		       SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
-{
-  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
-    return nr_bytes;
-
-#ifdef HAVE_DV_SOCKSER
-  if (addr == UART_INCHAR_ADDR)
-    {
-      int c = dv_sockser_read (sd);
-      if (c == -1)
-	return 0;
-      *(char *) source = c;
-      return 1;
-    }
-  if (addr == UART_STATUS_ADDR)
-    {
-      int status = dv_sockser_status (sd);
-      unsigned char *p = source;
-      p[0] = 0;
-      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
-#ifdef UART_INPUT_READY0
-	       ? UART_INPUT_READY : 0)
-#else
-	       ? 0 : UART_INPUT_READY)
-#endif
-	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
-      return 2;
-    }
-#endif
-
-  return nr_bytes;
-}
-
-int
-device_io_write_buffer (device *me, const void *source, int space,
-			address_word addr, unsigned nr_bytes,
-			SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
-{
-#if WITH_SCACHE
-  /* MSPR support is deprecated but is kept in for upward compatibility
-     with existing overlay support.  */
-  if (addr == MSPR_ADDR)
-    {
-      if ((*(const char *) source & MSPR_PURGE) != 0)
-	scache_flush (sd);
-      return nr_bytes;
-    }
-  if (addr == MCCR_ADDR)
-    {
-      if ((*(const char *) source & MCCR_CP) != 0)
-	scache_flush (sd);
-      return nr_bytes;
-    }
-#endif
-
-  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
-    return nr_bytes;
-
-#ifdef HAVE_DV_SOCKSER
-  if (addr == UART_OUTCHAR_ADDR)
-    {
-      int rc = dv_sockser_write (sd, *(char *) source);
-      return rc == 1;
-    }
-#endif
-
-  return nr_bytes;
-}
-
-void
-device_error (device *me, char *message, ...)
-{
-}
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
deleted file mode 100644
index 100274d..0000000
--- a/sim/m32r/m32r-sim.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* collection of junk waiting time to sort out
-   Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef M32R_SIM_H
-#define M32R_SIM_H
-
-/* GDB register numbers.  */
-#define PSW_REGNUM	16
-#define CBR_REGNUM	17
-#define SPI_REGNUM	18
-#define SPU_REGNUM	19
-#define BPC_REGNUM	20
-#define PC_REGNUM	21
-#define ACCL_REGNUM	22
-#define ACCH_REGNUM	23
-#define ACC1L_REGNUM	24
-#define ACC1H_REGNUM	25
-#define BBPSW_REGNUM	26
-#define BBPC_REGNUM	27
-#define EVB_REGNUM	28
-
-extern int m32r_decode_gdb_ctrl_regnum (int);
-
-/* Cover macros for hardware accesses.
-   FIXME: Eventually move to cgen.  */
-#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
-
-#ifndef GET_H_CR
-extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
-extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
-
-#define GET_H_CR(regno) \
-  XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
-#define SET_H_CR(regno, val) \
-  XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
-#endif
-
-#ifndef  GET_H_PSW
-extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
-extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
-
-#define GET_H_PSW() \
-  XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
-#define SET_H_PSW(val) \
-  XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
-#endif
-
-#ifndef  GET_H_ACCUM
-extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
-extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
-
-#define GET_H_ACCUM() \
-  XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
-#define SET_H_ACCUM(val) \
-  XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
-#endif
-
-/* Misc. profile data.  */
-
-typedef struct {
-  /* nop insn slot filler count */
-  unsigned int fillnop_count;
-  /* number of parallel insns */
-  unsigned int parallel_count;
-
-  /* FIXME: generalize this to handle all insn lengths, move to common.  */
-  /* number of short insns, not including parallel ones */
-  unsigned int short_count;
-  /* number of long insns */
-  unsigned int long_count;
-
-  /* Working area for computing cycle counts.  */
-  unsigned long insn_cycles; /* FIXME: delete */
-  unsigned long cti_stall;
-  unsigned long load_stall;
-  unsigned long biggest_cycles;
-
-  /* Bitmask of registers loaded by previous insn.  */
-  unsigned int load_regs;
-  /* Bitmask of registers loaded by current insn.  */
-  unsigned int load_regs_pending;
-} M32R_MISC_PROFILE;
-
-/* Initialize the working area.  */
-void m32r_init_insn_cycles (SIM_CPU *, int);
-/* Update the totals for the insn.  */
-void m32r_record_insn_cycles (SIM_CPU *, int);
-
-/* This is invoked by the nop pattern in the .cpu file.  */
-#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
-do { \
-  if (PROFILE_INSN_P (cpu) \
-      && (addr & 3) != 0) \
-    ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_PARINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_SHORTINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
-} while (0)
-
-/* This is invoked by the execute section of mloop{,x}.in.  */
-#define PROFILE_COUNT_LONGINSNS(cpu) \
-do { \
-  if (PROFILE_INSN_P (cpu)) \
-    ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
-} while (0)
-
-#define GETTWI GETTSI
-#define SETTWI SETTSI
-
-/* Additional execution support.  */
-
-
-/* Hardware/device support.
-   ??? Will eventually want to move device stuff to config files.  */
-
-/* Exception, Interrupt, and Trap addresses */
-#define EIT_SYSBREAK_ADDR	0x10
-#define EIT_RSVD_INSN_ADDR	0x20
-#define EIT_ADDR_EXCP_ADDR	0x30
-#define EIT_TRAP_BASE_ADDR	0x40
-#define EIT_EXTERN_ADDR		0x80
-#define EIT_RESET_ADDR		0x7ffffff0
-#define EIT_WAKEUP_ADDR		0x7ffffff0
-
-/* Special purpose traps.  */
-#define TRAP_SYSCALL	0
-#define TRAP_BREAKPOINT	1
-
-/* Support for the MSPR register (Cache Purge Control Register)
-   and the MCCR register (Cache Control Register) are needed in order for
-   overlays to work correctly with the scache.
-   MSPR no longer exists but is supported for upward compatibility with
-   early overlay support.  */
-
-/* Cache Purge Control (only exists on early versions of chips) */
-#define MSPR_ADDR 0xfffffff7
-#define MSPR_PURGE 1
-
-/* Lock Control Register (not supported) */
-#define MLCR_ADDR 0xfffffff7
-#define MLCR_LM 1
-
-/* Power Management Control Register (not supported) */
-#define MPMR_ADDR 0xfffffffb
-
-/* Cache Control Register */
-#define MCCR_ADDR 0xffffffff
-#define MCCR_CP 0x80
-/* not supported */
-#define MCCR_CM0 2
-#define MCCR_CM1 1
-
-/* Serial device addresses.  */
-#ifdef M32R_EVA /* orig eva board, no longer supported */
-#define UART_INCHAR_ADDR	0xff102013
-#define UART_OUTCHAR_ADDR	0xff10200f
-#define UART_STATUS_ADDR	0xff102006
-/* Indicate ready bit is inverted.  */
-#define UART_INPUT_READY0
-#else
-/* These are the values for the MSA2000 board.
-   ??? Will eventually need to move this to a config file.  */
-#define UART_INCHAR_ADDR	0xff004009
-#define UART_OUTCHAR_ADDR	0xff004007
-#define UART_STATUS_ADDR	0xff004002
-#endif
-
-#define UART_INPUT_READY	0x4
-#define UART_OUTPUT_READY	0x1
-
-/* Start address and length of all device support.  */
-#define M32R_DEVICE_ADDR	0xff000000
-#define M32R_DEVICE_LEN		0x00ffffff
-
-/* sim_core_attach device argument.  */
-extern device m32r_devices;
-
-/* FIXME: Temporary, until device support ready.  */
-struct _device { int foo; };
-
-/* Handle the trap insn.  */
-USI m32r_trap (SIM_CPU *, PCADDR, int);
-
-#endif /* M32R_SIM_H */
diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c
deleted file mode 100644
index 8e9c75e..0000000
--- a/sim/m32r/m32r.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* m32r simulator support code
-   Copyright (C) 1996, 1997, 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-/* Decode gdb ctrl register number.  */
-
-int
-m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
-{
-  switch (gdb_regnum)
-    {
-      case PSW_REGNUM : return H_CR_PSW;
-      case CBR_REGNUM : return H_CR_CBR;
-      case SPI_REGNUM : return H_CR_SPI;
-      case SPU_REGNUM : return H_CR_SPU;
-      case BPC_REGNUM : return H_CR_BPC;
-      case BBPSW_REGNUM : return H_CR_BBPSW;
-      case BBPC_REGNUM : return H_CR_BBPC;
-      case EVB_REGNUM : return H_CR_CR5;
-    }
-  abort ();
-}
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  if (rn < 16)
-    SETTWI (buf, m32rbf_h_gr_get (current_cpu, rn));
-  else
-    switch (rn)
-      {
-      case PSW_REGNUM :
-      case CBR_REGNUM :
-      case SPI_REGNUM :
-      case SPU_REGNUM :
-      case BPC_REGNUM :
-      case BBPSW_REGNUM :
-      case BBPC_REGNUM :
-	SETTWI (buf, m32rbf_h_cr_get (current_cpu,
-				      m32r_decode_gdb_ctrl_regnum (rn)));
-	break;
-      case PC_REGNUM :
-	SETTWI (buf, m32rbf_h_pc_get (current_cpu));
-	break;
-      case ACCL_REGNUM :
-	SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
-	break;
-      case ACCH_REGNUM :
-	SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
-	break;
-      default :
-	return 0;
-      }
-
-  return -1; /*FIXME*/
-}
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  if (rn < 16)
-    m32rbf_h_gr_set (current_cpu, rn, GETTWI (buf));
-  else
-    switch (rn)
-      {
-      case PSW_REGNUM :
-      case CBR_REGNUM :
-      case SPI_REGNUM :
-      case SPU_REGNUM :
-      case BPC_REGNUM :
-      case BBPSW_REGNUM :
-      case BBPC_REGNUM :
-	m32rbf_h_cr_set (current_cpu,
-			 m32r_decode_gdb_ctrl_regnum (rn),
-			 GETTWI (buf));
-	break;
-      case PC_REGNUM :
-	m32rbf_h_pc_set (current_cpu, GETTWI (buf));
-	break;
-      case ACCL_REGNUM :
-	{
-	  DI val = m32rbf_h_accum_get (current_cpu);
-	  SETLODI (val, GETTWI (buf));
-	  m32rbf_h_accum_set (current_cpu, val);
-	  break;
-	}
-      case ACCH_REGNUM :
-	{
-	  DI val = m32rbf_h_accum_get (current_cpu);
-	  SETHIDI (val, GETTWI (buf));
-	  m32rbf_h_accum_set (current_cpu, val);
-	  break;
-	}
-      default :
-	return 0;
-      }
-
-  return -1; /*FIXME*/
-}
-
-USI
-m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* psw */
-      return (((CPU (h_bpsw) & 0xc1) << 8)
-	      | ((CPU (h_psw) & 0xc0) << 0)
-	      | GET_H_COND ());
-    case H_CR_BBPSW : /* backup backup psw */
-      return CPU (h_bbpsw) & 0xc1;
-    case H_CR_CBR : /* condition bit */
-      return GET_H_COND ();
-    case H_CR_SPI : /* interrupt stack pointer */
-      if (! GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPI]);
-    case H_CR_SPU : /* user stack pointer */
-      if (GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPU]);
-    case H_CR_BPC : /* backup pc */
-      return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
-    case H_CR_BBPC : /* backup backup pc */
-      return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      return CPU (h_cr[cr]);
-    default :
-      return 0;
-    }
-}
-
-void
-m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* psw */
-      {
-	int old_sm = (CPU (h_psw) & 0x80) != 0;
-	int new_sm = (newval & 0x80) != 0;
-	CPU (h_bpsw) = (newval >> 8) & 0xff;
-	CPU (h_psw) = newval & 0xff;
-	SET_H_COND (newval & 1);
-	/* When switching stack modes, update the registers.  */
-	if (old_sm != new_sm)
-	  {
-	    if (old_sm)
-	      {
-		/* Switching user -> system.  */
-		CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
-	      }
-	    else
-	      {
-		/* Switching system -> user.  */
-		CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
-	      }
-	  }
-	break;
-      }
-    case H_CR_BBPSW : /* backup backup psw */
-      CPU (h_bbpsw) = newval & 0xff;
-      break;
-    case H_CR_CBR : /* condition bit */
-      SET_H_COND (newval & 1);
-      break;
-    case H_CR_SPI : /* interrupt stack pointer */
-      if (! GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPI]) = newval;
-      break;
-    case H_CR_SPU : /* user stack pointer */
-      if (GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPU]) = newval;
-      break;
-    case H_CR_BPC : /* backup pc */
-      CPU (h_cr[H_CR_BPC]) = newval;
-      break;
-    case H_CR_BBPC : /* backup backup pc */
-      CPU (h_cr[H_CR_BBPC]) = newval;
-      break;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      CPU (h_cr[cr]) = newval;
-      break;
-    default :
-      /* ignore */
-      break;
-    }
-}
-
-/* Cover fns to access h-psw.  */
-
-UQI
-m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
-{
-  return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
-}
-
-void
-m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_psw) = newval;
-  CPU (h_cond) = newval & 1;
-}
-
-/* Cover fns to access h-accum.  */
-
-DI
-m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
-{
-  /* Sign extend the top 8 bits.  */
-  DI r;
-#if 1
-  r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
-  r = XORDI (r, MAKEDI (0x800000, 0));
-  r = SUBDI (r, MAKEDI (0x800000, 0));
-#else
-  SI hi,lo;
-  r = CPU (h_accum);
-  hi = GETHIDI (r);
-  lo = GETLODI (r);
-  hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
-  r = MAKEDI (hi, lo);
-#endif
-  return r;
-}
-
-void
-m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
-{
-  CPU (h_accum) = newval;
-}
-
-#if WITH_PROFILE_MODEL_P
-
-/* FIXME: Some of these should be inline or macros.  Later.  */
-
-/* Initialize cycle counting for an insn.
-   FIRST_P is non-zero if this is the first insn in a set of parallel
-   insns.  */
-
-void
-m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
-{
-  M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
-  mp->cti_stall = 0;
-  mp->load_stall = 0;
-  if (first_p)
-    {
-      mp->load_regs_pending = 0;
-      mp->biggest_cycles = 0;
-    }
-}
-
-/* Record the cycles computed for an insn.
-   LAST_P is non-zero if this is the last insn in a set of parallel insns,
-   and we update the total cycle count.
-   CYCLES is the cycle count of the insn.  */
-
-void
-m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
-{
-  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
-  M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
-  unsigned long total = cycles + mp->cti_stall + mp->load_stall;
-
-  if (last_p)
-    {
-      unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
-      PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
-      PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
-    }
-  else
-    {
-      /* Here we take advantage of the fact that !last_p -> first_p.  */
-      mp->biggest_cycles = total;
-      PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
-    }
-
-  /* Branch and load stall counts are recorded independently of the
-     total cycle count.  */
-  PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
-  PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
-
-  mp->load_regs = mp->load_regs_pending;
-}
-
-static INLINE void
-check_load_stall (SIM_CPU *cpu, int regno)
-{
-  UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
-
-  if (regno != -1
-      && (h_gr & (1 << regno)) != 0)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
-      if (TRACE_INSN_P (cpu))
-	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
-    }
-}
-
-int
-m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
-			    int unit_num, int referenced,
-			    INT sr, INT sr2, INT dr)
-{
-  check_load_stall (cpu, sr);
-  check_load_stall (cpu, sr2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT sr)
-{
-  PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
-  int taken_p = (referenced & (1 << 1)) != 0;
-
-  check_load_stall (cpu, sr);
-  if (taken_p)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
-      PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
-    }
-  else
-    PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
-			    int unit_num, int referenced,
-			    INT sr, INT dr)
-{
-  CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
-  check_load_stall (cpu, sr);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
-			     int unit_num, int referenced,
-			     INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
-			  int unit_num, int referenced)
-{
-  return idesc->timing->units[unit_num].done;
-}
-
-#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
deleted file mode 100644
index 594ce8a..0000000
--- a/sim/m32r/m32r2.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* m32r2 simulator support code
-   Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU m32r2f
-#define WANT_CPU_M32R2F
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  return m32rbf_fetch_register (current_cpu, rn, buf, len);
-}
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  return m32rbf_store_register (current_cpu, rn, buf, len);
-}
-
-/* Cover fns to get/set the control registers.
-   FIXME: Duplicated from m32r.c.  The issue is structure offsets.  */
-
-USI
-m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* PSW.  */
-      return (((CPU (h_bpsw) & 0xc1) << 8)
-	      | ((CPU (h_psw) & 0xc0) << 0)
-	      | GET_H_COND ());
-    case H_CR_BBPSW : /* Backup backup psw.  */
-      return CPU (h_bbpsw) & 0xc1;
-    case H_CR_CBR : /* Condition bit.  */
-      return GET_H_COND ();
-    case H_CR_SPI : /* Interrupt stack pointer.  */
-      if (! GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPI]);
-    case H_CR_SPU : /* User stack pointer.  */
-      if (GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPU]);
-    case H_CR_BPC : /* Backup pc.  */
-      return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
-    case H_CR_BBPC : /* Backup backup pc.  */
-      return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      return CPU (h_cr[cr]);
-    default :
-      return 0;
-    }
-}
-
-void
-m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* psw */
-      {
-	int old_sm = (CPU (h_psw) & 0x80) != 0;
-	int new_sm = (newval & 0x80) != 0;
-	CPU (h_bpsw) = (newval >> 8) & 0xff;
-	CPU (h_psw) = newval & 0xff;
-	SET_H_COND (newval & 1);
-	/* When switching stack modes, update the registers.  */
-	if (old_sm != new_sm)
-	  {
-	    if (old_sm)
-	      {
-		/* Switching user -> system.  */
-		CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
-	      }
-	    else
-	      {
-		/* Switching system -> user.  */
-		CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
-	      }
-	  }
-	break;
-      }
-    case H_CR_BBPSW : /* backup backup psw */
-      CPU (h_bbpsw) = newval & 0xff;
-      break;
-    case H_CR_CBR : /* condition bit */
-      SET_H_COND (newval & 1);
-      break;
-    case H_CR_SPI : /* interrupt stack pointer */
-      if (! GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPI]) = newval;
-      break;
-    case H_CR_SPU : /* user stack pointer */
-      if (GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPU]) = newval;
-      break;
-    case H_CR_BPC : /* backup pc */
-      CPU (h_cr[H_CR_BPC]) = newval;
-      break;
-    case H_CR_BBPC : /* backup backup pc */
-      CPU (h_cr[H_CR_BBPC]) = newval;
-      break;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      CPU (h_cr[cr]) = newval;
-      break;
-    default :
-      /* ignore */
-      break;
-    }
-}
-
-/* Cover fns to access h-psw.  */
-
-UQI
-m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
-{
-  return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
-}
-
-void
-m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_psw) = newval;
-  CPU (h_cond) = newval & 1;
-}
-
-/* Cover fns to access h-accum.  */
-
-DI
-m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
-{
-  /* Sign extend the top 8 bits.  */
-  DI r;
-  r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
-  r = XORDI (r, MAKEDI (0x800000, 0));
-  r = SUBDI (r, MAKEDI (0x800000, 0));
-  return r;
-}
-
-void
-m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
-{
-  CPU (h_accum) = newval;
-}
-
-/* Cover fns to access h-accums.  */
-
-DI
-m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
-{
-  /* FIXME: Yes, this is just a quick hack.  */
-  DI r;
-  if (regno == 0)
-    r = CPU (h_accum);
-  else
-    r = CPU (h_accums[1]);
-  /* Sign extend the top 8 bits.  */
-  r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
-  r = XORDI (r, MAKEDI (0x800000, 0));
-  r = SUBDI (r, MAKEDI (0x800000, 0));
-  return r;
-}
-
-void
-m32r2f_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  /* FIXME: Yes, this is just a quick hack.  */
-  if (regno == 0)
-    CPU (h_accum) = newval;
-  else
-    CPU (h_accums[1]) = newval;
-}
-
-#if WITH_PROFILE_MODEL_P
-
-/* Initialize cycle counting for an insn.
-   FIRST_P is non-zero if this is the first insn in a set of parallel
-   insns.  */
-
-void
-m32r2f_model_insn_before (SIM_CPU *cpu, int first_p)
-{
-  m32rbf_model_insn_before (cpu, first_p);
-}
-
-/* Record the cycles computed for an insn.
-   LAST_P is non-zero if this is the last insn in a set of parallel insns,
-   and we update the total cycle count.
-   CYCLES is the cycle count of the insn.  */
-
-void
-m32r2f_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
-{
-  m32rbf_model_insn_after (cpu, last_p, cycles);
-}
-
-static INLINE void
-check_load_stall (SIM_CPU *cpu, int regno)
-{
-  UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
-
-  if (regno != -1
-      && (h_gr & (1 << regno)) != 0)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
-      if (TRACE_INSN_P (cpu))
-	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
-    }
-}
-
-int
-m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT sr, INT sr2, INT dr)
-{
-  check_load_stall (cpu, sr);
-  check_load_stall (cpu, sr2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
-			  int unit_num, int referenced,
-			  INT sr)
-{
-  PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
-  int taken_p = (referenced & (1 << 1)) != 0;
-
-  check_load_stall (cpu, sr);
-  if (taken_p)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
-      PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
-    }
-  else
-    PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT sr, INT dr)
-{
-  CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
-			    int unit_num, int referenced,
-			    INT src1, INT src2)
-{
-  return idesc->timing->units[unit_num].done;
-}
-
-#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
deleted file mode 100644
index cb319f6..0000000
--- a/sim/m32r/m32rx.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* m32rx simulator support code
-   Copyright (C) 1997, 1998 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  return m32rbf_fetch_register (current_cpu, rn, buf, len);
-}
-
-/* The contents of BUF are in target byte order.  */
-
-int
-m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
-{
-  return m32rbf_store_register (current_cpu, rn, buf, len);
-}
-
-/* Cover fns to get/set the control registers.
-   FIXME: Duplicated from m32r.c.  The issue is structure offsets.  */
-
-USI
-m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* psw */
-      return (((CPU (h_bpsw) & 0xc1) << 8)
-	      | ((CPU (h_psw) & 0xc0) << 0)
-	      | GET_H_COND ());
-    case H_CR_BBPSW : /* backup backup psw */
-      return CPU (h_bbpsw) & 0xc1;
-    case H_CR_CBR : /* condition bit */
-      return GET_H_COND ();
-    case H_CR_SPI : /* interrupt stack pointer */
-      if (! GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPI]);
-    case H_CR_SPU : /* user stack pointer */
-      if (GET_H_SM ())
-	return CPU (h_gr[H_GR_SP]);
-      else
-	return CPU (h_cr[H_CR_SPU]);
-    case H_CR_BPC : /* backup pc */
-      return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
-    case H_CR_BBPC : /* backup backup pc */
-      return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      return CPU (h_cr[cr]);
-    default :
-      return 0;
-    }
-}
-
-void
-m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
-{
-  switch (cr)
-    {
-    case H_CR_PSW : /* psw */
-      {
-	int old_sm = (CPU (h_psw) & 0x80) != 0;
-	int new_sm = (newval & 0x80) != 0;
-	CPU (h_bpsw) = (newval >> 8) & 0xff;
-	CPU (h_psw) = newval & 0xff;
-	SET_H_COND (newval & 1);
-	/* When switching stack modes, update the registers.  */
-	if (old_sm != new_sm)
-	  {
-	    if (old_sm)
-	      {
-		/* Switching user -> system.  */
-		CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
-	      }
-	    else
-	      {
-		/* Switching system -> user.  */
-		CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
-		CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
-	      }
-	  }
-	break;
-      }
-    case H_CR_BBPSW : /* backup backup psw */
-      CPU (h_bbpsw) = newval & 0xff;
-      break;
-    case H_CR_CBR : /* condition bit */
-      SET_H_COND (newval & 1);
-      break;
-    case H_CR_SPI : /* interrupt stack pointer */
-      if (! GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPI]) = newval;
-      break;
-    case H_CR_SPU : /* user stack pointer */
-      if (GET_H_SM ())
-	CPU (h_gr[H_GR_SP]) = newval;
-      else
-	CPU (h_cr[H_CR_SPU]) = newval;
-      break;
-    case H_CR_BPC : /* backup pc */
-      CPU (h_cr[H_CR_BPC]) = newval;
-      break;
-    case H_CR_BBPC : /* backup backup pc */
-      CPU (h_cr[H_CR_BBPC]) = newval;
-      break;
-    case 4 : /* ??? unspecified, but apparently available */
-    case 5 : /* ??? unspecified, but apparently available */
-      CPU (h_cr[cr]) = newval;
-      break;
-    default :
-      /* ignore */
-      break;
-    }
-}
-
-/* Cover fns to access h-psw.  */
-
-UQI
-m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
-{
-  return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
-}
-
-void
-m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
-{
-  CPU (h_psw) = newval;
-  CPU (h_cond) = newval & 1;
-}
-
-/* Cover fns to access h-accum.  */
-
-DI
-m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
-{
-  /* Sign extend the top 8 bits.  */
-  DI r;
-  r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
-  r = XORDI (r, MAKEDI (0x800000, 0));
-  r = SUBDI (r, MAKEDI (0x800000, 0));
-  return r;
-}
-
-void
-m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
-{
-  CPU (h_accum) = newval;
-}
-
-/* Cover fns to access h-accums.  */
-
-DI
-m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
-{
-  /* FIXME: Yes, this is just a quick hack.  */
-  DI r;
-  if (regno == 0)
-    r = CPU (h_accum);
-  else
-    r = CPU (h_accums[1]);
-  /* Sign extend the top 8 bits.  */
-  r = ANDDI (r, MAKEDI (0xffffff, 0xffffffff));
-  r = XORDI (r, MAKEDI (0x800000, 0));
-  r = SUBDI (r, MAKEDI (0x800000, 0));
-  return r;
-}
-
-void
-m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
-{
-  /* FIXME: Yes, this is just a quick hack.  */
-  if (regno == 0)
-    CPU (h_accum) = newval;
-  else
-    CPU (h_accums[1]) = newval;
-}
-
-#if WITH_PROFILE_MODEL_P
-
-/* Initialize cycle counting for an insn.
-   FIRST_P is non-zero if this is the first insn in a set of parallel
-   insns.  */
-
-void
-m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
-{
-  m32rbf_model_insn_before (cpu, first_p);
-}
-
-/* Record the cycles computed for an insn.
-   LAST_P is non-zero if this is the last insn in a set of parallel insns,
-   and we update the total cycle count.
-   CYCLES is the cycle count of the insn.  */
-
-void
-m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
-{
-  m32rbf_model_insn_after (cpu, last_p, cycles);
-}
-
-static INLINE void
-check_load_stall (SIM_CPU *cpu, int regno)
-{
-  UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
-
-  if (regno != -1
-      && (h_gr & (1 << regno)) != 0)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
-      if (TRACE_INSN_P (cpu))
-	cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
-    }
-}
-
-int
-m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT sr, INT sr2, INT dr)
-{
-  check_load_stall (cpu, sr);
-  check_load_stall (cpu, sr2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT src1, INT src2)
-{
-  check_load_stall (cpu, src1);
-  check_load_stall (cpu, src2);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
-			  int unit_num, int referenced,
-			  INT sr)
-{
-  PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
-  int taken_p = (referenced & (1 << 1)) != 0;
-
-  check_load_stall (cpu, sr);
-  if (taken_p)
-    {
-      CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
-      PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
-    }
-  else
-    PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
-			   int unit_num, int referenced,
-			   INT sr, INT dr)
-{
-  CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
-  return idesc->timing->units[unit_num].done;
-}
-
-int
-m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
-			    int unit_num, int referenced,
-			    INT src1, INT src2)
-{
-  return idesc->timing->units[unit_num].done;
-}
-
-#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/m32r/mloop.in b/sim/m32r/mloop.in
deleted file mode 100644
index 0be16bb..0000000
--- a/sim/m32r/mloop.in
+++ /dev/null
@@ -1,319 +0,0 @@
-# Simulator main loop for m32r. -*- C -*-
-# Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
-#
-# This file is part of the GNU Simulators.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Syntax:
-# /bin/sh mainloop.in command
-#
-# Command is one of:
-#
-# init
-# support
-# extract-{simple,scache,pbb}
-# {full,fast}-exec-{simple,scache,pbb}
-#
-# A target need only provide a "full" version of one of simple,scache,pbb.
-# If the target wants it can also provide a fast version of same, or if
-# the slow (full featured) version is `simple', then the fast version can be
-# one of scache/pbb.
-# A target can't provide more than this.
-# However for illustration's sake this file provides examples of all.
-
-# ??? After a few more ports are done, revisit.
-# Will eventually need to machine generate a lot of this.
-
-case "x$1" in
-
-xsupport)
-
-cat <<EOF
-
-static INLINE const IDESC *
-extract16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	   ARGBUF *abuf, int fast_p)
-{
-  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
-
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  if (! fast_p)
-    {
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
-    }
-  return id;
-}
-
-static INLINE const IDESC *
-extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	   ARGBUF *abuf, int fast_p)
-{
-  const IDESC *id = @cpu@_decode (current_cpu, pc, (USI) insn >> 16, insn, abuf);
-
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  if (! fast_p)
-    {
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
-    }
-  return id;
-}
-
-static INLINE SEM_PC
-execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
-{
-  SEM_PC vpc;
-
-  if (fast_p)
-    {
-#if ! WITH_SEM_SWITCH_FAST
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
-#endif
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FAST */
-    }
-  else
-    {
-#if ! WITH_SEM_SWITCH_FULL
-      ARGBUF *abuf = &sc->argbuf;
-      const IDESC *idesc = abuf->idesc;
-      const CGEN_INSN *idata = idesc->idata;
-#if WITH_SCACHE_PBB
-      int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
-#else
-      int virtual_p = 0;
-#endif
-
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-before */
-	  if (ARGBUF_PROFILE_P (abuf))
-	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
-	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
-	  TRACE_INSN_INIT (current_cpu, abuf, 1);
-	  TRACE_INSN (current_cpu, idata,
-		      (const struct argbuf *) abuf, abuf->addr);
-	}
-#if WITH_SCACHE
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
-#else
-      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
-#endif
-      if (! virtual_p)
-	{
-	  /* FIXME: call x-after */
-	  if (PROFILE_MODEL_P (current_cpu)
-	      && ARGBUF_PROFILE_P (abuf))
-	    {
-	      int cycles;
-
-	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
-	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
-	    }
-	  TRACE_INSN_FINI (current_cpu, abuf, 1);
-	}
-#else
-      abort ();
-#endif /* WITH_SEM_SWITCH_FULL */
-    }
-
-  return vpc;
-}
-
-EOF
-
-;;
-
-xinit)
-
-# Nothing needed.
-
-;;
-
-xextract-simple | xextract-scache)
-
-cat <<EOF
-{
-  if ((pc & 3) != 0)
-    {
-      /* This only occurs when single stepping.
-	 The test is unnecessary otherwise, but the cost is teensy,
-	 compared with decoding/extraction.  */
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
-    }
-  else
-    {
-      USI insn = GETIMEMUSI (current_cpu, pc);
-      if ((SI) insn < 0)
-	{
-	  extract32 (current_cpu, pc, insn, sc, FAST_P);
-	}
-      else
-	{
-	  extract16 (current_cpu, pc, insn >> 16, sc, FAST_P);
-	  extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P);
-	  /* The m32r doesn't support parallel execution.  */
-	  if ((insn & 0x8000) != 0
-	      && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
-	    sim_engine_illegal_insn (current_cpu, pc);
-	}
-    }
-}
-EOF
-
-;;
-
-xextract-pbb)
-
-# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
-# Outputs: sc, pc
-# sc must be left pointing past the last created entry.
-# pc must be left pointing past the last created entry.
-# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
-# to record the vpc of the cti insn.
-# SET_INSN_COUNT(n) must be called to record number of real insns.
-
-cat <<EOF
-{
-  const IDESC *idesc;
-  int icount = 0;
-
-  if ((pc & 3) != 0)
-    {
-      /* This only occurs when single stepping.
-	 The test is unnecessary otherwise, but the cost is teensy,
-	 compared with decoding/extraction.  */
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
-      ++sc;
-      --max_insns;
-      ++icount;
-      pc += 2;
-      if (IDESC_CTI_P (idesc))
-	{
-	  SET_CTI_VPC (sc - 1);
-	  goto Finish;
-	}
-    }
-
-  while (max_insns > 0)
-    {
-      USI insn = GETIMEMUSI (current_cpu, pc);
-      if ((SI) insn < 0)
-	{
-	  idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
-	  ++sc;
-	  --max_insns;
-	  ++icount;
-	  pc += 4;
-	  if (IDESC_CTI_P (idesc))
-	    {
-	      SET_CTI_VPC (sc - 1);
-	      break;
-	    }
-	}
-      else
-	{
-	  idesc = extract16 (current_cpu, pc, insn >> 16, &sc->argbuf, FAST_P);
-	  ++sc;
-	  --max_insns;
-	  ++icount;
-	  pc += 2;
-	  if (IDESC_CTI_P (idesc))
-	    {
-	      SET_CTI_VPC (sc - 1);
-	      break;
-	    }
-	  /* The m32r doesn't support parallel execution.  */
-	  if ((insn & 0x8000) != 0)
-	    {
-	      /* ??? Defer signalling to execution.  */
-	      if ((insn & 0x7fff) != 0x7000) /* parallel nops are ok */
-		sim_engine_invalid_insn (current_cpu, pc - 2, 0);
-	      /* There's no point in processing parallel nops in fast mode.
-		 We might as well do this test since we've already tested
-		 that we have a parallel nop.  */
-	      if (0 && FAST_P)
-		{
-		  pc += 2;
-		  continue;
-		}
-	    }
-	  else
-	    {
-	      /* Non-parallel case.
-		 While we're guaranteed that there's room to extract the
-		 insn, when single stepping we can't; the pbb must stop
-		 after the first insn.  */
-	      if (max_insns == 0)
-		break;
-	    }
-	  /* We're guaranteed that we can always process 16 bit insns in
-	     pairs.  */
-	  idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
-	  ++sc;
-	  --max_insns;
-	  ++icount;
-	  pc += 2;
-	  if (IDESC_CTI_P (idesc))
-	    {
-	      SET_CTI_VPC (sc - 1);
-	      break;
-	    }
-	}
-    }
-
- Finish:
-  SET_INSN_COUNT (icount);
-}
-EOF
-
-;;
-
-xfull-exec-* | xfast-exec-*)
-
-# Inputs: current_cpu, vpc, FAST_P
-# Outputs: vpc
-# vpc is the virtual program counter.
-
-cat <<EOF
-#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
-#define DEFINE_SWITCH
-#include "sem-switch.c"
-#else
-  vpc = execute (current_cpu, vpc, FAST_P);
-#endif
-EOF
-
-;;
-
-*)
-  echo "Invalid argument to mainloop.in: $1" >&2
-  exit 1
-  ;;
-
-esac
diff --git a/sim/m32r/mloop2.in b/sim/m32r/mloop2.in
deleted file mode 100644
index 69c6ec7..0000000
--- a/sim/m32r/mloop2.in
+++ /dev/null
@@ -1,536 +0,0 @@
-# Simulator main loop for m32r2. -*- C -*-
-#
-# Copyright 1996, 1997, 1998, 2003, 2004 Free Software Foundation, Inc.
-#
-# This file is part of GDB, the GNU debugger.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Syntax:
-# /bin/sh mainloop.in command
-#
-# Command is one of:
-#
-# init
-# support
-# extract-{simple,scache,pbb}
-# {full,fast}-exec-{simple,scache,pbb}
-#
-# A target need only provide a "full" version of one of simple,scache,pbb.
-# If the target wants it can also provide a fast version of same, or if
-# the slow (full featured) version is `simple', then the fast version can be
-# one of scache/pbb.
-# A target can't provide more than this.
-
-# ??? After a few more ports are done, revisit.
-# Will eventually need to machine generate a lot of this.
-
-case "x$1" in
-
-xsupport)
-
-cat <<EOF
-
-/* Emit insns to write back the results of insns executed in parallel.
-   SC points to a sufficient number of scache entries for the writeback
-   handlers.
-   SC1/ID1 is the first insn (left slot, lower address).
-   SC2/ID2 is the second insn (right slot, higher address).  */
-
-static INLINE void
-emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
-		 SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
-{
-  ARGBUF *abuf;
-
-  abuf = &sc->argbuf;
-  id1 = id1->par_idesc;
-  abuf->fields.write.abuf = &sc1->argbuf;
-  @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
-  /* no need to set trace_p,profile_p */
-#if 0 /* not currently needed for id2 since results written directly */
-  abuf = &sc[1].argbuf;
-  id2 = id2->par_idesc;
-  abuf->fields.write.abuf = &sc2->argbuf;
-  @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
-  /* no need to set trace_p,profile_p */
-#endif
-}
-
-static INLINE const IDESC *
-emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	 SCACHE *sc, int fast_p, int parallel_p)
-{
-  ARGBUF *abuf = &sc->argbuf;
-  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
-
-  if (parallel_p)
-    id = id->par_idesc;
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
-	     int trace_p, int profile_p)
-{
-  const IDESC *id;
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-  id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
-  @cpu@_emit_after (current_cpu, sc + 2, pc);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-  return id;
-}
-
-static INLINE const IDESC *
-emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	       SCACHE *sc, int fast_p)
-{
-  const IDESC *id,*id2;
-
-  /* Emit both insns, then emit a finisher-upper.
-     We speed things up by handling the second insn serially
-     [not parallelly].  Then the writeback only has to deal
-     with the first insn.  */
-  /* ??? Revisit to handle exceptions right.  */
-
-  /* FIXME: No need to handle this parallely if second is nop.  */
-  id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
-
-  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
-  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
-
-  /* Set sc/snc insns notion of where to skip to.  */
-  if (IDESC_SKIP_P (id))
-    SEM_SKIP_COMPILE (current_cpu, sc, 1);
-
-  /* Emit code to finish executing the semantics
-     (write back the results).  */
-  emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
-
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-		    SCACHE *sc, int trace_p, int profile_p)
-{
-  const IDESC *id,*id2;
-
-  /* Emit both insns, then emit a finisher-upper.
-     We speed things up by handling the second insn serially
-     [not parallelly].  Then the writeback only has to deal
-     with the first insn.  */
-  /* ??? Revisit to handle exceptions right.  */
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-
-  /* FIXME: No need to handle this parallelly if second is nop.  */
-  id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-
-  @cpu@_emit_before (current_cpu, sc + 2, pc, 0);
-
-  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
-  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
-  sc[3].argbuf.trace_p = trace_p;
-  sc[3].argbuf.profile_p = profile_p;
-
-  /* Set sc/snc insns notion of where to skip to.  */
-  if (IDESC_SKIP_P (id))
-    SEM_SKIP_COMPILE (current_cpu, sc, 4);
-
-  /* Emit code to finish executing the semantics
-     (write back the results).  */
-  emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
-
-  @cpu@_emit_after (current_cpu, sc + 5, pc);
-
-  return id;
-}
-
-static INLINE const IDESC *
-emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	 SCACHE *sc, int fast_p)
-{
-  ARGBUF *abuf = &sc->argbuf;
-  const IDESC *id = @cpu@_decode (current_cpu, pc,
-				  (USI) insn >> 16, insn, abuf);
-
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
-	     int trace_p, int profile_p)
-{
-  const IDESC *id;
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-  id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
-  @cpu@_emit_after (current_cpu, sc + 2, pc);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-  return id;
-}
-
-EOF
-
-;;
-
-xinit)
-
-# Nothing needed.
-
-;;
-
-xextract-pbb)
-
-# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
-# Outputs: sc, pc
-# sc must be left pointing past the last created entry.
-# pc must be left pointing past the last created entry.
-# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
-# to record the vpc of the cti insn.
-# SET_INSN_COUNT(n) must be called to record number of real insns.
-
-cat <<EOF
-{
-  const IDESC *idesc;
-  int icount = 0;
-
-  if ((pc & 3) != 0)
-    {
-      /* This occurs when single stepping and when compiling the not-taken
-	 part of conditional branches.  */
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      SCACHE *cti_sc; /* ??? tmp hack */
-
-      /* A parallel insn isn't allowed here, but we don't mind nops.
-	 ??? We need to wait until the insn is executed before signalling
-	 the error, for situations where such signalling is wanted.  */
-#if 0
-      if ((insn & 0x8000) != 0
-	  && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
-	sim_engine_invalid_insn (current_cpu, pc, 0);
-#endif
-
-      /* Only emit before/after handlers if necessary.  */
-      if (FAST_P || (! trace_p && ! profile_p))
-	{
-	  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
-	  cti_sc = sc;
-	  ++sc;
-	  --max_insns;
-	}
-      else
-	{
-	  idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
-			       trace_p, profile_p);
-	  cti_sc = sc + 1;
-	  sc += 3;
-	  max_insns -= 3;
-	}
-      ++icount;
-      pc += 2;
-      if (IDESC_CTI_P (idesc))
-	{
-	  SET_CTI_VPC (cti_sc);
-	  goto Finish;
-	}
-    }
-
-  /* There are two copies of the compiler: full(!fast) and fast.
-     The "full" case emits before/after handlers for each insn.
-     Having two copies of this code is a tradeoff, having one copy
-     seemed a bit more difficult to read (due to constantly testing
-     FAST_P).  ??? On the other hand, with address ranges we'll want to
-     omit before/after handlers for unwanted insns.  Having separate loops
-     for FAST/!FAST avoids constantly doing the test in the loop, but
-     typically FAST_P is a constant and such tests will get optimized out.  */
-
-  if (FAST_P)
-    {
-      while (max_insns > 0)
-	{
-	  USI insn = GETIMEMUSI (current_cpu, pc);
-	  if ((SI) insn < 0)
-	    {
-	      /* 32 bit insn */
-	      idesc = emit_32 (current_cpu, pc, insn, sc, 1);
-	      ++sc;
-	      --max_insns;
-	      ++icount;
-	      pc += 4;
-	      if (IDESC_CTI_P (idesc))
-		{
-		  SET_CTI_VPC (sc - 1);
-		  break;
-		}
-	    }
-	  else
-	    {
-	      if ((insn & 0x8000) != 0) /* parallel? */
-		{
-                  int up_count;
-
-		  if (((insn >> 16) & 0xfff0) == 0x10f0)
-		    {
-		      /* FIXME: No need to handle this sequentially if system
-		         calls will be able to execute after second insn in
-		         parallel. ( trap #num || insn ) */
-		      /* insn */
-		      idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
-				       sc, 1, 0);
-		      /* trap */
-		      emit_16 (current_cpu, pc, insn >> 16, sc + 1, 1, 0);
-                      up_count = 2;
-		    }
-		  else
-		    {
-		      /* Yep.  Here's the "interesting" [sic] part.  */
-		      idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
-                      up_count = 3;
-		    }
-		  sc += up_count;
-		  max_insns -= up_count;
-		  icount += 2;
-		  pc += 4;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - up_count);
-		      break;
-		    }
-		}
-	      else /* 2 serial 16 bit insns */
-		{
-		  idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
-		  ++sc;
-		  --max_insns;
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - 1);
-		      break;
-		    }
-		  /* While we're guaranteed that there's room to extract the
-		     insn, when single stepping we can't; the pbb must stop
-		     after the first insn.  */
-		  if (max_insns == 0)
-		    break;
-		  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
-		  ++sc;
-		  --max_insns;
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - 1);
-		      break;
-		    }
-		}
-	    }
-	}
-    }
-  else /* ! FAST_P */
-    {
-      while (max_insns > 0)
-	{
-	  USI insn = GETIMEMUSI (current_cpu, pc);
-	  int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-	  int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-	  SCACHE *cti_sc; /* ??? tmp hack */
-	  if ((SI) insn < 0)
-	    {
-	      /* 32 bit insn
-		 Only emit before/after handlers if necessary.  */
-	      if (trace_p || profile_p)
-		{
-		  idesc = emit_full32 (current_cpu, pc, insn, sc,
-				       trace_p, profile_p);
-		  cti_sc = sc + 1;
-		  sc += 3;
-		  max_insns -= 3;
-		}
-	      else
-		{
-		  idesc = emit_32 (current_cpu, pc, insn, sc, 0);
-		  cti_sc = sc;
-		  ++sc;
-		  --max_insns;
-		}
-	      ++icount;
-	      pc += 4;
-	      if (IDESC_CTI_P (idesc))
-		{
-		  SET_CTI_VPC (cti_sc);
-		  break;
-		}
-	    }
-	  else
-	    {
-	      if ((insn & 0x8000) != 0) /* parallel? */
-		{
-		  /* Yep.  Here's the "interesting" [sic] part.
-		     Only emit before/after handlers if necessary.  */
-		  if (trace_p || profile_p)
-		    {
-		      if (((insn >> 16) & 0xfff0) == 0x10f0)
-		        {
-		          /* FIXME: No need to handle this sequentially if
-			     system calls will be able to execute after second
-			     insn in parallel. ( trap #num || insn ) */
-		          /* insn */
-			  idesc = emit_full16 (current_cpu, pc + 2,
-					       insn & 0x7fff, sc, 0, 0);
-		          /* trap */
-			  emit_full16 (current_cpu, pc, insn >> 16, sc + 3,
-				       0, 0);
-		        }
-		      else
-		        {
-		          idesc = emit_full_parallel (current_cpu, pc, insn,
-						      sc, trace_p, profile_p);
-		        }
-		      cti_sc = sc + 1;
-		      sc += 6;
-		      max_insns -= 6;
-		    }
-		  else
-		    {
-                      int up_count;
-
-		      if (((insn >> 16) & 0xfff0) == 0x10f0)
-		        {
-		          /* FIXME: No need to handle this sequentially if
-			     system calls will be able to execute after second
-			     insn in parallel. ( trap #num || insn ) */
-		          /* insn */
-		          idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
-				           sc, 0, 0);
-		          /* trap */
-		          emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 0);
-                          up_count = 2;
-		        }
-		      else
-		        {
-		          idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
-                          up_count = 3;
-		        }
-		      cti_sc = sc;
-		      sc += up_count;
-		      max_insns -= up_count;
-		    }
-		  icount += 2;
-		  pc += 4;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		}
-	      else /* 2 serial 16 bit insns */
-		{
-		  /* Only emit before/after handlers if necessary.  */
-		  if (trace_p || profile_p)
-		    {
-		      idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
-					   trace_p, profile_p);
-		      cti_sc = sc + 1;
-		      sc += 3;
-		      max_insns -= 3;
-		    }
-		  else
-		    {
-		      idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
-		      cti_sc = sc;
-		      ++sc;
-		      --max_insns;
-		    }
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		  /* While we're guaranteed that there's room to extract the
-		     insn, when single stepping we can't; the pbb must stop
-		     after the first insn.  */
-		  if (max_insns <= 0)
-		    break;
-		  /* Use the same trace/profile address for the 2nd insn.
-		     Saves us having to compute it and they come in pairs
-		     anyway (e.g. can never branch to the 2nd insn).  */
-		  if (trace_p || profile_p)
-		    {
-		      idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
-					   trace_p, profile_p);
-		      cti_sc = sc + 1;
-		      sc += 3;
-		      max_insns -= 3;
-		    }
-		  else
-		    {
-		      idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
-		      cti_sc = sc;
-		      ++sc;
-		      --max_insns;
-		    }
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		}
-	    }
-	}
-    }
-
- Finish:
-  SET_INSN_COUNT (icount);
-}
-EOF
-
-;;
-
-xfull-exec-pbb)
-
-# Inputs: current_cpu, vpc, FAST_P
-# Outputs: vpc
-# vpc is the virtual program counter.
-
-cat <<EOF
-#define DEFINE_SWITCH
-#include "sem2-switch.c"
-EOF
-
-;;
-
-*)
-  echo "Invalid argument to mainloop.in: $1" >&2
-  exit 1
-  ;;
-
-esac
diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in
deleted file mode 100644
index 5ca20a1..0000000
--- a/sim/m32r/mloopx.in
+++ /dev/null
@@ -1,536 +0,0 @@
-# Simulator main loop for m32rx. -*- C -*-
-#
-# Copyright 1996, 1997, 1998, 2004 Free Software Foundation, Inc.
-#
-# This file is part of the GNU Simulators.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Syntax:
-# /bin/sh mainloop.in command
-#
-# Command is one of:
-#
-# init
-# support
-# extract-{simple,scache,pbb}
-# {full,fast}-exec-{simple,scache,pbb}
-#
-# A target need only provide a "full" version of one of simple,scache,pbb.
-# If the target wants it can also provide a fast version of same, or if
-# the slow (full featured) version is `simple', then the fast version can be
-# one of scache/pbb.
-# A target can't provide more than this.
-
-# ??? After a few more ports are done, revisit.
-# Will eventually need to machine generate a lot of this.
-
-case "x$1" in
-
-xsupport)
-
-cat <<EOF
-
-/* Emit insns to write back the results of insns executed in parallel.
-   SC points to a sufficient number of scache entries for the writeback
-   handlers.
-   SC1/ID1 is the first insn (left slot, lower address).
-   SC2/ID2 is the second insn (right slot, higher address).  */
-
-static INLINE void
-emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
-		 SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
-{
-  ARGBUF *abuf;
-
-  abuf = &sc->argbuf;
-  id1 = id1->par_idesc;
-  abuf->fields.write.abuf = &sc1->argbuf;
-  @cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
-  /* no need to set trace_p,profile_p */
-#if 0 /* not currently needed for id2 since results written directly */
-  abuf = &sc[1].argbuf;
-  id2 = id2->par_idesc;
-  abuf->fields.write.abuf = &sc2->argbuf;
-  @cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
-  /* no need to set trace_p,profile_p */
-#endif
-}
-
-static INLINE const IDESC *
-emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	 SCACHE *sc, int fast_p, int parallel_p)
-{
-  ARGBUF *abuf = &sc->argbuf;
-  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
-
-  if (parallel_p)
-    id = id->par_idesc;
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
-	     int trace_p, int profile_p)
-{
-  const IDESC *id;
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-  id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
-  @cpu@_emit_after (current_cpu, sc + 2, pc);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-  return id;
-}
-
-static INLINE const IDESC *
-emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	       SCACHE *sc, int fast_p)
-{
-  const IDESC *id,*id2;
-
-  /* Emit both insns, then emit a finisher-upper.
-     We speed things up by handling the second insn serially
-     [not parallelly].  Then the writeback only has to deal
-     with the first insn.  */
-  /* ??? Revisit to handle exceptions right.  */
-
-  /* FIXME: No need to handle this parallely if second is nop.  */
-  id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
-
-  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
-  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
-
-  /* Set sc/snc insns notion of where to skip to.  */
-  if (IDESC_SKIP_P (id))
-    SEM_SKIP_COMPILE (current_cpu, sc, 1);
-
-  /* Emit code to finish executing the semantics
-     (write back the results).  */
-  emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
-
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-		    SCACHE *sc, int trace_p, int profile_p)
-{
-  const IDESC *id,*id2;
-
-  /* Emit both insns, then emit a finisher-upper.
-     We speed things up by handling the second insn serially
-     [not parallelly].  Then the writeback only has to deal
-     with the first insn.  */
-  /* ??? Revisit to handle exceptions right.  */
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-
-  /* FIXME: No need to handle this parallelly if second is nop.  */
-  id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-
-  @cpu@_emit_before (current_cpu, sc + 2, pc, 0);
-
-  /* Note that this can never be a cti.  No cti's go in the S pipeline.  */
-  id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
-  sc[3].argbuf.trace_p = trace_p;
-  sc[3].argbuf.profile_p = profile_p;
-
-  /* Set sc/snc insns notion of where to skip to.  */
-  if (IDESC_SKIP_P (id))
-    SEM_SKIP_COMPILE (current_cpu, sc, 4);
-
-  /* Emit code to finish executing the semantics
-     (write back the results).  */
-  emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
-
-  @cpu@_emit_after (current_cpu, sc + 5, pc);
-
-  return id;
-}
-
-static INLINE const IDESC *
-emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
-	 SCACHE *sc, int fast_p)
-{
-  ARGBUF *abuf = &sc->argbuf;
-  const IDESC *id = @cpu@_decode (current_cpu, pc,
-				  (USI) insn >> 16, insn, abuf);
-
-  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
-  return id;
-}
-
-static INLINE const IDESC *
-emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
-	     int trace_p, int profile_p)
-{
-  const IDESC *id;
-
-  @cpu@_emit_before (current_cpu, sc, pc, 1);
-  id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
-  @cpu@_emit_after (current_cpu, sc + 2, pc);
-  sc[1].argbuf.trace_p = trace_p;
-  sc[1].argbuf.profile_p = profile_p;
-  return id;
-}
-
-EOF
-
-;;
-
-xinit)
-
-# Nothing needed.
-
-;;
-
-xextract-pbb)
-
-# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
-# Outputs: sc, pc
-# sc must be left pointing past the last created entry.
-# pc must be left pointing past the last created entry.
-# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
-# to record the vpc of the cti insn.
-# SET_INSN_COUNT(n) must be called to record number of real insns.
-
-cat <<EOF
-{
-  const IDESC *idesc;
-  int icount = 0;
-
-  if ((pc & 3) != 0)
-    {
-      /* This occurs when single stepping and when compiling the not-taken
-	 part of conditional branches.  */
-      UHI insn = GETIMEMUHI (current_cpu, pc);
-      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-      SCACHE *cti_sc; /* ??? tmp hack */
-
-      /* A parallel insn isn't allowed here, but we don't mind nops.
-	 ??? We need to wait until the insn is executed before signalling
-	 the error, for situations where such signalling is wanted.  */
-#if 0
-      if ((insn & 0x8000) != 0
-	  && (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
-	sim_engine_invalid_insn (current_cpu, pc, 0);
-#endif
-
-      /* Only emit before/after handlers if necessary.  */
-      if (FAST_P || (! trace_p && ! profile_p))
-	{
-	  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
-	  cti_sc = sc;
-	  ++sc;
-	  --max_insns;
-	}
-      else
-	{
-	  idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
-			       trace_p, profile_p);
-	  cti_sc = sc + 1;
-	  sc += 3;
-	  max_insns -= 3;
-	}
-      ++icount;
-      pc += 2;
-      if (IDESC_CTI_P (idesc))
-	{
-	  SET_CTI_VPC (cti_sc);
-	  goto Finish;
-	}
-    }
-
-  /* There are two copies of the compiler: full(!fast) and fast.
-     The "full" case emits before/after handlers for each insn.
-     Having two copies of this code is a tradeoff, having one copy
-     seemed a bit more difficult to read (due to constantly testing
-     FAST_P).  ??? On the other hand, with address ranges we'll want to
-     omit before/after handlers for unwanted insns.  Having separate loops
-     for FAST/!FAST avoids constantly doing the test in the loop, but
-     typically FAST_P is a constant and such tests will get optimized out.  */
-
-  if (FAST_P)
-    {
-      while (max_insns > 0)
-	{
-	  USI insn = GETIMEMUSI (current_cpu, pc);
-	  if ((SI) insn < 0)
-	    {
-	      /* 32 bit insn */
-	      idesc = emit_32 (current_cpu, pc, insn, sc, 1);
-	      ++sc;
-	      --max_insns;
-	      ++icount;
-	      pc += 4;
-	      if (IDESC_CTI_P (idesc))
-		{
-		  SET_CTI_VPC (sc - 1);
-		  break;
-		}
-	    }
-	  else
-	    {
-	      if ((insn & 0x8000) != 0) /* parallel? */
-		{
-		  int up_count;
-
-		  if (((insn >> 16) & 0xfff0) == 0x10f0)
-		    {
-		      /* FIXME: No need to handle this sequentially if system
-		         calls will be able to execute after second insn in
-		         parallel. ( trap #num || insn ) */
-		      /* insn */
-		      idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
- 				       sc, 1, 0);
-		      /* trap */
-		      emit_16 (current_cpu, pc, insn >> 16, sc + 1, 1, 0);
-		      up_count = 2;
-		    }
-		  else
-		    {
-		      /* Yep.  Here's the "interesting" [sic] part.  */
-		      idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
-		      up_count = 3;
-		    }
-		  sc += up_count;
-		  max_insns -= up_count;
-		  icount += 2;
-		  pc += 4;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - up_count);
-		      break;
-		    }
-		}
-	      else /* 2 serial 16 bit insns */
-		{
-		  idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
-		  ++sc;
-		  --max_insns;
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - 1);
-		      break;
-		    }
-		  /* While we're guaranteed that there's room to extract the
-		     insn, when single stepping we can't; the pbb must stop
-		     after the first insn.  */
-		  if (max_insns == 0)
-		    break;
-		  idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
-		  ++sc;
-		  --max_insns;
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (sc - 1);
-		      break;
-		    }
-		}
-	    }
-	}
-    }
-  else /* ! FAST_P */
-    {
-      while (max_insns > 0)
-	{
-	  USI insn = GETIMEMUSI (current_cpu, pc);
-	  int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
-	  int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
-	  SCACHE *cti_sc; /* ??? tmp hack */
-	  if ((SI) insn < 0)
-	    {
-	      /* 32 bit insn
-		 Only emit before/after handlers if necessary.  */
-	      if (trace_p || profile_p)
-		{
-		  idesc = emit_full32 (current_cpu, pc, insn, sc,
-				       trace_p, profile_p);
-		  cti_sc = sc + 1;
-		  sc += 3;
-		  max_insns -= 3;
-		}
-	      else
-		{
-		  idesc = emit_32 (current_cpu, pc, insn, sc, 0);
-		  cti_sc = sc;
-		  ++sc;
-		  --max_insns;
-		}
-	      ++icount;
-	      pc += 4;
-	      if (IDESC_CTI_P (idesc))
-		{
-		  SET_CTI_VPC (cti_sc);
-		  break;
-		}
-	    }
-	  else
-	    {
-	      if ((insn & 0x8000) != 0) /* parallel? */
-		{
-		  /* Yep.  Here's the "interesting" [sic] part.
-		     Only emit before/after handlers if necessary.  */
-		  if (trace_p || profile_p)
-		    {
-		      if (((insn >> 16) & 0xfff0) == 0x10f0)
-			{
-			  /* FIXME: No need to handle this sequentially if
-			     system calls will be able to execute after second
-			     insn in parallel. ( trap #num || insn ) */
-			  /* insn */
-			  idesc = emit_full16 (current_cpu, pc + 2,
-					       insn & 0x7fff, sc, 0, 0);
-			  /* trap */
-			  emit_full16 (current_cpu, pc, insn >> 16, sc + 3,
-				       0, 0);
-			}
-		      else
-			{
-		          idesc = emit_full_parallel (current_cpu, pc, insn,
-						      sc, trace_p, profile_p);
-			}
-		      cti_sc = sc + 1;
-		      sc += 6;
-		      max_insns -= 6;
-		    }
-		  else
-		    {
-		      int up_count;
-
-		      if (((insn >> 16) & 0xfff0) == 0x10f0)
-			{
-                          /* FIXME: No need to handle this sequentially if
-                             system calls will be able to execute after second
-                             insn in parallel. ( trap #num || insn ) */
-                          /* insn */
-                          idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
-                                           sc, 0, 0);
-                          /* trap */
-                          emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 0);
-                          up_count = 2;
-			}
-		      else
-			{
-		          idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
-                          up_count = 3;
-			}
-		      cti_sc = sc;
-		      sc += up_count;
-		      max_insns -= up_count;
-		    }
-		  icount += 2;
-		  pc += 4;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		}
-	      else /* 2 serial 16 bit insns */
-		{
-		  /* Only emit before/after handlers if necessary.  */
-		  if (trace_p || profile_p)
-		    {
-		      idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
-					   trace_p, profile_p);
-		      cti_sc = sc + 1;
-		      sc += 3;
-		      max_insns -= 3;
-		    }
-		  else
-		    {
-		      idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
-		      cti_sc = sc;
-		      ++sc;
-		      --max_insns;
-		    }
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		  /* While we're guaranteed that there's room to extract the
-		     insn, when single stepping we can't; the pbb must stop
-		     after the first insn.  */
-		  if (max_insns <= 0)
-		    break;
-		  /* Use the same trace/profile address for the 2nd insn.
-		     Saves us having to compute it and they come in pairs
-		     anyway (e.g. can never branch to the 2nd insn).  */
-		  if (trace_p || profile_p)
-		    {
-		      idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
-					   trace_p, profile_p);
-		      cti_sc = sc + 1;
-		      sc += 3;
-		      max_insns -= 3;
-		    }
-		  else
-		    {
-		      idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
-		      cti_sc = sc;
-		      ++sc;
-		      --max_insns;
-		    }
-		  ++icount;
-		  pc += 2;
-		  if (IDESC_CTI_P (idesc))
-		    {
-		      SET_CTI_VPC (cti_sc);
-		      break;
-		    }
-		}
-	    }
-	}
-    }
-
- Finish:
-  SET_INSN_COUNT (icount);
-}
-EOF
-
-;;
-
-xfull-exec-pbb)
-
-# Inputs: current_cpu, vpc, FAST_P
-# Outputs: vpc
-# vpc is the virtual program counter.
-
-cat <<EOF
-#define DEFINE_SWITCH
-#include "semx-switch.c"
-EOF
-
-;;
-
-*)
-  echo "Invalid argument to mainloop.in: $1" >&2
-  exit 1
-  ;;
-
-esac
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
deleted file mode 100644
index c94e349..0000000
--- a/sim/m32r/model.c
+++ /dev/null
@@ -1,4359 +0,0 @@
-/* Simulator model support for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-
-/* The profiling data is recorded here, but is accessed via the profiling
-   mechanism.  After all, this is information for profiling.  */
-
-#if WITH_PROFILE_MODEL_P
-
-/* Model handlers for each insn.  */
-
-static int
-model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_sr);
-    out_dr = FLD (out_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_setpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bset (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_bclr (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r_d_btst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_setpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bset (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_bclr (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_test_btst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
-  }
-  return cycles;
-#undef FLD
-}
-
-/* We assume UNIT_NONE == 0 because the tables don't always terminate
-   entries with it.  */
-
-/* Model timing data for `m32r/d'.  */
-
-static const INSN_TIMING m32r_d_timing[] = {
-  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
-  { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
-  { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
-  { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
-  { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
-  { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
-  { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
-  { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
-  { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
-  { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
-  { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
-  { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
-  { M32RBF_INSN_CLRPSW, model_m32r_d_clrpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETPSW, model_m32r_d_setpsw, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BSET, model_m32r_d_bset, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BCLR, model_m32r_d_bclr, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BTST, model_m32r_d_btst, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
-};
-
-/* Model timing data for `test'.  */
-
-static const INSN_TIMING test_timing[] = {
-  { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_CLRPSW, model_test_clrpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_SETPSW, model_test_setpsw, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BSET, model_test_bset, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BCLR, model_test_bclr, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-  { M32RBF_INSN_BTST, model_test_btst, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
-};
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-static void
-m32r_d_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
-}
-
-static void
-test_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
-}
-
-#if WITH_PROFILE_MODEL_P
-#define TIMING_DATA(td) td
-#else
-#define TIMING_DATA(td) 0
-#endif
-
-static const MODEL m32r_models[] =
-{
-  { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
-  { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
-  { 0 }
-};
-
-/* The properties of this cpu's implementation.  */
-
-static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-
-static void
-m32rbf_prepare_run (SIM_CPU *cpu)
-{
-  if (CPU_IDESC (cpu) == NULL)
-    m32rbf_init_idesc_table (cpu);
-}
-
-static const CGEN_INSN *
-m32rbf_get_idata (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].idata;
-}
-
-static void
-m32r_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
-  CPU_REG_STORE (cpu) = m32rbf_store_register;
-  CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
-  CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
-  CPU_GET_IDATA (cpu) = m32rbf_get_idata;
-  CPU_MAX_INSNS (cpu) = M32RBF_INSN__MAX;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
-#endif
-}
-
-const MACH m32r_mach =
-{
-  "m32r", "m32r", MACH_M32R,
-  32, 32, & m32r_models[0], & m32rbf_imp_properties,
-  m32r_init_cpu,
-  m32rbf_prepare_run
-};
-
diff --git a/sim/m32r/model2.c b/sim/m32r/model2.c
deleted file mode 100644
index 7328ea4..0000000
--- a/sim/m32r/model2.c
+++ /dev/null
@@ -1,3253 +0,0 @@
-/* Simulator model support for m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32r2f
-#define WANT_CPU_M32R2F
-
-#include "sim-main.h"
-
-/* The profiling data is recorded here, but is accessed via the profiling
-   mechanism.  After all, this is information for profiling.  */
-
-#if WITH_PROFILE_MODEL_P
-
-/* Model handlers for each insn.  */
-
-static int
-model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_sr);
-    out_dr = FLD (out_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-/* We assume UNIT_NONE == 0 because the tables don't always terminate
-   entries with it.  */
-
-/* Model timing data for `m32r2'.  */
-
-static const INSN_TIMING m32r2_timing[] = {
-  { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, { (int) UNIT_M32R2_U_CMP, 1, 0 } } },
-  { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
-  { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
-  { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
-  { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } } },
-  { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 } } },
-  { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },
-  { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
-  { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
-  { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
-  { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
-  { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 } } },
-  { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } } },
-  { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
-  { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
-  { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 2 } } },
-  { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
-  { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
-  { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
-  { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
-  { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } },
-  { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 } } },
-  { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STORE, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },
-  { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } },
-  { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } },
-  { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, 1 } } },
-  { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-  { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },
-};
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-static void
-m32r2_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R2_DATA));
-}
-
-#if WITH_PROFILE_MODEL_P
-#define TIMING_DATA(td) td
-#else
-#define TIMING_DATA(td) 0
-#endif
-
-static const MODEL m32r2_models[] =
-{
-  { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
-  { 0 }
-};
-
-/* The properties of this cpu's implementation.  */
-
-static const MACH_IMP_PROPERTIES m32r2f_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-
-static void
-m32r2f_prepare_run (SIM_CPU *cpu)
-{
-  if (CPU_IDESC (cpu) == NULL)
-    m32r2f_init_idesc_table (cpu);
-}
-
-static const CGEN_INSN *
-m32r2f_get_idata (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].idata;
-}
-
-static void
-m32r2_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = m32r2f_fetch_register;
-  CPU_REG_STORE (cpu) = m32r2f_store_register;
-  CPU_PC_FETCH (cpu) = m32r2f_h_pc_get;
-  CPU_PC_STORE (cpu) = m32r2f_h_pc_set;
-  CPU_GET_IDATA (cpu) = m32r2f_get_idata;
-  CPU_MAX_INSNS (cpu) = M32R2F_INSN__MAX;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = m32r2f_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = m32r2f_engine_run_full;
-#endif
-}
-
-const MACH m32r2_mach =
-{
-  "m32r2", "m32r2", MACH_M32R2,
-  32, 32, & m32r2_models[0], & m32r2f_imp_properties,
-  m32r2_init_cpu,
-  m32r2f_prepare_run
-};
-
diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c
deleted file mode 100644
index 8e0250c..0000000
--- a/sim/m32r/modelx.c
+++ /dev/null
@@ -1,3071 +0,0 @@
-/* Simulator model support for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rxf
-#define WANT_CPU_M32RXF
-
-#include "sim-main.h"
-
-/* The profiling data is recorded here, but is accessed via the profiling
-   mechanism.  After all, this is information for profiling.  */
-
-#if WITH_PROFILE_MODEL_P
-
-/* Model handlers for each insn.  */
-
-static int
-model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_sr);
-    out_dr = FLD (out_sr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_src1);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sth_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_stb_plus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = 0;
-    INT in_src2 = 0;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_dr = FLD (in_src2);
-    out_dr = FLD (out_src2);
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    in_dr = FLD (in_dr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_trap.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = 0;
-    INT out_dr = 0;
-    cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    out_dr = FLD (out_dr);
-    if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
-    referenced |= 1 << 2;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_src1 = -1;
-    INT in_src2 = -1;
-    in_src1 = FLD (in_src1);
-    in_src2 = FLD (in_src2);
-    referenced |= 1 << 0;
-    referenced |= 1 << 1;
-    cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_clrpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_setpsw (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bset (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_bclr (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-static int
-model_m32rx_btst (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
-  const IDESC * UNUSED idesc = abuf->idesc;
-  int cycles = 0;
-  {
-    int referenced = 0;
-    int UNUSED insn_referenced = abuf->written;
-    INT in_sr = -1;
-    INT in_dr = -1;
-    INT out_dr = -1;
-    in_sr = FLD (in_sr);
-    referenced |= 1 << 0;
-    cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
-  }
-  return cycles;
-#undef FLD
-}
-
-/* We assume UNIT_NONE == 0 because the tables don't always terminate
-   entries with it.  */
-
-/* Model timing data for `m32rx'.  */
-
-static const INSN_TIMING m32rx_timing[] = {
-  { M32RXF_INSN_X_INVALID, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_AFTER, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_BEFORE, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_CHAIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_X_BEGIN, 0, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
-  { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
-  { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
-  { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
-  { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
-  { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
-  { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
-  { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
-  { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
-  { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_STH_PLUS, model_m32rx_sth_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_STB_PLUS, model_m32rx_stb_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
-  { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
-  { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
-  { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
-  { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_CLRPSW, model_m32rx_clrpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_SETPSW, model_m32rx_setpsw, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_BSET, model_m32rx_bset, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_BCLR, model_m32rx_bclr, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-  { M32RXF_INSN_BTST, model_m32rx_btst, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
-};
-
-#endif /* WITH_PROFILE_MODEL_P */
-
-static void
-m32rx_model_init (SIM_CPU *cpu)
-{
-  CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
-}
-
-#if WITH_PROFILE_MODEL_P
-#define TIMING_DATA(td) td
-#else
-#define TIMING_DATA(td) 0
-#endif
-
-static const MODEL m32rx_models[] =
-{
-  { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
-  { 0 }
-};
-
-/* The properties of this cpu's implementation.  */
-
-static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
-{
-  sizeof (SIM_CPU),
-#if WITH_SCACHE
-  sizeof (SCACHE)
-#else
-  0
-#endif
-};
-
-
-static void
-m32rxf_prepare_run (SIM_CPU *cpu)
-{
-  if (CPU_IDESC (cpu) == NULL)
-    m32rxf_init_idesc_table (cpu);
-}
-
-static const CGEN_INSN *
-m32rxf_get_idata (SIM_CPU *cpu, int inum)
-{
-  return CPU_IDESC (cpu) [inum].idata;
-}
-
-static void
-m32rx_init_cpu (SIM_CPU *cpu)
-{
-  CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
-  CPU_REG_STORE (cpu) = m32rxf_store_register;
-  CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
-  CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
-  CPU_GET_IDATA (cpu) = m32rxf_get_idata;
-  CPU_MAX_INSNS (cpu) = M32RXF_INSN__MAX;
-  CPU_INSN_NAME (cpu) = cgen_insn_name;
-  CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
-#if WITH_FAST
-  CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
-#else
-  CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
-#endif
-}
-
-const MACH m32rx_mach =
-{
-  "m32rx", "m32rx", MACH_M32RX,
-  32, 32, & m32rx_models[0], & m32rxf_imp_properties,
-  m32rx_init_cpu,
-  m32rxf_prepare_run
-};
-
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
deleted file mode 100644
index b378010..0000000
--- a/sim/m32r/sem-switch.c
+++ /dev/null
@@ -1,2615 +0,0 @@
-/* Simulator instruction semantics for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { M32RBF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { M32RBF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { M32RBF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { M32RBF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { M32RBF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { M32RBF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { M32RBF_INSN_ADD, && case_sem_INSN_ADD },
-    { M32RBF_INSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32RBF_INSN_AND, && case_sem_INSN_AND },
-    { M32RBF_INSN_AND3, && case_sem_INSN_AND3 },
-    { M32RBF_INSN_OR, && case_sem_INSN_OR },
-    { M32RBF_INSN_OR3, && case_sem_INSN_OR3 },
-    { M32RBF_INSN_XOR, && case_sem_INSN_XOR },
-    { M32RBF_INSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32RBF_INSN_ADDI, && case_sem_INSN_ADDI },
-    { M32RBF_INSN_ADDV, && case_sem_INSN_ADDV },
-    { M32RBF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32RBF_INSN_ADDX, && case_sem_INSN_ADDX },
-    { M32RBF_INSN_BC8, && case_sem_INSN_BC8 },
-    { M32RBF_INSN_BC24, && case_sem_INSN_BC24 },
-    { M32RBF_INSN_BEQ, && case_sem_INSN_BEQ },
-    { M32RBF_INSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32RBF_INSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32RBF_INSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32RBF_INSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32RBF_INSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32RBF_INSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32RBF_INSN_BL8, && case_sem_INSN_BL8 },
-    { M32RBF_INSN_BL24, && case_sem_INSN_BL24 },
-    { M32RBF_INSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32RBF_INSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32RBF_INSN_BNE, && case_sem_INSN_BNE },
-    { M32RBF_INSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32RBF_INSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32RBF_INSN_CMP, && case_sem_INSN_CMP },
-    { M32RBF_INSN_CMPI, && case_sem_INSN_CMPI },
-    { M32RBF_INSN_CMPU, && case_sem_INSN_CMPU },
-    { M32RBF_INSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32RBF_INSN_DIV, && case_sem_INSN_DIV },
-    { M32RBF_INSN_DIVU, && case_sem_INSN_DIVU },
-    { M32RBF_INSN_REM, && case_sem_INSN_REM },
-    { M32RBF_INSN_REMU, && case_sem_INSN_REMU },
-    { M32RBF_INSN_JL, && case_sem_INSN_JL },
-    { M32RBF_INSN_JMP, && case_sem_INSN_JMP },
-    { M32RBF_INSN_LD, && case_sem_INSN_LD },
-    { M32RBF_INSN_LD_D, && case_sem_INSN_LD_D },
-    { M32RBF_INSN_LDB, && case_sem_INSN_LDB },
-    { M32RBF_INSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32RBF_INSN_LDH, && case_sem_INSN_LDH },
-    { M32RBF_INSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32RBF_INSN_LDUB, && case_sem_INSN_LDUB },
-    { M32RBF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32RBF_INSN_LDUH, && case_sem_INSN_LDUH },
-    { M32RBF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32RBF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32RBF_INSN_LD24, && case_sem_INSN_LD24 },
-    { M32RBF_INSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32RBF_INSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32RBF_INSN_LOCK, && case_sem_INSN_LOCK },
-    { M32RBF_INSN_MACHI, && case_sem_INSN_MACHI },
-    { M32RBF_INSN_MACLO, && case_sem_INSN_MACLO },
-    { M32RBF_INSN_MACWHI, && case_sem_INSN_MACWHI },
-    { M32RBF_INSN_MACWLO, && case_sem_INSN_MACWLO },
-    { M32RBF_INSN_MUL, && case_sem_INSN_MUL },
-    { M32RBF_INSN_MULHI, && case_sem_INSN_MULHI },
-    { M32RBF_INSN_MULLO, && case_sem_INSN_MULLO },
-    { M32RBF_INSN_MULWHI, && case_sem_INSN_MULWHI },
-    { M32RBF_INSN_MULWLO, && case_sem_INSN_MULWLO },
-    { M32RBF_INSN_MV, && case_sem_INSN_MV },
-    { M32RBF_INSN_MVFACHI, && case_sem_INSN_MVFACHI },
-    { M32RBF_INSN_MVFACLO, && case_sem_INSN_MVFACLO },
-    { M32RBF_INSN_MVFACMI, && case_sem_INSN_MVFACMI },
-    { M32RBF_INSN_MVFC, && case_sem_INSN_MVFC },
-    { M32RBF_INSN_MVTACHI, && case_sem_INSN_MVTACHI },
-    { M32RBF_INSN_MVTACLO, && case_sem_INSN_MVTACLO },
-    { M32RBF_INSN_MVTC, && case_sem_INSN_MVTC },
-    { M32RBF_INSN_NEG, && case_sem_INSN_NEG },
-    { M32RBF_INSN_NOP, && case_sem_INSN_NOP },
-    { M32RBF_INSN_NOT, && case_sem_INSN_NOT },
-    { M32RBF_INSN_RAC, && case_sem_INSN_RAC },
-    { M32RBF_INSN_RACH, && case_sem_INSN_RACH },
-    { M32RBF_INSN_RTE, && case_sem_INSN_RTE },
-    { M32RBF_INSN_SETH, && case_sem_INSN_SETH },
-    { M32RBF_INSN_SLL, && case_sem_INSN_SLL },
-    { M32RBF_INSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32RBF_INSN_SLLI, && case_sem_INSN_SLLI },
-    { M32RBF_INSN_SRA, && case_sem_INSN_SRA },
-    { M32RBF_INSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32RBF_INSN_SRAI, && case_sem_INSN_SRAI },
-    { M32RBF_INSN_SRL, && case_sem_INSN_SRL },
-    { M32RBF_INSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32RBF_INSN_SRLI, && case_sem_INSN_SRLI },
-    { M32RBF_INSN_ST, && case_sem_INSN_ST },
-    { M32RBF_INSN_ST_D, && case_sem_INSN_ST_D },
-    { M32RBF_INSN_STB, && case_sem_INSN_STB },
-    { M32RBF_INSN_STB_D, && case_sem_INSN_STB_D },
-    { M32RBF_INSN_STH, && case_sem_INSN_STH },
-    { M32RBF_INSN_STH_D, && case_sem_INSN_STH_D },
-    { M32RBF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32RBF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32RBF_INSN_SUB, && case_sem_INSN_SUB },
-    { M32RBF_INSN_SUBV, && case_sem_INSN_SUBV },
-    { M32RBF_INSN_SUBX, && case_sem_INSN_SUBX },
-    { M32RBF_INSN_TRAP, && case_sem_INSN_TRAP },
-    { M32RBF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
-    { M32RBF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
-    { M32RBF_INSN_SETPSW, && case_sem_INSN_SETPSW },
-    { M32RBF_INSN_BSET, && case_sem_INSN_BSET },
-    { M32RBF_INSN_BCLR, && case_sem_INSN_BCLR },
-    { M32RBF_INSN_BTST, && case_sem_INSN_BTST },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-    {
-#if FAST_P
-      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-    }
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = m32rbf_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV) : /* div $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REM) : /* rem $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACHI) : /* machi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLO) : /* maclo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWHI) : /* macwhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWLO) : /* macwlo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULHI) : /* mulhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULLO) : /* mullo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWHI) : /* mulwhi $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWLO) : /* mulwlo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACHI) : /* mvfachi $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACLO) : /* mvfaclo $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUM ());
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACMI) : /* mvfacmi $dr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACHI) : /* mvtachi $src1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACLO) : /* mvtaclo $src1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    SET_H_CR (FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RAC) : /* rac */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RACH) : /* rach */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  {
-    DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    SET_H_CR (((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
deleted file mode 100644
index b06c9f0..0000000
--- a/sim/m32r/sem.c
+++ /dev/null
@@ -1,2814 +0,0 @@
-/* Simulator instruction semantics for m32rbf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#define WANT_CPU m32rbf
-#define WANT_CPU_M32RBF
-
-#include "sim-main.h"
-#include "cgen-mem.h"
-#include "cgen-ops.h"
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-/* This is used so that we can compile two copies of the semantic code,
-   one with full feature support and one without that runs fast(er).
-   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */
-#if FAST_P
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#else
-#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
-#endif
-
-/* x-invalid: --invalid-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-after: --after-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-before: --before-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    m32rbf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-cti-chain: --cti-chain-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#ifdef DEFINE_SWITCH
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-chain: --chain-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-    vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* x-begin: --begin-- */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RBF
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rbf_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = m32rbf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = m32rbf_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add: add $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* add3: add3 $dr,$sr,$hash$slo16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* and: and $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* and3: and3 $dr,$sr,$uimm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* or: or $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* or3: or3 $dr,$sr,$hash$ulo16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xor: xor $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* xor3: xor3 $dr,$sr,$uimm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_and3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addi: addi $dr,$simm8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* addv: addv $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* addv3: addv3 $dr,$sr,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* addx: addx $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* bc8: bc.s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bc24: bc.l $disp24 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* beq: beq $src1,$src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* beqz: beqz $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgez: bgez $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bgtz: bgtz $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* blez: blez $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bltz: bltz $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnez: bnez $src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bl8: bl.s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bl24: bl.l $disp24 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnc8: bnc.s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bnc24: bnc.l $disp24 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bne: bne $src1,$src2,$disp16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_beq.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bra8: bra.s $disp8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* bra24: bra.l $disp24 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* cmp: cmp $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpi: cmpi $src2,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpu: cmpu $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* cmpui: cmpui $src2,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* div: div $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* divu: divu $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* rem: rem $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* remu: remu $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* jl: jl $sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* jmp: jmp $sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_jl.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* ld: ld $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ld-d: ld $dr,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldb: ldb $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldb-d: ldb $dr,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldh: ldh $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldh-d: ldh $dr,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldub: ldub $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldub-d: ldub $dr,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lduh: lduh $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lduh-d: lduh $dr,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ld-plus: ld $dr,@$sr+ */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* ld24: ld24 $dr,$uimm24 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldi8: ldi8 $dr,$simm8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_addi.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* ldi16: ldi16 $dr,$hash$slo16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* lock: lock $dr,@$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* machi: machi $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* maclo: maclo $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* macwhi: macwhi $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* macwlo: macwlo $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUM (), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mul: mul $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulhi: mulhi $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mullo: mullo $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulwhi: mulwhi $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mulwlo: mulwlo $src1,$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mv: mv $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfachi: mvfachi $dr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfaclo: mvfaclo $dr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUM ());
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfacmi: mvfacmi $dr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUM (), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvfc: mvfc $dr,$scr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtachi: mvtachi $src1 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtaclo: mvtaclo $src1 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUM (), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* mvtc: mvtc $sr,$dcr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    SET_H_CR (FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* neg: neg $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* nop: nop */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-  return vpc;
-#undef FLD
-}
-
-/* not: not $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* rac: rac */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rach: rach */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
-  tmp_tmp1 = MAKEDI (16383, 0x80000000);
-} else {
-if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (16760832, 0)))) {
-  tmp_tmp1 = MAKEDI (16760832, 0);
-} else {
-  tmp_tmp1 = ANDDI (ADDDI (GET_H_ACCUM (), MAKEDI (0, 1073741824)), MAKEDI (0xffffffff, 0x80000000));
-}
-}
-  tmp_tmp1 = SLLDI (tmp_tmp1, 1);
-  {
-    DI opval = SRADI (SLLDI (tmp_tmp1, 7), 7);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* rte: rte */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.fmt_empty.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* seth: seth $dr,$hash$hi16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_seth.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sll: sll $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sll3: sll3 $dr,$sr,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* slli: slli $dr,$uimm5 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sra: sra $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sra3: sra3 $dr,$sr,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srai: srai $dr,$uimm5 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srl: srl $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srl3: srl3 $dr,$sr,$simm16 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add3.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* srli: srli $dr,$uimm5 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_slli.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st: st $src1,@$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st-d: st $src1,@($slo16,$src2) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stb: stb $src1,@$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* stb-d: stb $src1,@($slo16,$src2) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sth: sth $src1,@$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* sth-d: sth $src1,@($slo16,$src2) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* st-plus: st $src1,@+$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* st-minus: st $src1,@-$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* sub: sub $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* subv: subv $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* subx: subx $dr,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_add.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-  return vpc;
-#undef FLD
-}
-
-/* trap: trap $uimm4 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_trap.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    SET_H_CR (((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-  return vpc;
-#undef FLD
-}
-
-/* unlock: unlock $src1,@$src2 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  return vpc;
-#undef FLD
-}
-
-/* clrpsw: clrpsw $uimm8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,clrpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* setpsw: setpsw $uimm8 */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,setpsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* bset: bset $uimm3,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bset) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* bclr: bclr $uimm3,@($slo16,$sr) */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,bclr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* btst: btst $uimm3,$sr */
-
-static SEM_PC
-SEM_FN_NAME (m32rbf,btst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_bset.f
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-  return vpc;
-#undef FLD
-}
-
-/* Table of all semantic fns.  */
-
-static const struct sem_fn_desc sem_fns[] = {
-  { M32RBF_INSN_X_INVALID, SEM_FN_NAME (m32rbf,x_invalid) },
-  { M32RBF_INSN_X_AFTER, SEM_FN_NAME (m32rbf,x_after) },
-  { M32RBF_INSN_X_BEFORE, SEM_FN_NAME (m32rbf,x_before) },
-  { M32RBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (m32rbf,x_cti_chain) },
-  { M32RBF_INSN_X_CHAIN, SEM_FN_NAME (m32rbf,x_chain) },
-  { M32RBF_INSN_X_BEGIN, SEM_FN_NAME (m32rbf,x_begin) },
-  { M32RBF_INSN_ADD, SEM_FN_NAME (m32rbf,add) },
-  { M32RBF_INSN_ADD3, SEM_FN_NAME (m32rbf,add3) },
-  { M32RBF_INSN_AND, SEM_FN_NAME (m32rbf,and) },
-  { M32RBF_INSN_AND3, SEM_FN_NAME (m32rbf,and3) },
-  { M32RBF_INSN_OR, SEM_FN_NAME (m32rbf,or) },
-  { M32RBF_INSN_OR3, SEM_FN_NAME (m32rbf,or3) },
-  { M32RBF_INSN_XOR, SEM_FN_NAME (m32rbf,xor) },
-  { M32RBF_INSN_XOR3, SEM_FN_NAME (m32rbf,xor3) },
-  { M32RBF_INSN_ADDI, SEM_FN_NAME (m32rbf,addi) },
-  { M32RBF_INSN_ADDV, SEM_FN_NAME (m32rbf,addv) },
-  { M32RBF_INSN_ADDV3, SEM_FN_NAME (m32rbf,addv3) },
-  { M32RBF_INSN_ADDX, SEM_FN_NAME (m32rbf,addx) },
-  { M32RBF_INSN_BC8, SEM_FN_NAME (m32rbf,bc8) },
-  { M32RBF_INSN_BC24, SEM_FN_NAME (m32rbf,bc24) },
-  { M32RBF_INSN_BEQ, SEM_FN_NAME (m32rbf,beq) },
-  { M32RBF_INSN_BEQZ, SEM_FN_NAME (m32rbf,beqz) },
-  { M32RBF_INSN_BGEZ, SEM_FN_NAME (m32rbf,bgez) },
-  { M32RBF_INSN_BGTZ, SEM_FN_NAME (m32rbf,bgtz) },
-  { M32RBF_INSN_BLEZ, SEM_FN_NAME (m32rbf,blez) },
-  { M32RBF_INSN_BLTZ, SEM_FN_NAME (m32rbf,bltz) },
-  { M32RBF_INSN_BNEZ, SEM_FN_NAME (m32rbf,bnez) },
-  { M32RBF_INSN_BL8, SEM_FN_NAME (m32rbf,bl8) },
-  { M32RBF_INSN_BL24, SEM_FN_NAME (m32rbf,bl24) },
-  { M32RBF_INSN_BNC8, SEM_FN_NAME (m32rbf,bnc8) },
-  { M32RBF_INSN_BNC24, SEM_FN_NAME (m32rbf,bnc24) },
-  { M32RBF_INSN_BNE, SEM_FN_NAME (m32rbf,bne) },
-  { M32RBF_INSN_BRA8, SEM_FN_NAME (m32rbf,bra8) },
-  { M32RBF_INSN_BRA24, SEM_FN_NAME (m32rbf,bra24) },
-  { M32RBF_INSN_CMP, SEM_FN_NAME (m32rbf,cmp) },
-  { M32RBF_INSN_CMPI, SEM_FN_NAME (m32rbf,cmpi) },
-  { M32RBF_INSN_CMPU, SEM_FN_NAME (m32rbf,cmpu) },
-  { M32RBF_INSN_CMPUI, SEM_FN_NAME (m32rbf,cmpui) },
-  { M32RBF_INSN_DIV, SEM_FN_NAME (m32rbf,div) },
-  { M32RBF_INSN_DIVU, SEM_FN_NAME (m32rbf,divu) },
-  { M32RBF_INSN_REM, SEM_FN_NAME (m32rbf,rem) },
-  { M32RBF_INSN_REMU, SEM_FN_NAME (m32rbf,remu) },
-  { M32RBF_INSN_JL, SEM_FN_NAME (m32rbf,jl) },
-  { M32RBF_INSN_JMP, SEM_FN_NAME (m32rbf,jmp) },
-  { M32RBF_INSN_LD, SEM_FN_NAME (m32rbf,ld) },
-  { M32RBF_INSN_LD_D, SEM_FN_NAME (m32rbf,ld_d) },
-  { M32RBF_INSN_LDB, SEM_FN_NAME (m32rbf,ldb) },
-  { M32RBF_INSN_LDB_D, SEM_FN_NAME (m32rbf,ldb_d) },
-  { M32RBF_INSN_LDH, SEM_FN_NAME (m32rbf,ldh) },
-  { M32RBF_INSN_LDH_D, SEM_FN_NAME (m32rbf,ldh_d) },
-  { M32RBF_INSN_LDUB, SEM_FN_NAME (m32rbf,ldub) },
-  { M32RBF_INSN_LDUB_D, SEM_FN_NAME (m32rbf,ldub_d) },
-  { M32RBF_INSN_LDUH, SEM_FN_NAME (m32rbf,lduh) },
-  { M32RBF_INSN_LDUH_D, SEM_FN_NAME (m32rbf,lduh_d) },
-  { M32RBF_INSN_LD_PLUS, SEM_FN_NAME (m32rbf,ld_plus) },
-  { M32RBF_INSN_LD24, SEM_FN_NAME (m32rbf,ld24) },
-  { M32RBF_INSN_LDI8, SEM_FN_NAME (m32rbf,ldi8) },
-  { M32RBF_INSN_LDI16, SEM_FN_NAME (m32rbf,ldi16) },
-  { M32RBF_INSN_LOCK, SEM_FN_NAME (m32rbf,lock) },
-  { M32RBF_INSN_MACHI, SEM_FN_NAME (m32rbf,machi) },
-  { M32RBF_INSN_MACLO, SEM_FN_NAME (m32rbf,maclo) },
-  { M32RBF_INSN_MACWHI, SEM_FN_NAME (m32rbf,macwhi) },
-  { M32RBF_INSN_MACWLO, SEM_FN_NAME (m32rbf,macwlo) },
-  { M32RBF_INSN_MUL, SEM_FN_NAME (m32rbf,mul) },
-  { M32RBF_INSN_MULHI, SEM_FN_NAME (m32rbf,mulhi) },
-  { M32RBF_INSN_MULLO, SEM_FN_NAME (m32rbf,mullo) },
-  { M32RBF_INSN_MULWHI, SEM_FN_NAME (m32rbf,mulwhi) },
-  { M32RBF_INSN_MULWLO, SEM_FN_NAME (m32rbf,mulwlo) },
-  { M32RBF_INSN_MV, SEM_FN_NAME (m32rbf,mv) },
-  { M32RBF_INSN_MVFACHI, SEM_FN_NAME (m32rbf,mvfachi) },
-  { M32RBF_INSN_MVFACLO, SEM_FN_NAME (m32rbf,mvfaclo) },
-  { M32RBF_INSN_MVFACMI, SEM_FN_NAME (m32rbf,mvfacmi) },
-  { M32RBF_INSN_MVFC, SEM_FN_NAME (m32rbf,mvfc) },
-  { M32RBF_INSN_MVTACHI, SEM_FN_NAME (m32rbf,mvtachi) },
-  { M32RBF_INSN_MVTACLO, SEM_FN_NAME (m32rbf,mvtaclo) },
-  { M32RBF_INSN_MVTC, SEM_FN_NAME (m32rbf,mvtc) },
-  { M32RBF_INSN_NEG, SEM_FN_NAME (m32rbf,neg) },
-  { M32RBF_INSN_NOP, SEM_FN_NAME (m32rbf,nop) },
-  { M32RBF_INSN_NOT, SEM_FN_NAME (m32rbf,not) },
-  { M32RBF_INSN_RAC, SEM_FN_NAME (m32rbf,rac) },
-  { M32RBF_INSN_RACH, SEM_FN_NAME (m32rbf,rach) },
-  { M32RBF_INSN_RTE, SEM_FN_NAME (m32rbf,rte) },
-  { M32RBF_INSN_SETH, SEM_FN_NAME (m32rbf,seth) },
-  { M32RBF_INSN_SLL, SEM_FN_NAME (m32rbf,sll) },
-  { M32RBF_INSN_SLL3, SEM_FN_NAME (m32rbf,sll3) },
-  { M32RBF_INSN_SLLI, SEM_FN_NAME (m32rbf,slli) },
-  { M32RBF_INSN_SRA, SEM_FN_NAME (m32rbf,sra) },
-  { M32RBF_INSN_SRA3, SEM_FN_NAME (m32rbf,sra3) },
-  { M32RBF_INSN_SRAI, SEM_FN_NAME (m32rbf,srai) },
-  { M32RBF_INSN_SRL, SEM_FN_NAME (m32rbf,srl) },
-  { M32RBF_INSN_SRL3, SEM_FN_NAME (m32rbf,srl3) },
-  { M32RBF_INSN_SRLI, SEM_FN_NAME (m32rbf,srli) },
-  { M32RBF_INSN_ST, SEM_FN_NAME (m32rbf,st) },
-  { M32RBF_INSN_ST_D, SEM_FN_NAME (m32rbf,st_d) },
-  { M32RBF_INSN_STB, SEM_FN_NAME (m32rbf,stb) },
-  { M32RBF_INSN_STB_D, SEM_FN_NAME (m32rbf,stb_d) },
-  { M32RBF_INSN_STH, SEM_FN_NAME (m32rbf,sth) },
-  { M32RBF_INSN_STH_D, SEM_FN_NAME (m32rbf,sth_d) },
-  { M32RBF_INSN_ST_PLUS, SEM_FN_NAME (m32rbf,st_plus) },
-  { M32RBF_INSN_ST_MINUS, SEM_FN_NAME (m32rbf,st_minus) },
-  { M32RBF_INSN_SUB, SEM_FN_NAME (m32rbf,sub) },
-  { M32RBF_INSN_SUBV, SEM_FN_NAME (m32rbf,subv) },
-  { M32RBF_INSN_SUBX, SEM_FN_NAME (m32rbf,subx) },
-  { M32RBF_INSN_TRAP, SEM_FN_NAME (m32rbf,trap) },
-  { M32RBF_INSN_UNLOCK, SEM_FN_NAME (m32rbf,unlock) },
-  { M32RBF_INSN_CLRPSW, SEM_FN_NAME (m32rbf,clrpsw) },
-  { M32RBF_INSN_SETPSW, SEM_FN_NAME (m32rbf,setpsw) },
-  { M32RBF_INSN_BSET, SEM_FN_NAME (m32rbf,bset) },
-  { M32RBF_INSN_BCLR, SEM_FN_NAME (m32rbf,bclr) },
-  { M32RBF_INSN_BTST, SEM_FN_NAME (m32rbf,btst) },
-  { 0, 0 }
-};
-
-/* Add the semantic fns to IDESC_TABLE.  */
-
-void
-SEM_FN_NAME (m32rbf,init_idesc_table) (SIM_CPU *current_cpu)
-{
-  IDESC *idesc_table = CPU_IDESC (current_cpu);
-  const struct sem_fn_desc *sf;
-  int mach_num = MACH_NUM (CPU_MACH (current_cpu));
-
-  for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
-    {
-      const CGEN_INSN *insn = idesc_table[sf->index].idata;
-      int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
-		     || CGEN_INSN_MACH_HAS_P (insn, mach_num));
-#if FAST_P
-      if (valid_p)
-	idesc_table[sf->index].sem_fast = sf->fn;
-      else
-	idesc_table[sf->index].sem_fast = SEM_FN_NAME (m32rbf,x_invalid);
-#else
-      if (valid_p)
-	idesc_table[sf->index].sem_full = sf->fn;
-      else
-	idesc_table[sf->index].sem_full = SEM_FN_NAME (m32rbf,x_invalid);
-#endif
-    }
-}
-
diff --git a/sim/m32r/sem2-switch.c b/sim/m32r/sem2-switch.c
deleted file mode 100644
index 82af4cd..0000000
--- a/sim/m32r/sem2-switch.c
+++ /dev/null
@@ -1,6822 +0,0 @@
-/* Simulator instruction semantics for m32r2f.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { M32R2F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { M32R2F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { M32R2F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { M32R2F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { M32R2F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { M32R2F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { M32R2F_INSN_ADD, && case_sem_INSN_ADD },
-    { M32R2F_INSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32R2F_INSN_AND, && case_sem_INSN_AND },
-    { M32R2F_INSN_AND3, && case_sem_INSN_AND3 },
-    { M32R2F_INSN_OR, && case_sem_INSN_OR },
-    { M32R2F_INSN_OR3, && case_sem_INSN_OR3 },
-    { M32R2F_INSN_XOR, && case_sem_INSN_XOR },
-    { M32R2F_INSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32R2F_INSN_ADDI, && case_sem_INSN_ADDI },
-    { M32R2F_INSN_ADDV, && case_sem_INSN_ADDV },
-    { M32R2F_INSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32R2F_INSN_ADDX, && case_sem_INSN_ADDX },
-    { M32R2F_INSN_BC8, && case_sem_INSN_BC8 },
-    { M32R2F_INSN_BC24, && case_sem_INSN_BC24 },
-    { M32R2F_INSN_BEQ, && case_sem_INSN_BEQ },
-    { M32R2F_INSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32R2F_INSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32R2F_INSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32R2F_INSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32R2F_INSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32R2F_INSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32R2F_INSN_BL8, && case_sem_INSN_BL8 },
-    { M32R2F_INSN_BL24, && case_sem_INSN_BL24 },
-    { M32R2F_INSN_BCL8, && case_sem_INSN_BCL8 },
-    { M32R2F_INSN_BCL24, && case_sem_INSN_BCL24 },
-    { M32R2F_INSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32R2F_INSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32R2F_INSN_BNE, && case_sem_INSN_BNE },
-    { M32R2F_INSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32R2F_INSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32R2F_INSN_BNCL8, && case_sem_INSN_BNCL8 },
-    { M32R2F_INSN_BNCL24, && case_sem_INSN_BNCL24 },
-    { M32R2F_INSN_CMP, && case_sem_INSN_CMP },
-    { M32R2F_INSN_CMPI, && case_sem_INSN_CMPI },
-    { M32R2F_INSN_CMPU, && case_sem_INSN_CMPU },
-    { M32R2F_INSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32R2F_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
-    { M32R2F_INSN_CMPZ, && case_sem_INSN_CMPZ },
-    { M32R2F_INSN_DIV, && case_sem_INSN_DIV },
-    { M32R2F_INSN_DIVU, && case_sem_INSN_DIVU },
-    { M32R2F_INSN_REM, && case_sem_INSN_REM },
-    { M32R2F_INSN_REMU, && case_sem_INSN_REMU },
-    { M32R2F_INSN_REMH, && case_sem_INSN_REMH },
-    { M32R2F_INSN_REMUH, && case_sem_INSN_REMUH },
-    { M32R2F_INSN_REMB, && case_sem_INSN_REMB },
-    { M32R2F_INSN_REMUB, && case_sem_INSN_REMUB },
-    { M32R2F_INSN_DIVUH, && case_sem_INSN_DIVUH },
-    { M32R2F_INSN_DIVB, && case_sem_INSN_DIVB },
-    { M32R2F_INSN_DIVUB, && case_sem_INSN_DIVUB },
-    { M32R2F_INSN_DIVH, && case_sem_INSN_DIVH },
-    { M32R2F_INSN_JC, && case_sem_INSN_JC },
-    { M32R2F_INSN_JNC, && case_sem_INSN_JNC },
-    { M32R2F_INSN_JL, && case_sem_INSN_JL },
-    { M32R2F_INSN_JMP, && case_sem_INSN_JMP },
-    { M32R2F_INSN_LD, && case_sem_INSN_LD },
-    { M32R2F_INSN_LD_D, && case_sem_INSN_LD_D },
-    { M32R2F_INSN_LDB, && case_sem_INSN_LDB },
-    { M32R2F_INSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32R2F_INSN_LDH, && case_sem_INSN_LDH },
-    { M32R2F_INSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32R2F_INSN_LDUB, && case_sem_INSN_LDUB },
-    { M32R2F_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32R2F_INSN_LDUH, && case_sem_INSN_LDUH },
-    { M32R2F_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32R2F_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32R2F_INSN_LD24, && case_sem_INSN_LD24 },
-    { M32R2F_INSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32R2F_INSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32R2F_INSN_LOCK, && case_sem_INSN_LOCK },
-    { M32R2F_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
-    { M32R2F_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
-    { M32R2F_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
-    { M32R2F_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
-    { M32R2F_INSN_MUL, && case_sem_INSN_MUL },
-    { M32R2F_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
-    { M32R2F_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
-    { M32R2F_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
-    { M32R2F_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
-    { M32R2F_INSN_MV, && case_sem_INSN_MV },
-    { M32R2F_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
-    { M32R2F_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
-    { M32R2F_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
-    { M32R2F_INSN_MVFC, && case_sem_INSN_MVFC },
-    { M32R2F_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
-    { M32R2F_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
-    { M32R2F_INSN_MVTC, && case_sem_INSN_MVTC },
-    { M32R2F_INSN_NEG, && case_sem_INSN_NEG },
-    { M32R2F_INSN_NOP, && case_sem_INSN_NOP },
-    { M32R2F_INSN_NOT, && case_sem_INSN_NOT },
-    { M32R2F_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
-    { M32R2F_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
-    { M32R2F_INSN_RTE, && case_sem_INSN_RTE },
-    { M32R2F_INSN_SETH, && case_sem_INSN_SETH },
-    { M32R2F_INSN_SLL, && case_sem_INSN_SLL },
-    { M32R2F_INSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32R2F_INSN_SLLI, && case_sem_INSN_SLLI },
-    { M32R2F_INSN_SRA, && case_sem_INSN_SRA },
-    { M32R2F_INSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32R2F_INSN_SRAI, && case_sem_INSN_SRAI },
-    { M32R2F_INSN_SRL, && case_sem_INSN_SRL },
-    { M32R2F_INSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32R2F_INSN_SRLI, && case_sem_INSN_SRLI },
-    { M32R2F_INSN_ST, && case_sem_INSN_ST },
-    { M32R2F_INSN_ST_D, && case_sem_INSN_ST_D },
-    { M32R2F_INSN_STB, && case_sem_INSN_STB },
-    { M32R2F_INSN_STB_D, && case_sem_INSN_STB_D },
-    { M32R2F_INSN_STH, && case_sem_INSN_STH },
-    { M32R2F_INSN_STH_D, && case_sem_INSN_STH_D },
-    { M32R2F_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32R2F_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },
-    { M32R2F_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },
-    { M32R2F_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32R2F_INSN_SUB, && case_sem_INSN_SUB },
-    { M32R2F_INSN_SUBV, && case_sem_INSN_SUBV },
-    { M32R2F_INSN_SUBX, && case_sem_INSN_SUBX },
-    { M32R2F_INSN_TRAP, && case_sem_INSN_TRAP },
-    { M32R2F_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
-    { M32R2F_INSN_SATB, && case_sem_INSN_SATB },
-    { M32R2F_INSN_SATH, && case_sem_INSN_SATH },
-    { M32R2F_INSN_SAT, && case_sem_INSN_SAT },
-    { M32R2F_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
-    { M32R2F_INSN_SADD, && case_sem_INSN_SADD },
-    { M32R2F_INSN_MACWU1, && case_sem_INSN_MACWU1 },
-    { M32R2F_INSN_MSBLO, && case_sem_INSN_MSBLO },
-    { M32R2F_INSN_MULWU1, && case_sem_INSN_MULWU1 },
-    { M32R2F_INSN_MACLH1, && case_sem_INSN_MACLH1 },
-    { M32R2F_INSN_SC, && case_sem_INSN_SC },
-    { M32R2F_INSN_SNC, && case_sem_INSN_SNC },
-    { M32R2F_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
-    { M32R2F_INSN_SETPSW, && case_sem_INSN_SETPSW },
-    { M32R2F_INSN_BSET, && case_sem_INSN_BSET },
-    { M32R2F_INSN_BCLR, && case_sem_INSN_BCLR },
-    { M32R2F_INSN_BTST, && case_sem_INSN_BTST },
-    { M32R2F_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
-    { M32R2F_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
-    { M32R2F_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
-    { M32R2F_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
-    { M32R2F_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
-    { M32R2F_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
-    { M32R2F_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
-    { M32R2F_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
-    { M32R2F_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
-    { M32R2F_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
-    { M32R2F_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
-    { M32R2F_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
-    { M32R2F_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
-    { M32R2F_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
-    { M32R2F_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
-    { M32R2F_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
-    { M32R2F_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
-    { M32R2F_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
-    { M32R2F_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
-    { M32R2F_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
-    { M32R2F_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
-    { M32R2F_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
-    { M32R2F_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
-    { M32R2F_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
-    { M32R2F_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
-    { M32R2F_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
-    { M32R2F_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
-    { M32R2F_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
-    { M32R2F_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
-    { M32R2F_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
-    { M32R2F_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
-    { M32R2F_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
-    { M32R2F_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
-    { M32R2F_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
-    { M32R2F_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
-    { M32R2F_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
-    { M32R2F_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
-    { M32R2F_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
-    { M32R2F_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
-    { M32R2F_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
-    { M32R2F_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
-    { M32R2F_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
-    { M32R2F_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
-    { M32R2F_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
-    { M32R2F_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
-    { M32R2F_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
-    { M32R2F_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
-    { M32R2F_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
-    { M32R2F_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
-    { M32R2F_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
-    { M32R2F_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
-    { M32R2F_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
-    { M32R2F_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
-    { M32R2F_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
-    { M32R2F_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
-    { M32R2F_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
-    { M32R2F_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
-    { M32R2F_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
-    { M32R2F_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
-    { M32R2F_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
-    { M32R2F_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
-    { M32R2F_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
-    { M32R2F_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
-    { M32R2F_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
-    { M32R2F_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
-    { M32R2F_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
-    { M32R2F_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
-    { M32R2F_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
-    { M32R2F_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
-    { M32R2F_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
-    { M32R2F_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
-    { M32R2F_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
-    { M32R2F_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
-    { M32R2F_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
-    { M32R2F_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
-    { M32R2F_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
-    { M32R2F_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
-    { M32R2F_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
-    { M32R2F_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
-    { M32R2F_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
-    { M32R2F_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
-    { M32R2F_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
-    { M32R2F_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
-    { M32R2F_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
-    { M32R2F_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
-    { M32R2F_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
-    { M32R2F_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
-    { M32R2F_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
-    { M32R2F_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
-    { M32R2F_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
-    { M32R2F_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
-    { M32R2F_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
-    { M32R2F_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
-    { M32R2F_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
-    { M32R2F_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
-    { M32R2F_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
-    { M32R2F_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
-    { M32R2F_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
-    { M32R2F_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
-    { M32R2F_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
-    { M32R2F_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
-    { M32R2F_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
-    { M32R2F_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
-    { M32R2F_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
-    { M32R2F_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
-    { M32R2F_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
-    { M32R2F_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
-    { M32R2F_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
-    { M32R2F_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
-    { M32R2F_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
-    { M32R2F_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
-    { M32R2F_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
-    { M32R2F_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
-    { M32R2F_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
-    { M32R2F_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
-    { M32R2F_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
-    { M32R2F_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
-    { M32R2F_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
-    { M32R2F_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
-    { M32R2F_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
-    { M32R2F_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
-    { M32R2F_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
-    { M32R2F_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
-    { M32R2F_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
-    { M32R2F_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },
-    { M32R2F_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },
-    { M32R2F_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },
-    { M32R2F_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },
-    { M32R2F_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
-    { M32R2F_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
-    { M32R2F_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
-    { M32R2F_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
-    { M32R2F_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
-    { M32R2F_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
-    { M32R2F_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
-    { M32R2F_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
-    { M32R2F_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
-    { M32R2F_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
-    { M32R2F_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
-    { M32R2F_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
-    { M32R2F_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
-    { M32R2F_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
-    { M32R2F_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
-    { M32R2F_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
-    { M32R2F_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
-    { M32R2F_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
-    { M32R2F_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
-    { M32R2F_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
-    { M32R2F_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
-    { M32R2F_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
-    { M32R2F_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
-    { M32R2F_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
-    { M32R2F_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
-    { M32R2F_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
-    { M32R2F_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
-    { M32R2F_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
-    { M32R2F_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },
-    { M32R2F_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },
-    { M32R2F_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },
-    { M32R2F_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },
-    { M32R2F_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },
-    { M32R2F_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-    {
-#if FAST_P
-      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-    }
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32R2F
-    m32r2f_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32R2F
-    m32r2f_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32R2F
-#ifdef DEFINE_SWITCH
-    vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32r2f_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32R2F
-    vpc = m32r2f_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32R2F
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32r2f_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = m32r2f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = m32r2f_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV) : /* div $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REM) : /* rem $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMH) : /* remh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMUH) : /* remuh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMB) : /* remb $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMUB) : /* remub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVUH) : /* divuh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVB) : /* divb $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (EXTBISI (TRUNCSIBI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVUB) : /* divub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    SET_H_CR (FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_new_src2;
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_new_src2;
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    SET_H_CR (((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATB) : /* satb $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATH) : /* sath $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SAT) : /* sat $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    SET_H_ACCUMS (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (CPU (h_cond)))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (NOTBI (CPU (h_cond))))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_addi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bra8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bra8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JC) : /* jc $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    OPRND (h_gr_SI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JL) : /* jl $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jl.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    OPRND (sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  * FLD (i_sr) = OPRND (sr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_ldi8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_ldi8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_lock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    OPRND (h_lock_BI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_lock.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  CPU (h_lock) = OPRND (h_lock_BI);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvfc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvfc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvtc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    OPRND (dcr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvtc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (FLD (f_r1), OPRND (dcr));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_nop.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NOP) : /* nop */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_nop.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_rte.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    OPRND (h_cr_USI_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_psw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    OPRND (h_bpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RTE) : /* rte */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_rte.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
-  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
-  SET_H_PSW (OPRND (h_psw_UQI));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_SI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    OPRND (h_memory_QI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_QI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    OPRND (h_memory_HI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_HI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_SI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_new_src2;
-  {
-    HI opval = * FLD (i_src1);
-    OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_HI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_new_src2;
-  {
-    QI opval = * FLD (i_src1);
-    OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_QI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_SI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_trap.f
-#define OPRND(f) par_exec->operands.sfmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    OPRND (h_cr_USI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    OPRND (h_cr_USI_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_bbpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    OPRND (h_bpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    OPRND (h_psw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_trap.f
-#define OPRND(f) par_exec->operands.sfmt_trap.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bbpsw) = OPRND (h_bbpsw_UQI);
-  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
-  SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));
-  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
-  SET_H_PSW (OPRND (h_psw_UQI));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_unlock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_SI_src2) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    OPRND (h_lock_BI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_unlock.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_lock) = OPRND (h_lock_BI);
-  if (written & (1 << 4))
-    {
-      SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
-    }
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sadd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    OPRND (h_accums_DI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SADD) : /* sadd */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sadd.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_msblo.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    OPRND (accum) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_msblo.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUM (OPRND (accum));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (CPU (h_cond)))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SC) : /* sc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (NOTBI (CPU (h_cond))))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SNC) : /* snc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    OPRND (h_cr_USI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_setpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    OPRND (h_cr_USI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_setpsw.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-#define OPRND(f) par_exec->operands.sfmt_btst.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bset.f
-#define OPRND(f) par_exec->operands.sfmt_btst.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c
deleted file mode 100644
index d1d6abb..0000000
--- a/sim/m32r/semx-switch.c
+++ /dev/null
@@ -1,6654 +0,0 @@
-/* Simulator instruction semantics for m32rxf.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
-
-This file is part of the GNU simulators.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-*/
-
-#ifdef DEFINE_LABELS
-
-  /* The labels have the case they have because the enum of insn types
-     is all uppercase and in the non-stdc case the insn symbol is built
-     into the enum name.  */
-
-  static struct {
-    int index;
-    void *label;
-  } labels[] = {
-    { M32RXF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
-    { M32RXF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
-    { M32RXF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
-    { M32RXF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
-    { M32RXF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
-    { M32RXF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
-    { M32RXF_INSN_ADD, && case_sem_INSN_ADD },
-    { M32RXF_INSN_ADD3, && case_sem_INSN_ADD3 },
-    { M32RXF_INSN_AND, && case_sem_INSN_AND },
-    { M32RXF_INSN_AND3, && case_sem_INSN_AND3 },
-    { M32RXF_INSN_OR, && case_sem_INSN_OR },
-    { M32RXF_INSN_OR3, && case_sem_INSN_OR3 },
-    { M32RXF_INSN_XOR, && case_sem_INSN_XOR },
-    { M32RXF_INSN_XOR3, && case_sem_INSN_XOR3 },
-    { M32RXF_INSN_ADDI, && case_sem_INSN_ADDI },
-    { M32RXF_INSN_ADDV, && case_sem_INSN_ADDV },
-    { M32RXF_INSN_ADDV3, && case_sem_INSN_ADDV3 },
-    { M32RXF_INSN_ADDX, && case_sem_INSN_ADDX },
-    { M32RXF_INSN_BC8, && case_sem_INSN_BC8 },
-    { M32RXF_INSN_BC24, && case_sem_INSN_BC24 },
-    { M32RXF_INSN_BEQ, && case_sem_INSN_BEQ },
-    { M32RXF_INSN_BEQZ, && case_sem_INSN_BEQZ },
-    { M32RXF_INSN_BGEZ, && case_sem_INSN_BGEZ },
-    { M32RXF_INSN_BGTZ, && case_sem_INSN_BGTZ },
-    { M32RXF_INSN_BLEZ, && case_sem_INSN_BLEZ },
-    { M32RXF_INSN_BLTZ, && case_sem_INSN_BLTZ },
-    { M32RXF_INSN_BNEZ, && case_sem_INSN_BNEZ },
-    { M32RXF_INSN_BL8, && case_sem_INSN_BL8 },
-    { M32RXF_INSN_BL24, && case_sem_INSN_BL24 },
-    { M32RXF_INSN_BCL8, && case_sem_INSN_BCL8 },
-    { M32RXF_INSN_BCL24, && case_sem_INSN_BCL24 },
-    { M32RXF_INSN_BNC8, && case_sem_INSN_BNC8 },
-    { M32RXF_INSN_BNC24, && case_sem_INSN_BNC24 },
-    { M32RXF_INSN_BNE, && case_sem_INSN_BNE },
-    { M32RXF_INSN_BRA8, && case_sem_INSN_BRA8 },
-    { M32RXF_INSN_BRA24, && case_sem_INSN_BRA24 },
-    { M32RXF_INSN_BNCL8, && case_sem_INSN_BNCL8 },
-    { M32RXF_INSN_BNCL24, && case_sem_INSN_BNCL24 },
-    { M32RXF_INSN_CMP, && case_sem_INSN_CMP },
-    { M32RXF_INSN_CMPI, && case_sem_INSN_CMPI },
-    { M32RXF_INSN_CMPU, && case_sem_INSN_CMPU },
-    { M32RXF_INSN_CMPUI, && case_sem_INSN_CMPUI },
-    { M32RXF_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
-    { M32RXF_INSN_CMPZ, && case_sem_INSN_CMPZ },
-    { M32RXF_INSN_DIV, && case_sem_INSN_DIV },
-    { M32RXF_INSN_DIVU, && case_sem_INSN_DIVU },
-    { M32RXF_INSN_REM, && case_sem_INSN_REM },
-    { M32RXF_INSN_REMU, && case_sem_INSN_REMU },
-    { M32RXF_INSN_DIVH, && case_sem_INSN_DIVH },
-    { M32RXF_INSN_JC, && case_sem_INSN_JC },
-    { M32RXF_INSN_JNC, && case_sem_INSN_JNC },
-    { M32RXF_INSN_JL, && case_sem_INSN_JL },
-    { M32RXF_INSN_JMP, && case_sem_INSN_JMP },
-    { M32RXF_INSN_LD, && case_sem_INSN_LD },
-    { M32RXF_INSN_LD_D, && case_sem_INSN_LD_D },
-    { M32RXF_INSN_LDB, && case_sem_INSN_LDB },
-    { M32RXF_INSN_LDB_D, && case_sem_INSN_LDB_D },
-    { M32RXF_INSN_LDH, && case_sem_INSN_LDH },
-    { M32RXF_INSN_LDH_D, && case_sem_INSN_LDH_D },
-    { M32RXF_INSN_LDUB, && case_sem_INSN_LDUB },
-    { M32RXF_INSN_LDUB_D, && case_sem_INSN_LDUB_D },
-    { M32RXF_INSN_LDUH, && case_sem_INSN_LDUH },
-    { M32RXF_INSN_LDUH_D, && case_sem_INSN_LDUH_D },
-    { M32RXF_INSN_LD_PLUS, && case_sem_INSN_LD_PLUS },
-    { M32RXF_INSN_LD24, && case_sem_INSN_LD24 },
-    { M32RXF_INSN_LDI8, && case_sem_INSN_LDI8 },
-    { M32RXF_INSN_LDI16, && case_sem_INSN_LDI16 },
-    { M32RXF_INSN_LOCK, && case_sem_INSN_LOCK },
-    { M32RXF_INSN_MACHI_A, && case_sem_INSN_MACHI_A },
-    { M32RXF_INSN_MACLO_A, && case_sem_INSN_MACLO_A },
-    { M32RXF_INSN_MACWHI_A, && case_sem_INSN_MACWHI_A },
-    { M32RXF_INSN_MACWLO_A, && case_sem_INSN_MACWLO_A },
-    { M32RXF_INSN_MUL, && case_sem_INSN_MUL },
-    { M32RXF_INSN_MULHI_A, && case_sem_INSN_MULHI_A },
-    { M32RXF_INSN_MULLO_A, && case_sem_INSN_MULLO_A },
-    { M32RXF_INSN_MULWHI_A, && case_sem_INSN_MULWHI_A },
-    { M32RXF_INSN_MULWLO_A, && case_sem_INSN_MULWLO_A },
-    { M32RXF_INSN_MV, && case_sem_INSN_MV },
-    { M32RXF_INSN_MVFACHI_A, && case_sem_INSN_MVFACHI_A },
-    { M32RXF_INSN_MVFACLO_A, && case_sem_INSN_MVFACLO_A },
-    { M32RXF_INSN_MVFACMI_A, && case_sem_INSN_MVFACMI_A },
-    { M32RXF_INSN_MVFC, && case_sem_INSN_MVFC },
-    { M32RXF_INSN_MVTACHI_A, && case_sem_INSN_MVTACHI_A },
-    { M32RXF_INSN_MVTACLO_A, && case_sem_INSN_MVTACLO_A },
-    { M32RXF_INSN_MVTC, && case_sem_INSN_MVTC },
-    { M32RXF_INSN_NEG, && case_sem_INSN_NEG },
-    { M32RXF_INSN_NOP, && case_sem_INSN_NOP },
-    { M32RXF_INSN_NOT, && case_sem_INSN_NOT },
-    { M32RXF_INSN_RAC_DSI, && case_sem_INSN_RAC_DSI },
-    { M32RXF_INSN_RACH_DSI, && case_sem_INSN_RACH_DSI },
-    { M32RXF_INSN_RTE, && case_sem_INSN_RTE },
-    { M32RXF_INSN_SETH, && case_sem_INSN_SETH },
-    { M32RXF_INSN_SLL, && case_sem_INSN_SLL },
-    { M32RXF_INSN_SLL3, && case_sem_INSN_SLL3 },
-    { M32RXF_INSN_SLLI, && case_sem_INSN_SLLI },
-    { M32RXF_INSN_SRA, && case_sem_INSN_SRA },
-    { M32RXF_INSN_SRA3, && case_sem_INSN_SRA3 },
-    { M32RXF_INSN_SRAI, && case_sem_INSN_SRAI },
-    { M32RXF_INSN_SRL, && case_sem_INSN_SRL },
-    { M32RXF_INSN_SRL3, && case_sem_INSN_SRL3 },
-    { M32RXF_INSN_SRLI, && case_sem_INSN_SRLI },
-    { M32RXF_INSN_ST, && case_sem_INSN_ST },
-    { M32RXF_INSN_ST_D, && case_sem_INSN_ST_D },
-    { M32RXF_INSN_STB, && case_sem_INSN_STB },
-    { M32RXF_INSN_STB_D, && case_sem_INSN_STB_D },
-    { M32RXF_INSN_STH, && case_sem_INSN_STH },
-    { M32RXF_INSN_STH_D, && case_sem_INSN_STH_D },
-    { M32RXF_INSN_ST_PLUS, && case_sem_INSN_ST_PLUS },
-    { M32RXF_INSN_STH_PLUS, && case_sem_INSN_STH_PLUS },
-    { M32RXF_INSN_STB_PLUS, && case_sem_INSN_STB_PLUS },
-    { M32RXF_INSN_ST_MINUS, && case_sem_INSN_ST_MINUS },
-    { M32RXF_INSN_SUB, && case_sem_INSN_SUB },
-    { M32RXF_INSN_SUBV, && case_sem_INSN_SUBV },
-    { M32RXF_INSN_SUBX, && case_sem_INSN_SUBX },
-    { M32RXF_INSN_TRAP, && case_sem_INSN_TRAP },
-    { M32RXF_INSN_UNLOCK, && case_sem_INSN_UNLOCK },
-    { M32RXF_INSN_SATB, && case_sem_INSN_SATB },
-    { M32RXF_INSN_SATH, && case_sem_INSN_SATH },
-    { M32RXF_INSN_SAT, && case_sem_INSN_SAT },
-    { M32RXF_INSN_PCMPBZ, && case_sem_INSN_PCMPBZ },
-    { M32RXF_INSN_SADD, && case_sem_INSN_SADD },
-    { M32RXF_INSN_MACWU1, && case_sem_INSN_MACWU1 },
-    { M32RXF_INSN_MSBLO, && case_sem_INSN_MSBLO },
-    { M32RXF_INSN_MULWU1, && case_sem_INSN_MULWU1 },
-    { M32RXF_INSN_MACLH1, && case_sem_INSN_MACLH1 },
-    { M32RXF_INSN_SC, && case_sem_INSN_SC },
-    { M32RXF_INSN_SNC, && case_sem_INSN_SNC },
-    { M32RXF_INSN_CLRPSW, && case_sem_INSN_CLRPSW },
-    { M32RXF_INSN_SETPSW, && case_sem_INSN_SETPSW },
-    { M32RXF_INSN_BSET, && case_sem_INSN_BSET },
-    { M32RXF_INSN_BCLR, && case_sem_INSN_BCLR },
-    { M32RXF_INSN_BTST, && case_sem_INSN_BTST },
-    { M32RXF_INSN_PAR_ADD, && case_sem_INSN_PAR_ADD },
-    { M32RXF_INSN_WRITE_ADD, && case_sem_INSN_WRITE_ADD },
-    { M32RXF_INSN_PAR_AND, && case_sem_INSN_PAR_AND },
-    { M32RXF_INSN_WRITE_AND, && case_sem_INSN_WRITE_AND },
-    { M32RXF_INSN_PAR_OR, && case_sem_INSN_PAR_OR },
-    { M32RXF_INSN_WRITE_OR, && case_sem_INSN_WRITE_OR },
-    { M32RXF_INSN_PAR_XOR, && case_sem_INSN_PAR_XOR },
-    { M32RXF_INSN_WRITE_XOR, && case_sem_INSN_WRITE_XOR },
-    { M32RXF_INSN_PAR_ADDI, && case_sem_INSN_PAR_ADDI },
-    { M32RXF_INSN_WRITE_ADDI, && case_sem_INSN_WRITE_ADDI },
-    { M32RXF_INSN_PAR_ADDV, && case_sem_INSN_PAR_ADDV },
-    { M32RXF_INSN_WRITE_ADDV, && case_sem_INSN_WRITE_ADDV },
-    { M32RXF_INSN_PAR_ADDX, && case_sem_INSN_PAR_ADDX },
-    { M32RXF_INSN_WRITE_ADDX, && case_sem_INSN_WRITE_ADDX },
-    { M32RXF_INSN_PAR_BC8, && case_sem_INSN_PAR_BC8 },
-    { M32RXF_INSN_WRITE_BC8, && case_sem_INSN_WRITE_BC8 },
-    { M32RXF_INSN_PAR_BL8, && case_sem_INSN_PAR_BL8 },
-    { M32RXF_INSN_WRITE_BL8, && case_sem_INSN_WRITE_BL8 },
-    { M32RXF_INSN_PAR_BCL8, && case_sem_INSN_PAR_BCL8 },
-    { M32RXF_INSN_WRITE_BCL8, && case_sem_INSN_WRITE_BCL8 },
-    { M32RXF_INSN_PAR_BNC8, && case_sem_INSN_PAR_BNC8 },
-    { M32RXF_INSN_WRITE_BNC8, && case_sem_INSN_WRITE_BNC8 },
-    { M32RXF_INSN_PAR_BRA8, && case_sem_INSN_PAR_BRA8 },
-    { M32RXF_INSN_WRITE_BRA8, && case_sem_INSN_WRITE_BRA8 },
-    { M32RXF_INSN_PAR_BNCL8, && case_sem_INSN_PAR_BNCL8 },
-    { M32RXF_INSN_WRITE_BNCL8, && case_sem_INSN_WRITE_BNCL8 },
-    { M32RXF_INSN_PAR_CMP, && case_sem_INSN_PAR_CMP },
-    { M32RXF_INSN_WRITE_CMP, && case_sem_INSN_WRITE_CMP },
-    { M32RXF_INSN_PAR_CMPU, && case_sem_INSN_PAR_CMPU },
-    { M32RXF_INSN_WRITE_CMPU, && case_sem_INSN_WRITE_CMPU },
-    { M32RXF_INSN_PAR_CMPEQ, && case_sem_INSN_PAR_CMPEQ },
-    { M32RXF_INSN_WRITE_CMPEQ, && case_sem_INSN_WRITE_CMPEQ },
-    { M32RXF_INSN_PAR_CMPZ, && case_sem_INSN_PAR_CMPZ },
-    { M32RXF_INSN_WRITE_CMPZ, && case_sem_INSN_WRITE_CMPZ },
-    { M32RXF_INSN_PAR_JC, && case_sem_INSN_PAR_JC },
-    { M32RXF_INSN_WRITE_JC, && case_sem_INSN_WRITE_JC },
-    { M32RXF_INSN_PAR_JNC, && case_sem_INSN_PAR_JNC },
-    { M32RXF_INSN_WRITE_JNC, && case_sem_INSN_WRITE_JNC },
-    { M32RXF_INSN_PAR_JL, && case_sem_INSN_PAR_JL },
-    { M32RXF_INSN_WRITE_JL, && case_sem_INSN_WRITE_JL },
-    { M32RXF_INSN_PAR_JMP, && case_sem_INSN_PAR_JMP },
-    { M32RXF_INSN_WRITE_JMP, && case_sem_INSN_WRITE_JMP },
-    { M32RXF_INSN_PAR_LD, && case_sem_INSN_PAR_LD },
-    { M32RXF_INSN_WRITE_LD, && case_sem_INSN_WRITE_LD },
-    { M32RXF_INSN_PAR_LDB, && case_sem_INSN_PAR_LDB },
-    { M32RXF_INSN_WRITE_LDB, && case_sem_INSN_WRITE_LDB },
-    { M32RXF_INSN_PAR_LDH, && case_sem_INSN_PAR_LDH },
-    { M32RXF_INSN_WRITE_LDH, && case_sem_INSN_WRITE_LDH },
-    { M32RXF_INSN_PAR_LDUB, && case_sem_INSN_PAR_LDUB },
-    { M32RXF_INSN_WRITE_LDUB, && case_sem_INSN_WRITE_LDUB },
-    { M32RXF_INSN_PAR_LDUH, && case_sem_INSN_PAR_LDUH },
-    { M32RXF_INSN_WRITE_LDUH, && case_sem_INSN_WRITE_LDUH },
-    { M32RXF_INSN_PAR_LD_PLUS, && case_sem_INSN_PAR_LD_PLUS },
-    { M32RXF_INSN_WRITE_LD_PLUS, && case_sem_INSN_WRITE_LD_PLUS },
-    { M32RXF_INSN_PAR_LDI8, && case_sem_INSN_PAR_LDI8 },
-    { M32RXF_INSN_WRITE_LDI8, && case_sem_INSN_WRITE_LDI8 },
-    { M32RXF_INSN_PAR_LOCK, && case_sem_INSN_PAR_LOCK },
-    { M32RXF_INSN_WRITE_LOCK, && case_sem_INSN_WRITE_LOCK },
-    { M32RXF_INSN_PAR_MACHI_A, && case_sem_INSN_PAR_MACHI_A },
-    { M32RXF_INSN_WRITE_MACHI_A, && case_sem_INSN_WRITE_MACHI_A },
-    { M32RXF_INSN_PAR_MACLO_A, && case_sem_INSN_PAR_MACLO_A },
-    { M32RXF_INSN_WRITE_MACLO_A, && case_sem_INSN_WRITE_MACLO_A },
-    { M32RXF_INSN_PAR_MACWHI_A, && case_sem_INSN_PAR_MACWHI_A },
-    { M32RXF_INSN_WRITE_MACWHI_A, && case_sem_INSN_WRITE_MACWHI_A },
-    { M32RXF_INSN_PAR_MACWLO_A, && case_sem_INSN_PAR_MACWLO_A },
-    { M32RXF_INSN_WRITE_MACWLO_A, && case_sem_INSN_WRITE_MACWLO_A },
-    { M32RXF_INSN_PAR_MUL, && case_sem_INSN_PAR_MUL },
-    { M32RXF_INSN_WRITE_MUL, && case_sem_INSN_WRITE_MUL },
-    { M32RXF_INSN_PAR_MULHI_A, && case_sem_INSN_PAR_MULHI_A },
-    { M32RXF_INSN_WRITE_MULHI_A, && case_sem_INSN_WRITE_MULHI_A },
-    { M32RXF_INSN_PAR_MULLO_A, && case_sem_INSN_PAR_MULLO_A },
-    { M32RXF_INSN_WRITE_MULLO_A, && case_sem_INSN_WRITE_MULLO_A },
-    { M32RXF_INSN_PAR_MULWHI_A, && case_sem_INSN_PAR_MULWHI_A },
-    { M32RXF_INSN_WRITE_MULWHI_A, && case_sem_INSN_WRITE_MULWHI_A },
-    { M32RXF_INSN_PAR_MULWLO_A, && case_sem_INSN_PAR_MULWLO_A },
-    { M32RXF_INSN_WRITE_MULWLO_A, && case_sem_INSN_WRITE_MULWLO_A },
-    { M32RXF_INSN_PAR_MV, && case_sem_INSN_PAR_MV },
-    { M32RXF_INSN_WRITE_MV, && case_sem_INSN_WRITE_MV },
-    { M32RXF_INSN_PAR_MVFACHI_A, && case_sem_INSN_PAR_MVFACHI_A },
-    { M32RXF_INSN_WRITE_MVFACHI_A, && case_sem_INSN_WRITE_MVFACHI_A },
-    { M32RXF_INSN_PAR_MVFACLO_A, && case_sem_INSN_PAR_MVFACLO_A },
-    { M32RXF_INSN_WRITE_MVFACLO_A, && case_sem_INSN_WRITE_MVFACLO_A },
-    { M32RXF_INSN_PAR_MVFACMI_A, && case_sem_INSN_PAR_MVFACMI_A },
-    { M32RXF_INSN_WRITE_MVFACMI_A, && case_sem_INSN_WRITE_MVFACMI_A },
-    { M32RXF_INSN_PAR_MVFC, && case_sem_INSN_PAR_MVFC },
-    { M32RXF_INSN_WRITE_MVFC, && case_sem_INSN_WRITE_MVFC },
-    { M32RXF_INSN_PAR_MVTACHI_A, && case_sem_INSN_PAR_MVTACHI_A },
-    { M32RXF_INSN_WRITE_MVTACHI_A, && case_sem_INSN_WRITE_MVTACHI_A },
-    { M32RXF_INSN_PAR_MVTACLO_A, && case_sem_INSN_PAR_MVTACLO_A },
-    { M32RXF_INSN_WRITE_MVTACLO_A, && case_sem_INSN_WRITE_MVTACLO_A },
-    { M32RXF_INSN_PAR_MVTC, && case_sem_INSN_PAR_MVTC },
-    { M32RXF_INSN_WRITE_MVTC, && case_sem_INSN_WRITE_MVTC },
-    { M32RXF_INSN_PAR_NEG, && case_sem_INSN_PAR_NEG },
-    { M32RXF_INSN_WRITE_NEG, && case_sem_INSN_WRITE_NEG },
-    { M32RXF_INSN_PAR_NOP, && case_sem_INSN_PAR_NOP },
-    { M32RXF_INSN_WRITE_NOP, && case_sem_INSN_WRITE_NOP },
-    { M32RXF_INSN_PAR_NOT, && case_sem_INSN_PAR_NOT },
-    { M32RXF_INSN_WRITE_NOT, && case_sem_INSN_WRITE_NOT },
-    { M32RXF_INSN_PAR_RAC_DSI, && case_sem_INSN_PAR_RAC_DSI },
-    { M32RXF_INSN_WRITE_RAC_DSI, && case_sem_INSN_WRITE_RAC_DSI },
-    { M32RXF_INSN_PAR_RACH_DSI, && case_sem_INSN_PAR_RACH_DSI },
-    { M32RXF_INSN_WRITE_RACH_DSI, && case_sem_INSN_WRITE_RACH_DSI },
-    { M32RXF_INSN_PAR_RTE, && case_sem_INSN_PAR_RTE },
-    { M32RXF_INSN_WRITE_RTE, && case_sem_INSN_WRITE_RTE },
-    { M32RXF_INSN_PAR_SLL, && case_sem_INSN_PAR_SLL },
-    { M32RXF_INSN_WRITE_SLL, && case_sem_INSN_WRITE_SLL },
-    { M32RXF_INSN_PAR_SLLI, && case_sem_INSN_PAR_SLLI },
-    { M32RXF_INSN_WRITE_SLLI, && case_sem_INSN_WRITE_SLLI },
-    { M32RXF_INSN_PAR_SRA, && case_sem_INSN_PAR_SRA },
-    { M32RXF_INSN_WRITE_SRA, && case_sem_INSN_WRITE_SRA },
-    { M32RXF_INSN_PAR_SRAI, && case_sem_INSN_PAR_SRAI },
-    { M32RXF_INSN_WRITE_SRAI, && case_sem_INSN_WRITE_SRAI },
-    { M32RXF_INSN_PAR_SRL, && case_sem_INSN_PAR_SRL },
-    { M32RXF_INSN_WRITE_SRL, && case_sem_INSN_WRITE_SRL },
-    { M32RXF_INSN_PAR_SRLI, && case_sem_INSN_PAR_SRLI },
-    { M32RXF_INSN_WRITE_SRLI, && case_sem_INSN_WRITE_SRLI },
-    { M32RXF_INSN_PAR_ST, && case_sem_INSN_PAR_ST },
-    { M32RXF_INSN_WRITE_ST, && case_sem_INSN_WRITE_ST },
-    { M32RXF_INSN_PAR_STB, && case_sem_INSN_PAR_STB },
-    { M32RXF_INSN_WRITE_STB, && case_sem_INSN_WRITE_STB },
-    { M32RXF_INSN_PAR_STH, && case_sem_INSN_PAR_STH },
-    { M32RXF_INSN_WRITE_STH, && case_sem_INSN_WRITE_STH },
-    { M32RXF_INSN_PAR_ST_PLUS, && case_sem_INSN_PAR_ST_PLUS },
-    { M32RXF_INSN_WRITE_ST_PLUS, && case_sem_INSN_WRITE_ST_PLUS },
-    { M32RXF_INSN_PAR_STH_PLUS, && case_sem_INSN_PAR_STH_PLUS },
-    { M32RXF_INSN_WRITE_STH_PLUS, && case_sem_INSN_WRITE_STH_PLUS },
-    { M32RXF_INSN_PAR_STB_PLUS, && case_sem_INSN_PAR_STB_PLUS },
-    { M32RXF_INSN_WRITE_STB_PLUS, && case_sem_INSN_WRITE_STB_PLUS },
-    { M32RXF_INSN_PAR_ST_MINUS, && case_sem_INSN_PAR_ST_MINUS },
-    { M32RXF_INSN_WRITE_ST_MINUS, && case_sem_INSN_WRITE_ST_MINUS },
-    { M32RXF_INSN_PAR_SUB, && case_sem_INSN_PAR_SUB },
-    { M32RXF_INSN_WRITE_SUB, && case_sem_INSN_WRITE_SUB },
-    { M32RXF_INSN_PAR_SUBV, && case_sem_INSN_PAR_SUBV },
-    { M32RXF_INSN_WRITE_SUBV, && case_sem_INSN_WRITE_SUBV },
-    { M32RXF_INSN_PAR_SUBX, && case_sem_INSN_PAR_SUBX },
-    { M32RXF_INSN_WRITE_SUBX, && case_sem_INSN_WRITE_SUBX },
-    { M32RXF_INSN_PAR_TRAP, && case_sem_INSN_PAR_TRAP },
-    { M32RXF_INSN_WRITE_TRAP, && case_sem_INSN_WRITE_TRAP },
-    { M32RXF_INSN_PAR_UNLOCK, && case_sem_INSN_PAR_UNLOCK },
-    { M32RXF_INSN_WRITE_UNLOCK, && case_sem_INSN_WRITE_UNLOCK },
-    { M32RXF_INSN_PAR_PCMPBZ, && case_sem_INSN_PAR_PCMPBZ },
-    { M32RXF_INSN_WRITE_PCMPBZ, && case_sem_INSN_WRITE_PCMPBZ },
-    { M32RXF_INSN_PAR_SADD, && case_sem_INSN_PAR_SADD },
-    { M32RXF_INSN_WRITE_SADD, && case_sem_INSN_WRITE_SADD },
-    { M32RXF_INSN_PAR_MACWU1, && case_sem_INSN_PAR_MACWU1 },
-    { M32RXF_INSN_WRITE_MACWU1, && case_sem_INSN_WRITE_MACWU1 },
-    { M32RXF_INSN_PAR_MSBLO, && case_sem_INSN_PAR_MSBLO },
-    { M32RXF_INSN_WRITE_MSBLO, && case_sem_INSN_WRITE_MSBLO },
-    { M32RXF_INSN_PAR_MULWU1, && case_sem_INSN_PAR_MULWU1 },
-    { M32RXF_INSN_WRITE_MULWU1, && case_sem_INSN_WRITE_MULWU1 },
-    { M32RXF_INSN_PAR_MACLH1, && case_sem_INSN_PAR_MACLH1 },
-    { M32RXF_INSN_WRITE_MACLH1, && case_sem_INSN_WRITE_MACLH1 },
-    { M32RXF_INSN_PAR_SC, && case_sem_INSN_PAR_SC },
-    { M32RXF_INSN_WRITE_SC, && case_sem_INSN_WRITE_SC },
-    { M32RXF_INSN_PAR_SNC, && case_sem_INSN_PAR_SNC },
-    { M32RXF_INSN_WRITE_SNC, && case_sem_INSN_WRITE_SNC },
-    { M32RXF_INSN_PAR_CLRPSW, && case_sem_INSN_PAR_CLRPSW },
-    { M32RXF_INSN_WRITE_CLRPSW, && case_sem_INSN_WRITE_CLRPSW },
-    { M32RXF_INSN_PAR_SETPSW, && case_sem_INSN_PAR_SETPSW },
-    { M32RXF_INSN_WRITE_SETPSW, && case_sem_INSN_WRITE_SETPSW },
-    { M32RXF_INSN_PAR_BTST, && case_sem_INSN_PAR_BTST },
-    { M32RXF_INSN_WRITE_BTST, && case_sem_INSN_WRITE_BTST },
-    { 0, 0 }
-  };
-  int i;
-
-  for (i = 0; labels[i].label != 0; ++i)
-    {
-#if FAST_P
-      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
-#else
-      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
-#endif
-    }
-
-#undef DEFINE_LABELS
-#endif /* DEFINE_LABELS */
-
-#ifdef DEFINE_SWITCH
-
-/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
-   off frills like tracing and profiling.  */
-/* FIXME: A better way would be to have TRACE_RESULT check for something
-   that can cause it to be optimized out.  Another way would be to emit
-   special handlers into the instruction "stream".  */
-
-#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
-#endif
-
-#undef GET_ATTR
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
-#else
-#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
-#endif
-
-{
-
-#if WITH_SCACHE_PBB
-
-/* Branch to next handler without going around main loop.  */
-#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
-SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
-
-#else /* ! WITH_SCACHE_PBB */
-
-#define NEXT(vpc) BREAK (sem)
-#ifdef __GNUC__
-#if FAST_P
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
-#endif
-#else
-  SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
-#endif
-
-#endif /* ! WITH_SCACHE_PBB */
-
-    {
-
-  CASE (sem, INSN_X_INVALID) : /* --invalid-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-    /* Update the recorded pc in the cpu state struct.
-       Only necessary for WITH_SCACHE case, but to avoid the
-       conditional compilation ....  */
-    SET_H_PC (pc);
-    /* Virtual insns have zero size.  Overwrite vpc with address of next insn
-       using the default-insn-bitsize spec.  When executing insns in parallel
-       we may want to queue the fault and continue execution.  */
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-    vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_AFTER) : /* --after-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    m32rxf_pbb_after (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEFORE) : /* --before-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    m32rxf_pbb_before (current_cpu, sem_arg);
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-#ifdef DEFINE_SWITCH
-    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_type, pbb_br_npc);
-    BREAK (sem);
-#else
-    /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
-    vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_TYPE (current_cpu),
-			       CPU_PBB_BR_NPC (current_cpu));
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_CHAIN) : /* --chain-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-    vpc = m32rxf_pbb_chain (current_cpu, sem_arg);
-#ifdef DEFINE_SWITCH
-    BREAK (sem);
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_X_BEGIN) : /* --begin-- */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  {
-#if WITH_SCACHE_PBB_M32RXF
-#if defined DEFINE_SWITCH || defined FAST_P
-    /* In the switch case FAST_P is a constant, allowing several optimizations
-       in any called inline functions.  */
-    vpc = m32rxf_pbb_begin (current_cpu, FAST_P);
-#else
-#if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
-    vpc = m32rxf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
-#else
-    vpc = m32rxf_pbb_begin (current_cpu, 0);
-#endif
-#endif
-#endif
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADD3) : /* add3 $dr,$sr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ADDSI (* FLD (i_sr), FLD (f_simm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_AND3) : /* and3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ANDSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_OR3) : /* or3 $dr,$sr,$hash$ulo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_XOR3) : /* xor3 $dr,$sr,$uimm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_and3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = XORSI (* FLD (i_sr), FLD (f_uimm16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDV3) : /* addv3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
-  temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BC24) : /* bc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQ) : /* beq $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BEQZ) : /* beqz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (EQSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGEZ) : /* bgez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BGTZ) : /* bgtz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (GTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLEZ) : /* blez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BLTZ) : /* bltz $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (LTSI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNEZ) : /* bnez $src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src2), 0)) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BL24) : /* bl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCL24) : /* bcl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNC24) : /* bnc.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNE) : /* bne $src1,$src2,$disp16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_beq.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_src1), * FLD (i_src2))) {
-  {
-    USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BRA24) : /* bra.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BNCL24) : /* bncl.l $disp24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (pc, 4);
-    CPU (h_gr[((UINT) 14)]) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPI) : /* cmpi $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPUI) : /* cmpui $src2,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    BI opval = LTUSI (* FLD (i_src2), FLD (f_simm16));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIV) : /* div $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVU) : /* divu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UDIVSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REM) : /* rem $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = MODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_REMU) : /* remu $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = UMODSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_DIVH) : /* divh $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-if (NESI (* FLD (i_sr), 0)) {
-  {
-    SI opval = DIVSI (EXTHISI (TRUNCSIHI (* FLD (i_dr))), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    CPU (h_gr[((UINT) 14)]) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_D) : /* ld $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDB_D) : /* ldb $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDH_D) : /* ldh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUB_D) : /* ldub $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDUH_D) : /* lduh $dr,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    * FLD (i_sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LD24) : /* ld24 $dr,$uimm24 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld24.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (i_uimm24);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LDI16) : /* ldi16 $dr,$hash$slo16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = FLD (f_simm16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    SET_H_ACCUMS (FLD (f_acc), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    SET_H_ACCUMS (FLD (f_accs), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    SET_H_CR (FLD (f_r1), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    SET_H_ACCUMS (FLD (f_accd), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETH) : /* seth $dr,$hash$hi16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_seth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (FLD (f_hi16), 16);
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLL3) : /* sll3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SLLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRA3) : /* sra3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRASI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRL3) : /* srl3 $dr,$sr,$simm16 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add3.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = SRLSI (* FLD (i_sr), ANDSI (FLD (f_simm16), 31));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_D) : /* st $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_D) : /* stb $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_D) : /* sth $src1,@($slo16,$src2) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_d.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STH_PLUS) : /* sth $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_new_src2;
-  {
-    HI opval = * FLD (i_src1);
-    SETMEMHI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_STB_PLUS) : /* stb $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_new_src2;
-  {
-    QI opval = * FLD (i_src1);
-    SETMEMQI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    * FLD (i_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  SEM_BRANCH_INIT
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    SET_H_CR (((UINT) 14), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    SET_H_CR (((UINT) 6), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    CPU (h_bbpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    CPU (h_bpsw) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    SET_H_PSW (opval);
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  SEM_BRANCH_FINI (vpc);
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    CPU (h_lock) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATB) : /* satb $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 127)) ? (127) : (LESI (* FLD (i_sr), -128)) ? (-128) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SATH) : /* sath $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = (GESI (* FLD (i_sr), 32767)) ? (32767) : (LESI (* FLD (i_sr), -32768)) ? (-32768) : (* FLD (i_sr));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SAT) : /* sat $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    SI opval = ((CPU (h_cond)) ? (((LTSI (* FLD (i_sr), 0)) ? (2147483647) : (0x80000000))) : (* FLD (i_sr)));
-    * FLD (i_dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    SET_H_ACCUMS (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    SET_H_ACCUM (opval);
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    SET_H_ACCUMS (((UINT) 1), opval);
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (CPU (h_cond)))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (NOTBI (CPU (h_cond))))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_CLRPSW) : /* clrpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_SETPSW) : /* setpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    SET_H_CR (((UINT) 0), opval);
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BSET) : /* bset $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ORQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), SLLSI (1, SUBSI (7, FLD (f_uimm3))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BCLR) : /* bclr $uimm3,@($slo16,$sr) */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-
-  {
-    QI opval = ANDQI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))), INVQI (SLLSI (1, SUBSI (7, FLD (f_uimm3)))));
-    SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)), opval);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_BTST) : /* btst $uimm3,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    CPU (h_cond) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef FLD
-}
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADD) : /* add $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADD) : /* add $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_AND) : /* and $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_AND) : /* and $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_OR) : /* or $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_OR) : /* or $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_XOR) : /* xor $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = XORSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_XOR) : /* xor $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDI) : /* addi $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_addi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ADDSI (* FLD (i_dr), FLD (f_simm8));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDI) : /* addi $dr,$simm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_addi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDV) : /* addv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDV) : /* addv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ADDX) : /* addx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ADDX) : /* addx $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BC8) : /* bc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BC8) : /* bc.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BL8) : /* bl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BL8) : /* bl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BCL8) : /* bcl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BCL8) : /* bcl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNC8) : /* bnc.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BNC8) : /* bnc.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bc8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BRA8) : /* bra.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bra8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BRA8) : /* bra.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bra8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BNCL8) : /* bncl.s $disp8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-{
-  {
-    SI opval = ADDSI (ANDSI (pc, -4), 4);
-    OPRND (h_gr_SI_14) = opval;
-    written |= (1 << 3);
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = FLD (i_disp8);
-    OPRND (pc) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BNCL8) : /* bncl.s $disp8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bl8.f
-#define OPRND(f) par_exec->operands.sfmt_bcl8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 3))
-    {
-      CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-    }
-  if (written & (1 << 4))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMP) : /* cmp $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMP) : /* cmp $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPU) : /* cmpu $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = LTUSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPU) : /* cmpu $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPEQ) : /* cmpeq $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src1), * FLD (i_src2));
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPEQ) : /* cmpeq $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CMPZ) : /* cmpz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = EQSI (* FLD (i_src2), 0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CMPZ) : /* cmpz $src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JC) : /* jc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (CPU (h_cond)) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JC) : /* jc $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JNC) : /* jnc $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (NOTBI (CPU (h_cond))) {
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    written |= (1 << 2);
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JNC) : /* jnc $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  if (written & (1 << 2))
-    {
-      SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-    }
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JL) : /* jl $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jl.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;USI temp1;
-  temp0 = ADDSI (ANDSI (pc, -4), 4);
-  temp1 = ANDSI (* FLD (i_sr), -4);
-  {
-    SI opval = temp0;
-    OPRND (h_gr_SI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    USI opval = temp1;
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JL) : /* jl $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jl.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14);
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_JMP) : /* jmp $sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jmp.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = ANDSI (* FLD (i_sr), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_JMP) : /* jmp $sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_jl.f
-#define OPRND(f) par_exec->operands.sfmt_jmp.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD) : /* ld $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LD) : /* ld $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDB) : /* ldb $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDB) : /* ldb $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDH) : /* ldh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDH) : /* ldh $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUB) : /* ldub $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDUB) : /* ldub $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDUH) : /* lduh $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDUH) : /* lduh $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ldh.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LD_PLUS) : /* ld $dr,@$sr+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;SI temp1;
-  temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-  temp1 = ADDSI (* FLD (i_sr), 4);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    SI opval = temp1;
-    OPRND (sr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LD_PLUS) : /* ld $dr,@$sr+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_ld_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  * FLD (i_sr) = OPRND (sr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LDI8) : /* ldi8 $dr,$simm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_ldi8.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_simm8);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LDI8) : /* ldi8 $dr,$simm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_addi.f
-#define OPRND(f) par_exec->operands.sfmt_ldi8.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_LOCK) : /* lock $dr,@$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_lock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    BI opval = 1;
-    OPRND (h_lock_BI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-  {
-    SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_LOCK) : /* lock $dr,@$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_lock.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-  CPU (h_lock) = OPRND (h_lock_BI);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACHI_A) : /* machi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACHI_A) : /* machi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLO_A) : /* maclo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACLO_A) : /* maclo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWHI_A) : /* macwhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWLO_A) : /* macwlo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_machi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MUL) : /* mul $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = MULSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MUL) : /* mul $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULHI_A) : /* mulhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULHI_A) : /* mulhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULLO_A) : /* mullo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16);
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULLO_A) : /* mullo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWHI_A) : /* mulwhi $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))));
-    OPRND (acc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWLO_A) : /* mulwlo $src1,$src2,$acc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_machi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mulhi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_acc), OPRND (acc));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MV) : /* mv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_sr);
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MV) : /* mv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACHI_A) : /* mvfachi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACHI_A) : /* mvfachi $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACLO_A) : /* mvfaclo $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs)));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACLO_A) : /* mvfaclo $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFACMI_A) : /* mvfacmi $dr,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFACMI_A) : /* mvfacmi $dr,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvfachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvfachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVFC) : /* mvfc $dr,$scr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvfc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = GET_H_CR (FLD (f_r2));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVFC) : /* mvfc $dr,$scr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvfc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACHI_A) : /* mvtachi $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTACHI_A) : /* mvtachi $src1,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTACLO_A) : /* mvtaclo $src1,$accs */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1)));
-    OPRND (accs) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTACLO_A) : /* mvtaclo $src1,$accs */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_mvtachi_a.f
-#define OPRND(f) par_exec->operands.sfmt_mvtachi_a.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accs), OPRND (accs));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MVTC) : /* mvtc $sr,$dcr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvtc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    USI opval = * FLD (i_sr);
-    OPRND (dcr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MVTC) : /* mvtc $sr,$dcr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mvtc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (FLD (f_r1), OPRND (dcr));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NEG) : /* neg $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = NEGSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NEG) : /* neg $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOP) : /* nop */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_nop.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NOP) : /* nop */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_nop.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_NOT) : /* not $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = INVSI (* FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_NOT) : /* not $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_ld_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RAC_DSI) : /* rac $accd,$accs,$imm1 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  DI tmp_tmp1;
-  tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1));
-  tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
-  {
-    DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0)));
-    OPRND (accd) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RACH_DSI) : /* rach $accd,$accs,$imm1 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_rac_dsi.f
-#define OPRND(f) par_exec->operands.sfmt_rac_dsi.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (FLD (f_accd), OPRND (accd));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_RTE) : /* rte */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_rte.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-  {
-    USI opval = GET_H_CR (((UINT) 14));
-    OPRND (h_cr_USI_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_psw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bbpsw);
-    OPRND (h_bpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_RTE) : /* rte */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_rte.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
-  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
-  SET_H_PSW (OPRND (h_psw_UQI));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLL) : /* sll $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SLL) : /* sll $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SLLI) : /* slli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SLLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SLLI) : /* slli $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRA) : /* sra $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRA) : /* sra $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRAI) : /* srai $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRASI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRAI) : /* srai $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRL) : /* srl $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), ANDSI (* FLD (i_sr), 31));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRL) : /* srl $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SRLI) : /* srli $dr,$uimm5 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SRLSI (* FLD (i_dr), FLD (f_uimm5));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SRLI) : /* srli $dr,$uimm5 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_slli.f
-#define OPRND(f) par_exec->operands.sfmt_slli.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST) : /* st $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_SI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST) : /* st $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STB) : /* stb $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    QI opval = * FLD (i_src1);
-    OPRND (h_memory_QI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_QI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STB) : /* stb $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_src2_idx), OPRND (h_memory_QI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STH) : /* sth $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    HI opval = * FLD (i_src1);
-    OPRND (h_memory_HI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_HI_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STH) : /* sth $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_src2_idx), OPRND (h_memory_HI_src2));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_PLUS) : /* st $src1,@+$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_SI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST_PLUS) : /* st $src1,@+$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STH_PLUS) : /* sth $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  HI tmp_new_src2;
-  {
-    HI opval = * FLD (i_src1);
-    OPRND (h_memory_HI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_HI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 2);
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STH_PLUS) : /* sth $src1,@$src2+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_sth_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMHI (current_cpu, pc, OPRND (h_memory_HI_new_src2_idx), OPRND (h_memory_HI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_STB_PLUS) : /* stb $src1,@$src2+ */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  QI tmp_new_src2;
-  {
-    QI opval = * FLD (i_src1);
-    OPRND (h_memory_QI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_QI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  tmp_new_src2 = ADDSI (* FLD (i_src2), 1);
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_STB_PLUS) : /* stb $src1,@$src2+ */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_stb_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMQI (current_cpu, pc, OPRND (h_memory_QI_new_src2_idx), OPRND (h_memory_QI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_ST_MINUS) : /* st $src1,@-$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI tmp_new_src2;
-  tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_new_src2_idx) = tmp_new_src2;
-    OPRND (h_memory_SI_new_src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-  {
-    SI opval = tmp_new_src2;
-    OPRND (src2) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_ST_MINUS) : /* st $src1,@-$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_st_plus.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_new_src2_idx), OPRND (h_memory_SI_new_src2));
-  * FLD (i_src2) = OPRND (src2);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUB) : /* sub $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = SUBSI (* FLD (i_dr), * FLD (i_sr));
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUB) : /* sub $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_add.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBV) : /* subv $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
-  temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUBV) : /* subv $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addv.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SUBX) : /* subx $dr,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  SI temp0;BI temp1;
-  temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
-  {
-    SI opval = temp0;
-    OPRND (dr) = opval;
-    TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
-  }
-  {
-    BI opval = temp1;
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SUBX) : /* subx $dr,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_add.f
-#define OPRND(f) par_exec->operands.sfmt_addx.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-  * FLD (i_dr) = OPRND (dr);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_TRAP) : /* trap $uimm4 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_trap.f
-#define OPRND(f) par_exec->operands.sfmt_trap.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-  {
-    USI opval = GET_H_CR (((UINT) 6));
-    OPRND (h_cr_USI_14) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    USI opval = ADDSI (pc, 4);
-    OPRND (h_cr_USI_6) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-  {
-    UQI opval = CPU (h_bpsw);
-    OPRND (h_bbpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
-  }
-  {
-    UQI opval = GET_H_PSW ();
-    OPRND (h_bpsw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
-  }
-  {
-    UQI opval = ANDQI (GET_H_PSW (), 128);
-    OPRND (h_psw_UQI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
-  }
-  {
-    SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
-    OPRND (pc) = opval;
-    TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
-  }
-}
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_TRAP) : /* trap $uimm4 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_trap.f
-#define OPRND(f) par_exec->operands.sfmt_trap.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    SEM_BRANCH_INIT
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_bbpsw) = OPRND (h_bbpsw_UQI);
-  CPU (h_bpsw) = OPRND (h_bpsw_UQI);
-  SET_H_CR (((UINT) 14), OPRND (h_cr_USI_14));
-  SET_H_CR (((UINT) 6), OPRND (h_cr_USI_6));
-  SET_H_PSW (OPRND (h_psw_UQI));
-  SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
-
-  SEM_BRANCH_FINI (vpc);
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_UNLOCK) : /* unlock $src1,@$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_unlock.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-{
-if (CPU (h_lock)) {
-  {
-    SI opval = * FLD (i_src1);
-    OPRND (h_memory_SI_src2_idx) = * FLD (i_src2);
-    OPRND (h_memory_SI_src2) = opval;
-    written |= (1 << 4);
-    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
-  }
-}
-  {
-    BI opval = 0;
-    OPRND (h_lock_BI) = opval;
-    TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
-  }
-}
-
-  abuf->written = written;
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_UNLOCK) : /* unlock $src1,@$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_unlock.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_lock) = OPRND (h_lock_BI);
-  if (written & (1 << 4))
-    {
-      SETMEMSI (current_cpu, pc, OPRND (h_memory_SI_src2_idx), OPRND (h_memory_SI_src2));
-    }
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_PCMPBZ) : /* pcmpbz $src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = (EQSI (ANDSI (* FLD (i_src2), 255), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 65280), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (* FLD (i_src2), 0xff000000), 0)) ? (1) : (0);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_PCMPBZ) : /* pcmpbz $src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_cmpz.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SADD) : /* sadd */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sadd.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0)));
-    OPRND (h_accums_DI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SADD) : /* sadd */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sadd.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_DI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACWU1) : /* macwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACWU1) : /* macwu1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MSBLO) : /* msblo $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_msblo.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8);
-    OPRND (accum) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MSBLO) : /* msblo $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_msblo.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUM (OPRND (accum));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MULWU1) : /* mulwu1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MULWU1) : /* mulwu1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_mulwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_MACLH1) : /* maclh1 $src1,$src2 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8);
-    OPRND (h_accums_DI_1) = opval;
-    TRACE_RESULT (current_cpu, abuf, "accums", 'D', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_MACLH1) : /* maclh1 $src1,$src2 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_st_plus.f
-#define OPRND(f) par_exec->operands.sfmt_macwu1.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_DI_1));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SC) : /* sc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (CPU (h_cond)))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SC) : /* sc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SNC) : /* snc */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-if (ZEXTBISI (NOTBI (CPU (h_cond))))
-  SEM_SKIP_INSN (current_cpu, sem_arg, vpc);
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SNC) : /* snc */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.fmt_empty.f
-#define OPRND(f) par_exec->operands.sfmt_sc.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_CLRPSW) : /* clrpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = ANDSI (GET_H_CR (((UINT) 0)), ORSI (INVBI (FLD (f_uimm8)), 65280));
-    OPRND (h_cr_USI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_CLRPSW) : /* clrpsw $uimm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_clrpsw.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_SETPSW) : /* setpsw $uimm8 */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_setpsw.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    SI opval = FLD (f_uimm8);
-    OPRND (h_cr_USI_0) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cr", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_SETPSW) : /* setpsw $uimm8 */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_clrpsw.f
-#define OPRND(f) par_exec->operands.sfmt_setpsw.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  SET_H_CR (((UINT) 0), OPRND (h_cr_USI_0));
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-  CASE (sem, INSN_PAR_BTST) : /* btst $uimm3,$sr */
-{
-  SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-  ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_bset.f
-#define OPRND(f) par_exec->operands.sfmt_btst.f
-  int UNUSED written = 0;
-  IADDR UNUSED pc = abuf->addr;
-  vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
-
-  {
-    BI opval = ANDQI (SRLSI (* FLD (i_sr), SUBSI (7, FLD (f_uimm3))), 1);
-    OPRND (condbit) = opval;
-    TRACE_RESULT (current_cpu, abuf, "cond", 'x', opval);
-  }
-
-#undef OPRND
-#undef FLD
-}
-  NEXT (vpc);
-
-CASE (sem, INSN_WRITE_BTST) : /* btst $uimm3,$sr */
-  {
-    SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
-    const ARGBUF *abuf = SEM_ARGBUF (sem_arg)->fields.write.abuf;
-#define FLD(f) abuf->fields.sfmt_bset.f
-#define OPRND(f) par_exec->operands.sfmt_btst.f
-    int UNUSED written = abuf->written;
-    IADDR UNUSED pc = abuf->addr;
-    vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
-
-  CPU (h_cond) = OPRND (condbit);
-
-#undef OPRND
-#undef FLD
-  }
-  NEXT (vpc);
-
-
-    }
-  ENDSWITCH (sem) /* End of semantic switch.  */
-
-  /* At this point `vpc' contains the next insn to execute.  */
-}
-
-#undef DEFINE_SWITCH
-#endif /* DEFINE_SWITCH */
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
deleted file mode 100644
index f8bbece..0000000
--- a/sim/m32r/sim-if.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* Main simulator entry points specific to the M32R.
-   Copyright (C) 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-#include "sim-options.h"
-#include "libiberty.h"
-#include "bfd.h"
-
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-
-static void free_state (SIM_DESC);
-static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
-
-/* Records simulator descriptor so utilities like m32r_dump_regs can be
-   called from gdb.  */
-SIM_DESC current_state;
-
-/* Cover function of sim_state_free to free the cpu buffers as well.  */
-
-static void
-free_state (SIM_DESC sd)
-{
-  if (STATE_MODULES (sd) != NULL)
-    sim_module_uninstall (sd);
-  sim_cpu_free_all (sd);
-  sim_state_free (sd);
-}
-
-/* Create an instance of the simulator.  */
-
-SIM_DESC
-sim_open (kind, callback, abfd, argv)
-     SIM_OPEN_KIND kind;
-     host_callback *callback;
-     struct bfd *abfd;
-     char **argv;
-{
-  SIM_DESC sd = sim_state_alloc (kind, callback);
-  char c;
-  int i;
-
-  /* The cpu data is kept in a separately allocated chunk of memory.  */
-  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#if 0 /* FIXME: pc is in mach-specific struct */
-  /* FIXME: watchpoints code shouldn't need this */
-  {
-    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-    STATE_WATCHPOINTS (sd)->pc = &(PC);
-    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
-  }
-#endif
-
-  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-#ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */
-  if (dv_sockser_install (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-#endif
-
-#if 0 /* FIXME: 'twould be nice if we could do this */
-  /* These options override any module options.
-     Obviously ambiguity should be avoided, however the caller may wish to
-     augment the meaning of an option.  */
-  if (extra_options != NULL)
-    sim_add_option_table (sd, extra_options);
-#endif
-
-  /* getopt will print the error message so we just have to exit if this fails.
-     FIXME: Hmmm...  in the case of gdb we need getopt to call
-     print_filtered.  */
-  if (sim_parse_args (sd, argv) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Allocate a handler for the control registers and other devices
-     if no memory for that range has been allocated by the user.
-     All are allocated in one chunk to keep things from being
-     unnecessarily complicated.  */
-  if (sim_core_read_buffer (sd, NULL, read_map, &c, M32R_DEVICE_ADDR, 1) == 0)
-    sim_core_attach (sd, NULL,
-		     0 /*level*/,
-		     access_read_write,
-		     0 /*space ???*/,
-		     M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/,
-		     0 /*modulo*/,
-		     &m32r_devices,
-		     NULL /*buffer*/);
-
-  /* Allocate core managed memory if none specified by user.
-     Use address 4 here in case the user wanted address 0 unmapped.  */
-  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
-    sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
-
-  /* check for/establish the reference program image */
-  if (sim_analyze_program (sd,
-			   (STATE_PROG_ARGV (sd) != NULL
-			    ? *STATE_PROG_ARGV (sd)
-			    : NULL),
-			   abfd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Establish any remaining configuration options.  */
-  if (sim_config (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  if (sim_post_argv_init (sd) != SIM_RC_OK)
-    {
-      free_state (sd);
-      return 0;
-    }
-
-  /* Open a copy of the cpu descriptor table.  */
-  {
-    CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
-					     CGEN_ENDIAN_BIG);
-    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
-      {
-	SIM_CPU *cpu = STATE_CPU (sd, i);
-	CPU_CPU_DESC (cpu) = cd;
-	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
-      }
-    m32r_cgen_init_dis (cd);
-  }
-
-  /* Initialize various cgen things not done by common framework.
-     Must be done after m32r_cgen_cpu_open.  */
-  cgen_init (sd);
-
-  for (c = 0; c < MAX_NR_PROCESSORS; ++c)
-    {
-      /* Only needed for profiling, but the structure member is small.  */
-      memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
-	      sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
-      /* Hook in callback for reporting these stats */
-      PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
-	= print_m32r_misc_cpu;
-    }
-
-  /* Store in a global so things like sparc32_dump_regs can be invoked
-     from the gdb command line.  */
-  current_state = sd;
-
-  return sd;
-}
-
-void
-sim_close (sd, quitting)
-     SIM_DESC sd;
-     int quitting;
-{
-  m32r_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
-  sim_module_uninstall (sd);
-}
-
-SIM_RC
-sim_create_inferior (sd, abfd, argv, envp)
-     SIM_DESC sd;
-     struct bfd *abfd;
-     char **argv;
-     char **envp;
-{
-  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
-  SIM_ADDR addr;
-
-  if (abfd != NULL)
-    addr = bfd_get_start_address (abfd);
-  else
-    addr = 0;
-  sim_pc_set (current_cpu, addr);
-
-#ifdef M32R_LINUX
-  m32rbf_h_cr_set (current_cpu,
-                    m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
-  m32rbf_h_cr_set (current_cpu,
-                    m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
-#endif
-
-#if 0
-  STATE_ARGV (sd) = sim_copy_argv (argv);
-  STATE_ENVP (sd) = sim_copy_argv (envp);
-#endif
-
-  return SIM_RC_OK;
-}
-
-/* PROFILE_CPU_CALLBACK */
-
-static void
-print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
-{
-  SIM_DESC sd = CPU_STATE (cpu);
-  char buf[20];
-
-  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
-    {
-      sim_io_printf (sd, "Miscellaneous Statistics\n\n");
-      sim_io_printf (sd, "  %-*s %s\n\n",
-		     PROFILE_LABEL_WIDTH, "Fill nops:",
-		     sim_add_commas (buf, sizeof (buf),
-				     CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
-      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
-	sim_io_printf (sd, "  %-*s %s\n\n",
-		       PROFILE_LABEL_WIDTH, "Parallel insns:",
-		       sim_add_commas (buf, sizeof (buf),
-				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
-      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
-	sim_io_printf (sd, "  %-*s %s\n\n",
-		       PROFILE_LABEL_WIDTH, "Parallel insns:",
-		       sim_add_commas (buf, sizeof (buf),
-				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
-    }
-}
-
-void
-sim_do_command (sd, cmd)
-     SIM_DESC sd;
-     char *cmd;
-{ 
-  char **argv;
-
-  if (cmd == NULL)
-    return;
-
-  argv = buildargv (cmd);
-
-  if (argv[0] != NULL
-      && strcasecmp (argv[0], "info") == 0
-      && argv[1] != NULL
-      && strncasecmp (argv[1], "reg", 3) == 0)
-    {
-      SI val;
-
-      /* We only support printing bbpsw,bbpc here as there is no equivalent
-	 functionality in gdb.  */
-      if (argv[2] == NULL)
-	sim_io_eprintf (sd, "Missing register in `%s'\n", cmd);
-      else if (argv[3] != NULL)
-	sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd);
-      else if (strcasecmp (argv[2], "bbpsw") == 0)
-	{
-	  val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
-	  sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val);
-	}
-      else if (strcasecmp (argv[2], "bbpc") == 0)
-	{
-	  val = m32rbf_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
-	  sim_io_printf (sd, "bbpc 0x%x %d\n", val, val);
-	}
-      else
-	sim_io_eprintf (sd, "Printing of register `%s' not supported with `sim info'\n",
-			argv[2]);
-    }
-  else
-    {
-      if (sim_args_command (sd, cmd) != SIM_RC_OK)
-	sim_io_eprintf (sd, "Unknown sim command `%s'\n", cmd);
-    }
-
-  freeargv (argv);
-}
diff --git a/sim/m32r/sim-main.h b/sim/m32r/sim-main.h
deleted file mode 100644
index 2cbb40b..0000000
--- a/sim/m32r/sim-main.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* Main header for the m32r.  */
-
-#ifndef SIM_MAIN_H
-#define SIM_MAIN_H
-
-#define USING_SIM_BASE_H /* FIXME: quick hack */
-
-struct _sim_cpu; /* FIXME: should be in sim-basics.h */
-typedef struct _sim_cpu SIM_CPU;
-
-#include "symcat.h"
-#include "sim-basics.h"
-#include "cgen-types.h"
-#include "m32r-desc.h"
-#include "m32r-opc.h"
-#include "arch.h"
-
-/* These must be defined before sim-base.h.  */
-typedef USI sim_cia;
-
-#define CIA_GET(cpu)     CPU_PC_GET (cpu)
-#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
-
-#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
-do { \
-  if (cpu) /* null if ctrl-c */ \
-    sim_pc_set ((cpu), (cia)); \
-} while (0)
-#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
-do { \
-  sim_pc_set ((cpu), (cia)); \
-} while (0)
-
-#include "sim-base.h"
-#include "cgen-sim.h"
-#include "m32r-sim.h"
-#include "opcode/cgen.h"
-
-/* The _sim_cpu struct.  */
-
-struct _sim_cpu {
-  /* sim/common cpu base.  */
-  sim_cpu_base base;
-
-  /* Static parts of cgen.  */
-  CGEN_CPU cgen_cpu;
-
-  M32R_MISC_PROFILE m32r_misc_profile;
-#define CPU_M32R_MISC_PROFILE(cpu) (& (cpu)->m32r_misc_profile)
-
-  /* CPU specific parts go here.
-     Note that in files that don't need to access these pieces WANT_CPU_FOO
-     won't be defined and thus these parts won't appear.  This is ok in the
-     sense that things work.  It is a source of bugs though.
-     One has to of course be careful to not take the size of this
-     struct and no structure members accessed in non-cpu specific files can
-     go after here.  Oh for a better language.  */
-#if defined (WANT_CPU_M32RBF)
-  M32RBF_CPU_DATA cpu_data;
-#endif
-#if defined (WANT_CPU_M32RXF)
-  M32RXF_CPU_DATA cpu_data;
-#elif defined (WANT_CPU_M32R2F)
-  M32R2F_CPU_DATA cpu_data;
-#endif
-};
-
-/* The sim_state struct.  */
-
-struct sim_state {
-  sim_cpu *cpu;
-#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
-
-  CGEN_STATE cgen_state;
-
-  sim_state_base base;
-};
-
-/* Misc.  */
-
-/* Catch address exceptions.  */
-extern SIM_CORE_SIGNAL_FN m32r_core_signal;
-#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
-m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
-		  (TRANSFER), (ERROR))
-
-/* Default memory size.  */
-#ifdef M32R_LINUX
-#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
-#else
-#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
-#endif
-
-#endif /* SIM_MAIN_H */
diff --git a/sim/m32r/syscall.h b/sim/m32r/syscall.h
deleted file mode 100644
index 3f4252a..0000000
--- a/sim/m32r/syscall.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_exit		  1
-#define __NR_fork		  2
-#define __NR_read		  3
-#define __NR_write		  4
-#define __NR_open		  5
-#define __NR_close		  6
-#define __NR_waitpid		  7
-#define __NR_creat		  8
-#define __NR_link		  9
-#define __NR_unlink		 10
-#define __NR_execve		 11
-#define __NR_chdir		 12
-#define __NR_time		 13
-#define __NR_mknod		 14
-#define __NR_chmod		 15
-#define __NR_lchown		 16
-#define __NR_break		 17
-#define __NR_oldstat		 18
-#define __NR_lseek		 19
-#define __NR_getpid		 20
-#define __NR_mount		 21
-#define __NR_umount		 22
-#define __NR_setuid		 23
-#define __NR_getuid		 24
-#define __NR_stime		 25
-#define __NR_ptrace		 26
-#define __NR_alarm		 27
-#define __NR_oldfstat		 28
-#define __NR_pause		 29
-#define __NR_utime		 30
-#define __NR_stty		 31
-#define __NR_gtty		 32
-#define __NR_access		 33
-#define __NR_nice		 34
-#define __NR_ftime		 35
-#define __NR_sync		 36
-#define __NR_kill		 37
-#define __NR_rename		 38
-#define __NR_mkdir		 39
-#define __NR_rmdir		 40
-#define __NR_dup		 41
-#define __NR_pipe		 42
-#define __NR_times		 43
-#define __NR_prof		 44
-#define __NR_brk		 45
-#define __NR_setgid		 46
-#define __NR_getgid		 47
-#define __NR_signal		 48
-#define __NR_geteuid		 49
-#define __NR_getegid		 50
-#define __NR_acct		 51
-#define __NR_umount2		 52
-#define __NR_lock		 53
-#define __NR_ioctl		 54
-#define __NR_fcntl		 55
-#define __NR_mpx		 56
-#define __NR_setpgid		 57
-#define __NR_ulimit		 58
-#define __NR_oldolduname	 59
-#define __NR_umask		 60
-#define __NR_chroot		 61
-#define __NR_ustat		 62
-#define __NR_dup2		 63
-#define __NR_getppid		 64
-#define __NR_getpgrp		 65
-#define __NR_setsid		 66
-#define __NR_sigaction		 67
-#define __NR_sgetmask		 68
-#define __NR_ssetmask		 69
-#define __NR_setreuid		 70
-#define __NR_setregid		 71
-#define __NR_sigsuspend		 72
-#define __NR_sigpending		 73
-#define __NR_sethostname	 74
-#define __NR_setrlimit		 75
-#define __NR_getrlimit		 76
-#define __NR_getrusage		 77
-#define __NR_gettimeofday	 78
-#define __NR_settimeofday	 79
-#define __NR_getgroups		 80
-#define __NR_setgroups		 81
-#define __NR_select		 82
-#define __NR_symlink		 83
-#define __NR_oldlstat		 84
-#define __NR_readlink		 85
-#define __NR_uselib		 86
-#define __NR_swapon		 87
-#define __NR_reboot		 88
-#define __NR_readdir		 89
-#define __NR_mmap		 90
-#define __NR_munmap		 91
-#define __NR_truncate		 92
-#define __NR_ftruncate		 93
-#define __NR_fchmod		 94
-#define __NR_fchown		 95
-#define __NR_getpriority	 96
-#define __NR_setpriority	 97
-#define __NR_profil		 98
-#define __NR_statfs		 99
-#define __NR_fstatfs		100
-#define __NR_ioperm		101
-#define __NR_socketcall		102
-#define __NR_syslog		103
-#define __NR_setitimer		104
-#define __NR_getitimer		105
-#define __NR_stat		106
-#define __NR_lstat		107
-#define __NR_fstat		108
-#define __NR_olduname		109
-#define __NR_iopl		110
-#define __NR_vhangup		111
-#define __NR_idle		112
-#define __NR_vm86old		113
-#define __NR_wait4		114
-#define __NR_swapoff		115
-#define __NR_sysinfo		116
-#define __NR_ipc		117
-#define __NR_fsync		118
-#define __NR_sigreturn		119
-#define __NR_clone		120
-#define __NR_setdomainname	121
-#define __NR_uname		122
-#define __NR_modify_ldt		123
-#define __NR_adjtimex		124
-#define __NR_mprotect		125
-#define __NR_sigprocmask	126
-#define __NR_create_module	127
-#define __NR_init_module	128
-#define __NR_delete_module	129
-#define __NR_get_kernel_syms	130
-#define __NR_quotactl		131
-#define __NR_getpgid		132
-#define __NR_fchdir		133
-#define __NR_bdflush		134
-#define __NR_sysfs		135
-#define __NR_personality	136
-#define __NR_afs_syscall	137 /* Syscall for Andrew File System */
-#define __NR_setfsuid		138
-#define __NR_setfsgid		139
-#define __NR__llseek		140
-#define __NR_getdents		141
-#define __NR__newselect		142
-#define __NR_flock		143
-#define __NR_msync		144
-#define __NR_readv		145
-#define __NR_writev		146
-#define __NR_getsid		147
-#define __NR_fdatasync		148
-#define __NR__sysctl		149
-#define __NR_mlock		150
-#define __NR_munlock		151
-#define __NR_mlockall		152
-#define __NR_munlockall		153
-#define __NR_sched_setparam		154
-#define __NR_sched_getparam		155
-#define __NR_sched_setscheduler		156
-#define __NR_sched_getscheduler		157
-#define __NR_sched_yield		158
-#define __NR_sched_get_priority_max	159
-#define __NR_sched_get_priority_min	160
-#define __NR_sched_rr_get_interval	161
-#define __NR_nanosleep		162
-#define __NR_mremap		163
-#define __NR_setresuid		164
-#define __NR_getresuid		165
-#define __NR_vm86		166
-#define __NR_query_module	167
-#define __NR_poll		168
-#define __NR_nfsservctl		169
-#define __NR_setresgid		170
-#define __NR_getresgid		171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn	173
-#define __NR_rt_sigaction	174
-#define __NR_rt_sigprocmask	175
-#define __NR_rt_sigpending	176
-#define __NR_rt_sigtimedwait	177
-#define __NR_rt_sigqueueinfo	178
-#define __NR_rt_sigsuspend	179
-#define __NR_pread		180
-#define __NR_pwrite		181
-#define __NR_chown		182
-#define __NR_getcwd		183
-#define __NR_capget		184
-#define __NR_capset		185
-#define __NR_sigaltstack	186
-#define __NR_sendfile		187
-#define __NR_getpmsg		188	/* some people actually want streams */
-#define __NR_putpmsg		189	/* some people actually want streams */
-#define __NR_vfork		190
-
-#define __NR_pread64		180
-#define __NR_pwrite64		181
-
-#define __NR_ugetrlimit		191	/* SuS compliant getrlimit */
-#define __NR_mmap2		192
-#define __NR_truncate64		193
-#define __NR_ftruncate64	194
-#define __NR_stat64		195
-#define __NR_lstat64		196
-#define __NR_fstat64		197
-#define __NR_lchown32		198
-#define __NR_getuid32		199
-#define __NR_getgid32		200
-#define __NR_geteuid32		201
-#define __NR_getegid32		202
-#define __NR_setreuid32		203
-#define __NR_setregid32		204
-#define __NR_getgroups32	205
-#define __NR_setgroups32	206
-#define __NR_fchown32		207
-#define __NR_setresuid32	208
-#define __NR_getresuid32	209
-#define __NR_setresgid32	210
-#define __NR_getresgid32	211
-#define __NR_chown32		212
-#define __NR_setuid32		213
-#define __NR_setgid32		214
-#define __NR_setfsuid32		215
-#define __NR_setfsgid32		216
-#define __NR_pivot_root		217
-#define __NR_mincore		218
-#define __NR_madvise		219
-#define __NR_madvise1		219	/* delete when C lib stub is removed */
-#define __NR_getdents64		220
-#define __NR_fcntl64		221
-/* 223 is unused */
-#define __NR_gettid		224
-#define __NR_readahead		225
-#define __NR_setxattr		226
-#define __NR_lsetxattr		227
-#define __NR_fsetxattr		228
-#define __NR_getxattr		229
-#define __NR_lgetxattr		230
-#define __NR_fgetxattr		231
-#define __NR_listxattr		232
-#define __NR_llistxattr		233
-#define __NR_flistxattr		234
-#define __NR_removexattr	235
-#define __NR_lremovexattr	236
-#define __NR_fremovexattr	237
-#define __NR_tkill		238
-#define __NR_sendfile64		239
-#define __NR_futex		240
-#define __NR_sched_setaffinity	241
-#define __NR_sched_getaffinity	242
-#define __NR_set_thread_area	243
-#define __NR_get_thread_area	244
-#define __NR_io_setup		245
-#define __NR_io_destroy		246
-#define __NR_io_getevents	247
-#define __NR_io_submit		248
-#define __NR_io_cancel		249
-#define __NR_fadvise64		250
-
-#define __NR_exit_group		252
-#define __NR_lookup_dcookie	253
-#define __NR_epoll_create	254
-#define __NR_epoll_ctl		255
-#define __NR_epoll_wait		256
-#define __NR_remap_file_pages	257
-#define __NR_set_tid_address	258
-#define __NR_timer_create	259
-#define __NR_timer_settime	(__NR_timer_create+1)
-#define __NR_timer_gettime	(__NR_timer_create+2)
-#define __NR_timer_getoverrun	(__NR_timer_create+3)
-#define __NR_timer_delete	(__NR_timer_create+4)
-#define __NR_clock_settime	(__NR_timer_create+5)
-#define __NR_clock_gettime	(__NR_timer_create+6)
-#define __NR_clock_getres	(__NR_timer_create+7)
-#define __NR_clock_nanosleep	(__NR_timer_create+8)
-#define __NR_statfs64		268
-#define __NR_fstatfs64		269
-#define __NR_tgkill		270
-#define __NR_utimes		271
-#define __NR_fadvise64_64	272
-#define __NR_vserver		273
diff --git a/sim/m32r/tconfig.in b/sim/m32r/tconfig.in
deleted file mode 100644
index f2599e3..0000000
--- a/sim/m32r/tconfig.in
+++ /dev/null
@@ -1,47 +0,0 @@
-/* M32R target configuration file.  -*- C -*- */
-
-#ifndef M32R_TCONFIG_H
-#define M32R_TCONFIG_H
-
-/* Define this if the simulator can vary the size of memory.
-   See the xxx simulator for an example.
-   This enables the `-m size' option.
-   The memory size is stored in STATE_MEM_SIZE.  */
-/* Not used for M32R since we use the memory module.  */
-/* #define SIM_HAVE_MEM_SIZE */
-
-/* See sim-hload.c.  We properly handle LMA.  */
-#define SIM_HANDLES_LMA 1
-
-/* For MSPR support.  FIXME: revisit.  */
-#define WITH_DEVICES 1
-
-/* FIXME: Revisit.  */
-#ifdef HAVE_DV_SOCKSER
-MODULE_INSTALL_FN dv_sockser_install;
-#define MODULE_LIST dv_sockser_install,
-#endif
-
-#if 0
-/* Enable watchpoints.  */
-#define WITH_WATCHPOINTS 1
-#endif
-
-/* Define this to enable the intrinsic breakpoint mechanism. */
-/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
-   duplicates ifdef SIM_BREAKPOINT (right?) */
-#if 0
-#define SIM_HAVE_BREAKPOINTS
-#define SIM_BREAKPOINT { 0x10, 0xf1 }
-#define SIM_BREAKPOINT_SIZE 2
-#endif
-#if 0
-#define HAVE_DV_SOCKSER
-#endif
-
-/* This is a global setting.  Different cpu families can't mix-n-match -scache
-   and -pbb.  However some cpu families may use -simple while others use
-   one of -scache/-pbb.  */
-#define WITH_SCACHE_PBB 1
-
-#endif /* M32R_TCONFIG_H */
diff --git a/sim/m32r/traps-linux.c b/sim/m32r/traps-linux.c
deleted file mode 100644
index f5b6783..0000000
--- a/sim/m32r/traps-linux.c
+++ /dev/null
@@ -1,1389 +0,0 @@
-/* m32r exception, interrupt, and trap (EIT) support
-   Copyright (C) 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Renesas.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-#include "syscall.h"
-#include "targ-vals.h"
-#include <dirent.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <time.h>
-#include <unistd.h>
-#include <utime.h>
-#include <sys/mman.h>
-#include <sys/poll.h>
-#include <sys/resource.h>
-#include <sys/sysinfo.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include <sys/timeb.h>
-#include <sys/timex.h>
-#include <sys/types.h>
-#include <sys/uio.h>
-#include <sys/utsname.h>
-#include <sys/vfs.h>
-#include <linux/sysctl.h>
-#include <linux/types.h>
-#include <linux/unistd.h>
-
-#define TRAP_ELF_SYSCALL 0
-#define TRAP_LINUX_SYSCALL 2
-#define TRAP_FLUSH_CACHE 12
-
-/* The semantic code invokes this for invalid (unrecognized) instructions.  */
-
-SEM_PC
-sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-
-#if 0
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      h_bsm_set (current_cpu, h_sm_get (current_cpu));
-      h_bie_set (current_cpu, h_ie_get (current_cpu));
-      h_bcond_set (current_cpu, h_cond_get (current_cpu));
-      /* sm not changed */
-      h_ie_set (current_cpu, 0);
-      h_cond_set (current_cpu, 0);
-
-      h_bpc_set (current_cpu, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-			  EIT_RSVD_INSN_ADDR);
-    }
-  else
-#endif
-    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
-  return vpc;
-}
-
-/* Process an address exception.  */
-
-void
-m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
-		  unsigned int map, int nr_bytes, address_word addr,
-		  transfer_type transfer, sim_core_signals sig)
-{
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
-                       m32rbf_h_cr_get (current_cpu, H_CR_BPC));
-      if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
-        {
-          m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
-          /* sm not changed */
-          m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
-        }
-      else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
-        {
-          m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
-          /* sm not changed */
-          m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
-        }
-      else
-        {
-          m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
-          /* sm not changed */
-          m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
-        }
-      m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-                          EIT_ADDR_EXCP_ADDR);
-    }
-  else
-    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
-                     transfer, sig);
-}
-
-/* Read/write functions for system call interface.  */
-
-static int
-syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
-		  unsigned long taddr, char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
-}
-
-static int
-syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
-		   unsigned long taddr, const char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
-}
-
-/* Translate target's address to host's address.  */
-
-static void *
-t2h_addr (host_callback *cb, struct cb_syscall *sc,
-          unsigned long taddr)
-{
-  extern sim_core_trans_addr (SIM_DESC, sim_cpu *, unsigned, address_word);
-  void *addr;
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  if (taddr == 0)
-    return NULL;
-
-  return sim_core_trans_addr (sd, cpu, read_map, taddr);
-}
-
-static unsigned int
-conv_endian (unsigned int tvalue)
-{
-  unsigned int hvalue;
-  unsigned int t1, t2, t3, t4;
-
-  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
-    {
-      t1 = tvalue & 0xff000000;
-      t2 = tvalue & 0x00ff0000;
-      t3 = tvalue & 0x0000ff00;
-      t4 = tvalue & 0x000000ff;
-
-      hvalue =  t1 >> 24;
-      hvalue += t2 >> 8;
-      hvalue += t3 << 8;
-      hvalue += t4 << 24;
-    }
-  else
-    hvalue = tvalue;
-
-  return hvalue;
-}
-
-static unsigned short
-conv_endian16 (unsigned short tvalue)
-{
-  unsigned short hvalue;
-  unsigned short t1, t2;
-
-  if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
-    {
-      t1 = tvalue & 0xff00;
-      t2 = tvalue & 0x00ff;
-
-      hvalue =  t1 >> 8;
-      hvalue += t2 << 8;
-    }
-  else
-    hvalue = tvalue;
-
-  return hvalue;
-}
-
-static void
-translate_endian(void *addr, size_t size)
-{
-  unsigned int *p = (unsigned int *) addr;
-  int i;
-  
-  for (i = 0; i <= size - 4; i += 4,p++)
-    *p = conv_endian(*p);
-  
-  if (i <= size - 2)
-    *((unsigned short *) p) = conv_endian16(*((unsigned short *) p));
-}
-
-/* Trap support.
-   The result is the pc address to continue at.
-   Preprocessing like saving the various registers has already been done.  */
-
-USI
-m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-  host_callback *cb = STATE_CALLBACK (sd);
-
-#ifdef SIM_HAVE_BREAKPOINTS
-  /* Check for breakpoints "owned" by the simulator first, regardless
-     of --environment.  */
-  if (num == TRAP_BREAKPOINT)
-    {
-      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
-	 it doesn't return.  Otherwise it returns and let's us try.  */
-      sim_handle_breakpoint (sd, current_cpu, pc);
-      /* Fall through.  */
-    }
-#endif
-
-  switch (num)
-    {
-    case TRAP_ELF_SYSCALL :
-      {
-        CB_SYSCALL s;
- 
-        CB_SYSCALL_INIT (&s);
-        s.func = m32rbf_h_gr_get (current_cpu, 0);
-        s.arg1 = m32rbf_h_gr_get (current_cpu, 1);
-        s.arg2 = m32rbf_h_gr_get (current_cpu, 2);
-        s.arg3 = m32rbf_h_gr_get (current_cpu, 3);
- 
-        if (s.func == TARGET_SYS_exit)
-          {
-            sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
-          }
- 
-        s.p1 = (PTR) sd;
-        s.p2 = (PTR) current_cpu;
-        s.read_mem = syscall_read_mem;
-        s.write_mem = syscall_write_mem;
-        cb_syscall (cb, &s);
-        m32rbf_h_gr_set (current_cpu, 2, s.errcode);
-        m32rbf_h_gr_set (current_cpu, 0, s.result);
-        m32rbf_h_gr_set (current_cpu, 1, s.result2);
-        break;
-      }
-
-    case TRAP_LINUX_SYSCALL :
-      {
-	CB_SYSCALL s;
-        unsigned int func, arg1, arg2, arg3, arg4, arg5, arg6, arg7;
-        int result, result2, errcode;
-
-        if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-          {
-            /* The new pc is the trap vector entry.
-               We assume there's a branch there to some handler.
-	       Use cr5 as EVB (EIT Vector Base) register.  */
-            USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
-            return new_pc;
-          }
-
-	func = m32rbf_h_gr_get (current_cpu, 7);
-	arg1 = m32rbf_h_gr_get (current_cpu, 0);
-	arg2 = m32rbf_h_gr_get (current_cpu, 1);
-	arg3 = m32rbf_h_gr_get (current_cpu, 2);
-	arg4 = m32rbf_h_gr_get (current_cpu, 3);
-	arg5 = m32rbf_h_gr_get (current_cpu, 4);
-	arg6 = m32rbf_h_gr_get (current_cpu, 5);
-	arg7 = m32rbf_h_gr_get (current_cpu, 6);
-
-        CB_SYSCALL_INIT (&s);
-        s.func = func;
-        s.arg1 = arg1;
-        s.arg2 = arg2;
-        s.arg3 = arg3;
-
-        s.p1 = (PTR) sd;
-        s.p2 = (PTR) current_cpu;
-        s.read_mem = syscall_read_mem;
-        s.write_mem = syscall_write_mem;
-
-        result = 0;
-        result2 = 0;
-        errcode = 0;
-
-        switch (func)
-          {
-          case __NR_exit:
-	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, arg1);
-            break;
-
-          case __NR_read:
-            result = read(arg1, t2h_addr(cb, &s, arg2), arg3);
-            errcode = errno;
-            break;
-
-          case __NR_write:
-            result = write(arg1, t2h_addr(cb, &s, arg2), arg3);
-            errcode = errno;
-            break;
-
-          case __NR_open:
-            result = open((char *) t2h_addr(cb, &s, arg1), arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_close:
-            result = close(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_creat:
-            result = creat((char *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_link:
-            result = link((char *) t2h_addr(cb, &s, arg1),
-                          (char *) t2h_addr(cb, &s, arg2));
-            errcode = errno;
-            break;
-
-          case __NR_unlink:
-            result = unlink((char *) t2h_addr(cb, &s, arg1));
-            errcode = errno;
-            break;
-
-          case __NR_chdir:
-            result = chdir((char *) t2h_addr(cb, &s, arg1));
-            errcode = errno;
-            break;
-
-          case __NR_time:
-            {
-              time_t t;
-
-              if (arg1 == 0)
-                {
-                  result = (int) time(NULL);
-                  errcode = errno;
-                }
-              else
-                {
-                  result = (int) time(&t);
-                  errcode = errno;
-
-                  if (result != 0)
-                    break;
-
-                  translate_endian((void *) &t, sizeof(t));
-                  if ((s.write_mem) (cb, &s, arg1, (char *) &t, sizeof(t)) != sizeof(t))
-                    {
-                      result = -1;
-                      errcode = EINVAL;
-                    }
-                }
-            }
-            break;
-
-          case __NR_mknod:
-            result = mknod((char *) t2h_addr(cb, &s, arg1),
-                           (mode_t) arg2, (dev_t) arg3);
-            errcode = errno;
-            break;
-
-          case __NR_chmod:
-            result = chmod((char *) t2h_addr(cb, &s, arg1), (mode_t) arg2);
-            errcode = errno;
-            break;
-
-          case __NR_lchown32:
-          case __NR_lchown:
-            result = lchown((char *) t2h_addr(cb, &s, arg1),
-                            (uid_t) arg2, (gid_t) arg3);
-            errcode = errno;
-            break;
-
-          case __NR_lseek:
-            result = (int) lseek(arg1, (off_t) arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_getpid:
-            result = getpid();
-            errcode = errno;
-            break;
-
-          case __NR_getuid32:
-          case __NR_getuid:
-            result = getuid();
-            errcode = errno;
-            break;
-
-          case __NR_utime:
-            {
-              struct utimbuf buf;
-
-              if (arg2 == 0)
-                {
-                  result = utime((char *) t2h_addr(cb, &s, arg1), NULL);
-                  errcode = errno;
-                }
-              else
-                {
-                  buf = *((struct utimbuf *) t2h_addr(cb, &s, arg2));
-                  translate_endian((void *) &buf, sizeof(buf));
-                  result = utime((char *) t2h_addr(cb, &s, arg1), &buf);
-                  errcode = errno;
-                }
-            }
-            break;
-
-          case __NR_access:
-            result = access((char *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_ftime:
-            {
-              struct timeb t;
-
-              result = ftime(&t);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              t.time = conv_endian(t.time);
-              t.millitm = conv_endian16(t.millitm);
-              t.timezone = conv_endian16(t.timezone);
-              t.dstflag = conv_endian16(t.dstflag);
-              if ((s.write_mem) (cb, &s, arg1, (char *) &t, sizeof(t))
-                  != sizeof(t))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-
-          case __NR_sync:
-            sync();
-            result = 0;
-            break;
-
-          case __NR_rename:
-            result = rename((char *) t2h_addr(cb, &s, arg1),
-                            (char *) t2h_addr(cb, &s, arg2));
-            errcode = errno;
-            break;
-
-          case __NR_mkdir:
-            result = mkdir((char *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_rmdir:
-            result = rmdir((char *) t2h_addr(cb, &s, arg1));
-            errcode = errno;
-            break;
-
-          case __NR_dup:
-            result = dup(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_brk:
-            result = brk((void *) arg1);
-            errcode = errno;
-            //result = arg1;
-            break;
-
-          case __NR_getgid32:
-          case __NR_getgid:
-            result = getgid();
-            errcode = errno;
-            break;
-
-          case __NR_geteuid32:
-          case __NR_geteuid:
-            result = geteuid();
-            errcode = errno;
-            break;
-
-          case __NR_getegid32:
-          case __NR_getegid:
-            result = getegid();
-            errcode = errno;
-            break;
-
-          case __NR_ioctl:
-            result = ioctl(arg1, arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_fcntl:
-            result = fcntl(arg1, arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_dup2:
-            result = dup2(arg1, arg2);
-            errcode = errno;
-            break;
-
-          case __NR_getppid:
-            result = getppid();
-            errcode = errno;
-            break;
-
-          case __NR_getpgrp:
-            result = getpgrp();
-            errcode = errno;
-            break;
-
-          case __NR_getrlimit:
-            {
-              struct rlimit rlim;
-
-              result = getrlimit(arg1, &rlim);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &rlim, sizeof(rlim));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &rlim, sizeof(rlim))
-                  != sizeof(rlim))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_getrusage:
-            {
-              struct rusage usage;
-
-              result = getrusage(arg1, &usage);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &usage, sizeof(usage));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &usage, sizeof(usage))
-                  != sizeof(usage))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_gettimeofday:
-            {
-              struct timeval tv;
-              struct timezone tz;
-              
-              result = gettimeofday(&tv, &tz);
-              errcode = errno;
-              
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &tv, sizeof(tv));
-              if ((s.write_mem) (cb, &s, arg1, (char *) &tv, sizeof(tv))
-                  != sizeof(tv))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-
-              translate_endian((void *) &tz, sizeof(tz));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &tz, sizeof(tz))
-                  != sizeof(tz))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_getgroups32:
-          case __NR_getgroups:
-            {
-              gid_t *list;
-
-              if (arg1 > 0)
-                list = (gid_t *) malloc(arg1 * sizeof(gid_t));
-
-              result = getgroups(arg1, list);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) list, arg1 * sizeof(gid_t));
-              if (arg1 > 0)
-                if ((s.write_mem) (cb, &s, arg2, (char *) list, arg1 * sizeof(gid_t))
-                    != arg1 * sizeof(gid_t))
-                  {
-                    result = -1;
-                     errcode = EINVAL;
-                  }
-            }
-            break;
-
-          case __NR_select:
-            {
-              int n;
-              fd_set readfds;
-              fd_set *treadfdsp;
-              fd_set *hreadfdsp;
-              fd_set writefds;
-              fd_set *twritefdsp;
-              fd_set *hwritefdsp;
-              fd_set exceptfds;
-              fd_set *texceptfdsp;
-              fd_set *hexceptfdsp;
-              struct timeval *ttimeoutp;
-              struct timeval timeout;
-              
-              n = arg1;
-
-              treadfdsp = (fd_set *) arg2;
-              if (treadfdsp != NULL)
-                {
-                  readfds = *((fd_set *) t2h_addr(cb, &s, (unsigned int) treadfdsp));
-                  translate_endian((void *) &readfds, sizeof(readfds));
-                  hreadfdsp = &readfds;
-                }
-              else
-                hreadfdsp = NULL;
-              
-              twritefdsp  = (fd_set *) arg3;
-              if (twritefdsp != NULL)
-                {
-                  writefds = *((fd_set *) t2h_addr(cb, &s, (unsigned int) twritefdsp));
-                  translate_endian((void *) &writefds, sizeof(writefds));
-                  hwritefdsp = &writefds;
-                }
-              else
-                hwritefdsp = NULL;
-              
-              texceptfdsp = (fd_set *) arg4;
-              if (texceptfdsp != NULL)
-                {
-                  exceptfds = *((fd_set *) t2h_addr(cb, &s, (unsigned int) texceptfdsp));
-                  translate_endian((void *) &exceptfds, sizeof(exceptfds));
-                  hexceptfdsp = &exceptfds;
-                }
-              else
-                hexceptfdsp = NULL;
-              
-              ttimeoutp = (struct timeval *) arg5;
-              timeout = *((struct timeval *) t2h_addr(cb, &s, (unsigned int) ttimeoutp));
-              translate_endian((void *) &timeout, sizeof(timeout));
-
-              result = select(n, hreadfdsp, hwritefdsp, hexceptfdsp, &timeout);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              if (treadfdsp != NULL)
-                {
-                  translate_endian((void *) &readfds, sizeof(readfds));
-                  if ((s.write_mem) (cb, &s, (unsigned long) treadfdsp,
-                       (char *) &readfds, sizeof(readfds)) != sizeof(readfds))
-                    {
-                      result = -1;
-                      errcode = EINVAL;
-                    }
-                }
-
-              if (twritefdsp != NULL)
-                {
-                  translate_endian((void *) &writefds, sizeof(writefds));
-                  if ((s.write_mem) (cb, &s, (unsigned long) twritefdsp,
-                       (char *) &writefds, sizeof(writefds)) != sizeof(writefds))
-                    {
-                      result = -1;
-                      errcode = EINVAL;
-                    }
-                }
-
-              if (texceptfdsp != NULL)
-                {
-                  translate_endian((void *) &exceptfds, sizeof(exceptfds));
-                  if ((s.write_mem) (cb, &s, (unsigned long) texceptfdsp,
-                       (char *) &exceptfds, sizeof(exceptfds)) != sizeof(exceptfds))
-                    {
-                      result = -1;
-                      errcode = EINVAL;
-                    }
-                }
-
-              translate_endian((void *) &timeout, sizeof(timeout));
-              if ((s.write_mem) (cb, &s, (unsigned long) ttimeoutp,
-                   (char *) &timeout, sizeof(timeout)) != sizeof(timeout))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_symlink:
-            result = symlink((char *) t2h_addr(cb, &s, arg1),
-                             (char *) t2h_addr(cb, &s, arg2));
-            errcode = errno;
-            break;
-
-          case __NR_readlink:
-            result = readlink((char *) t2h_addr(cb, &s, arg1),
-                              (char *) t2h_addr(cb, &s, arg2),
-                              arg3);
-            errcode = errno;
-            break;
-
-          case __NR_readdir:
-            result = (int) readdir((DIR *) t2h_addr(cb, &s, arg1));
-            errcode = errno;
-            break;
-
-#if 0
-          case __NR_mmap:
-            {
-              result = (int) mmap((void *) t2h_addr(cb, &s, arg1),
-                                  arg2, arg3, arg4, arg5, arg6);
-              errcode = errno;
-
-              if (errno == 0)
-                {
-                  sim_core_attach (sd, NULL,
-                                   0, access_read_write_exec, 0,
-                                   result, arg2, 0, NULL, NULL);
-                }
-            }
-            break;
-#endif
-          case __NR_mmap2:
-            {
-              void *addr;
-              size_t len;
-              int prot, flags, fildes;
-              off_t off;
-              
-              addr   = (void *)  t2h_addr(cb, &s, arg1);
-              len    = arg2;
-              prot   = arg3;
-              flags  = arg4;
-              fildes = arg5;
-              off    = arg6 << 12;
-
-	      result = (int) mmap(addr, len, prot, flags, fildes, off);
-              errcode = errno;
-              if (result != -1)
-                {
-                  char c;
-		  if (sim_core_read_buffer (sd, NULL, read_map, &c, result, 1) == 0)
-                    sim_core_attach (sd, NULL,
-                                     0, access_read_write_exec, 0,
-                                     result, len, 0, NULL, NULL);
-                }
-            }
-            break;
-
-          case __NR_mmap:
-            {
-              void *addr;
-              size_t len;
-              int prot, flags, fildes;
-              off_t off;
-              
-              addr   = *((void **)  t2h_addr(cb, &s, arg1));
-              len    = *((size_t *) t2h_addr(cb, &s, arg1 + 4));
-              prot   = *((int *)    t2h_addr(cb, &s, arg1 + 8));
-              flags  = *((int *)    t2h_addr(cb, &s, arg1 + 12));
-              fildes = *((int *)    t2h_addr(cb, &s, arg1 + 16));
-              off    = *((off_t *)  t2h_addr(cb, &s, arg1 + 20));
-
-              addr   = (void *) conv_endian((unsigned int) addr);
-              len    = conv_endian(len);
-              prot   = conv_endian(prot);
-              flags  = conv_endian(flags);
-              fildes = conv_endian(fildes);
-              off    = conv_endian(off);
-
-              //addr   = (void *) t2h_addr(cb, &s, (unsigned int) addr);
-              result = (int) mmap(addr, len, prot, flags, fildes, off);
-              errcode = errno;
-
-              //if (errno == 0)
-              if (result != -1)
-                {
-                  char c;
-		  if (sim_core_read_buffer (sd, NULL, read_map, &c, result, 1) == 0)
-                    sim_core_attach (sd, NULL,
-                                     0, access_read_write_exec, 0,
-                                     result, len, 0, NULL, NULL);
-                }
-            }
-            break;
-
-          case __NR_munmap:
-            {
-            result = munmap((void *)arg1, arg2);
-            errcode = errno;
-            if (result != -1)
-              {
-                sim_core_detach (sd, NULL, 0, arg2, result);
-              }
-            }
-            break;
-
-          case __NR_truncate:
-            result = truncate((char *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_ftruncate:
-            result = ftruncate(arg1, arg2);
-            errcode = errno;
-            break;
-
-          case __NR_fchmod:
-            result = fchmod(arg1, arg2);
-            errcode = errno;
-            break;
-
-          case __NR_fchown32:
-          case __NR_fchown:
-            result = fchown(arg1, arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_statfs:
-            {
-              struct statfs statbuf;
-
-              result = statfs((char *) t2h_addr(cb, &s, arg1), &statbuf);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &statbuf, sizeof(statbuf));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &statbuf, sizeof(statbuf))
-                  != sizeof(statbuf))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_fstatfs:
-            {
-              struct statfs statbuf;
-
-              result = fstatfs(arg1, &statbuf);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &statbuf, sizeof(statbuf));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &statbuf, sizeof(statbuf))
-                  != sizeof(statbuf))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_syslog:
-            result = syslog(arg1, (char *) t2h_addr(cb, &s, arg2));
-            errcode = errno;
-            break;
-
-          case __NR_setitimer:
-            {
-              struct itimerval value, ovalue;
-
-              value = *((struct itimerval *) t2h_addr(cb, &s, arg2));
-              translate_endian((void *) &value, sizeof(value));
-
-              if (arg2 == 0)
-                {
-                  result = setitimer(arg1, &value, NULL);
-                  errcode = errno;
-                }
-              else
-                {
-                  result = setitimer(arg1, &value, &ovalue);
-                  errcode = errno;
-
-                  if (result != 0)
-                    break;
-
-                  translate_endian((void *) &ovalue, sizeof(ovalue));
-                  if ((s.write_mem) (cb, &s, arg3, (char *) &ovalue, sizeof(ovalue))
-                      != sizeof(ovalue))
-                    {
-                      result = -1;
-                      errcode = EINVAL;
-                    }
-                }
-            }
-            break;
-
-          case __NR_getitimer:
-            {
-              struct itimerval value;
-
-              result = getitimer(arg1, &value);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &value, sizeof(value));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &value, sizeof(value))
-                  != sizeof(value))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_stat:
-            {
-              char *buf;
-              int buflen;
-              struct stat statbuf;
-
-              result = stat((char *) t2h_addr(cb, &s, arg1), &statbuf);
-              errcode = errno;
-              if (result < 0)
-                break;
-
-              buflen = cb_host_to_target_stat (cb, NULL, NULL);
-              buf = xmalloc (buflen);
-              if (cb_host_to_target_stat (cb, &statbuf, buf) != buflen)
-                {
-                  /* The translation failed.  This is due to an internal
-                     host program error, not the target's fault.  */
-                  free (buf);
-                  result = -1;
-                  errcode = ENOSYS;
-                  break;
-                }
-              if ((s.write_mem) (cb, &s, arg2, buf, buflen) != buflen)
-                {
-                  free (buf);
-                  result = -1;
-                  errcode = EINVAL;
-                  break;
-                }
-              free (buf);
-            }
-            break;
-
-          case __NR_lstat:
-            {
-              char *buf;
-              int buflen;
-              struct stat statbuf;
-
-              result = lstat((char *) t2h_addr(cb, &s, arg1), &statbuf);
-              errcode = errno;
-              if (result < 0)
-                break;
-
-              buflen = cb_host_to_target_stat (cb, NULL, NULL);
-              buf = xmalloc (buflen);
-              if (cb_host_to_target_stat (cb, &statbuf, buf) != buflen)
-                {
-                  /* The translation failed.  This is due to an internal
-                     host program error, not the target's fault.  */
-                  free (buf);
-                  result = -1;
-                  errcode = ENOSYS;
-                  break;
-                }
-              if ((s.write_mem) (cb, &s, arg2, buf, buflen) != buflen)
-                {
-                  free (buf);
-                  result = -1;
-                  errcode = EINVAL;
-                  break;
-                }
-              free (buf);
-            }
-            break;
-
-          case __NR_fstat:
-            {
-              char *buf;
-              int buflen;
-              struct stat statbuf;
-
-              result = fstat(arg1, &statbuf);
-              errcode = errno;
-              if (result < 0)
-                break;
-
-              buflen = cb_host_to_target_stat (cb, NULL, NULL);
-              buf = xmalloc (buflen);
-              if (cb_host_to_target_stat (cb, &statbuf, buf) != buflen)
-                {
-                  /* The translation failed.  This is due to an internal
-                     host program error, not the target's fault.  */
-                  free (buf);
-                  result = -1;
-                  errcode = ENOSYS;
-                  break;
-                }
-              if ((s.write_mem) (cb, &s, arg2, buf, buflen) != buflen)
-                {
-                  free (buf);
-                  result = -1;
-                  errcode = EINVAL;
-                  break;
-                }
-              free (buf);
-            }
-            break;
-
-          case __NR_sysinfo:
-            {
-              struct sysinfo info;
-
-              result = sysinfo(&info);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              info.uptime    = conv_endian(info.uptime);
-              info.loads[0]  = conv_endian(info.loads[0]);
-              info.loads[1]  = conv_endian(info.loads[1]);
-              info.loads[2]  = conv_endian(info.loads[2]);
-              info.totalram  = conv_endian(info.totalram);
-              info.freeram   = conv_endian(info.freeram);
-              info.sharedram = conv_endian(info.sharedram);
-              info.bufferram = conv_endian(info.bufferram);
-              info.totalswap = conv_endian(info.totalswap);
-              info.freeswap  = conv_endian(info.freeswap);
-              info.procs     = conv_endian16(info.procs);
-#if LINUX_VERSION_CODE >= 0x20400
-              info.totalhigh = conv_endian(info.totalhigh);
-              info.freehigh  = conv_endian(info.freehigh);
-              info.mem_unit  = conv_endian(info.mem_unit);
-#endif
-              if ((s.write_mem) (cb, &s, arg1, (char *) &info, sizeof(info))
-                  != sizeof(info))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-#if 0
-          case __NR_ipc:
-            {
-              result = ipc(arg1, arg2, arg3, arg4,
-                           (void *) t2h_addr(cb, &s, arg5), arg6);
-              errcode = errno;
-            }
-            break;
-#endif
-
-          case __NR_fsync:
-            result = fsync(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_uname:
-            /* utsname contains only arrays of char, so it is not necessary
-               to translate endian. */
-            result = uname((struct utsname *) t2h_addr(cb, &s, arg1));
-            errcode = errno;
-            break;
-
-          case __NR_adjtimex:
-            {
-              struct timex buf;
-
-              result = adjtimex(&buf);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &buf, sizeof(buf));
-              if ((s.write_mem) (cb, &s, arg1, (char *) &buf, sizeof(buf))
-                  != sizeof(buf))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_mprotect:
-            result = mprotect((void *) arg1, arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_fchdir:
-            result = fchdir(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_setfsuid32:
-          case __NR_setfsuid:
-            result = setfsuid(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_setfsgid32:
-          case __NR_setfsgid:
-            result = setfsgid(arg1);
-            errcode = errno;
-            break;
-
-#if 0
-          case __NR__llseek:
-            {
-              loff_t buf;
-
-              result = _llseek(arg1, arg2, arg3, &buf, arg5);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &buf, sizeof(buf));
-              if ((s.write_mem) (cb, &s, t2h_addr(cb, &s, arg4),
-                                 (char *) &buf, sizeof(buf)) != sizeof(buf))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_getdents:
-            {
-              struct dirent dir;
-
-              result = getdents(arg1, &dir, arg3);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              dir.d_ino = conv_endian(dir.d_ino);
-              dir.d_off = conv_endian(dir.d_off);
-              dir.d_reclen = conv_endian16(dir.d_reclen);
-              if ((s.write_mem) (cb, &s, arg2, (char *) &dir, sizeof(dir))
-                  != sizeof(dir))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-#endif
-
-          case __NR_flock:
-            result = flock(arg1, arg2);
-            errcode = errno;
-            break;
-
-          case __NR_msync:
-            result = msync((void *) arg1, arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_readv:
-            {
-              struct iovec vector;
-
-              vector = *((struct iovec *) t2h_addr(cb, &s, arg2));
-              translate_endian((void *) &vector, sizeof(vector));
-
-              result = readv(arg1, &vector, arg3);
-              errcode = errno;
-            }
-            break;
-
-          case __NR_writev:
-            {
-              struct iovec vector;
-
-              vector = *((struct iovec *) t2h_addr(cb, &s, arg2));
-              translate_endian((void *) &vector, sizeof(vector));
-
-              result = writev(arg1, &vector, arg3);
-              errcode = errno;
-            }
-            break;
-
-          case __NR_fdatasync:
-            result = fdatasync(arg1);
-            errcode = errno;
-            break;
-
-          case __NR_mlock:
-            result = mlock((void *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_munlock:
-            result = munlock((void *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_nanosleep:
-            {
-              struct timespec req, rem;
-
-              req = *((struct timespec *) t2h_addr(cb, &s, arg2));
-              translate_endian((void *) &req, sizeof(req));
-
-              result = nanosleep(&req, &rem);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              translate_endian((void *) &rem, sizeof(rem));
-              if ((s.write_mem) (cb, &s, arg2, (char *) &rem, sizeof(rem))
-                  != sizeof(rem))
-                {
-                  result = -1;
-                  errcode = EINVAL;
-                }
-            }
-            break;
-
-          case __NR_mremap: /* FIXME */
-            result = (int) mremap((void *) t2h_addr(cb, &s, arg1), arg2, arg3, arg4); 
-            errcode = errno;
-            break;
-
-          case __NR_getresuid32:
-          case __NR_getresuid:
-            {
-              uid_t ruid, euid, suid;
-
-              result = getresuid(&ruid, &euid, &suid);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              *((uid_t *) t2h_addr(cb, &s, arg1)) = conv_endian(ruid);
-              *((uid_t *) t2h_addr(cb, &s, arg2)) = conv_endian(euid);
-              *((uid_t *) t2h_addr(cb, &s, arg3)) = conv_endian(suid);
-            }
-            break;
-
-          case __NR_poll:
-            {
-              struct pollfd ufds;
-
-              ufds = *((struct pollfd *) t2h_addr(cb, &s, arg1));
-              ufds.fd = conv_endian(ufds.fd);
-              ufds.events = conv_endian16(ufds.events);
-              ufds.revents = conv_endian16(ufds.revents);
-
-              result = poll(&ufds, arg2, arg3);
-              errcode = errno;
-            }
-            break;
-
-          case __NR_getresgid32:
-          case __NR_getresgid:
-            {
-              uid_t rgid, egid, sgid;
-
-              result = getresgid(&rgid, &egid, &sgid);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              *((uid_t *) t2h_addr(cb, &s, arg1)) = conv_endian(rgid);
-              *((uid_t *) t2h_addr(cb, &s, arg2)) = conv_endian(egid);
-              *((uid_t *) t2h_addr(cb, &s, arg3)) = conv_endian(sgid);
-            }
-            break;
-
-          case __NR_pread:
-            result =  pread(arg1, (void *) t2h_addr(cb, &s, arg2), arg3, arg4); 
-            errcode = errno;
-            break;
-
-          case __NR_pwrite:
-            result =  pwrite(arg1, (void *) t2h_addr(cb, &s, arg2), arg3, arg4); 
-            errcode = errno;
-            break;
-
-          case __NR_chown32:
-          case __NR_chown:
-            result = chown((char *) t2h_addr(cb, &s, arg1), arg2, arg3);
-            errcode = errno;
-            break;
-
-          case __NR_getcwd:
-            result = (int) getcwd((char *) t2h_addr(cb, &s, arg1), arg2);
-            errcode = errno;
-            break;
-
-          case __NR_sendfile:
-            {
-              off_t offset;
-
-              offset = *((off_t *) t2h_addr(cb, &s, arg3));
-              offset = conv_endian(offset);
-
-              result = sendfile(arg1, arg2, &offset, arg3);
-              errcode = errno;
-
-              if (result != 0)
-                break;
-
-              *((off_t *) t2h_addr(cb, &s, arg3)) = conv_endian(offset);
-            }
-            break;
-
-          default:
-            result = -1;
-            errcode = ENOSYS;
-            break;
-          }
-        
-        if (result == -1)
-	  m32rbf_h_gr_set (current_cpu, 0, -errcode);
-        else
-	  m32rbf_h_gr_set (current_cpu, 0, result);
-	break;
-      }
-
-    case TRAP_BREAKPOINT:
-      sim_engine_halt (sd, current_cpu, NULL, pc,
-		       sim_stopped, SIM_SIGTRAP);
-      break;
-
-    case TRAP_FLUSH_CACHE:
-      /* Do nothing.  */
-      break;
-
-    default :
-      {
-	/* Use cr5 as EVB (EIT Vector Base) register.  */
-        USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
-	return new_pc;
-      }
-    }
-
-  /* Fake an "rte" insn.  */
-  /* FIXME: Should duplicate all of rte processing.  */
-  return (pc & -4) + 4;
-}
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
deleted file mode 100644
index 473d0d7..0000000
--- a/sim/m32r/traps.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* m32r exception, interrupt, and trap (EIT) support
-   Copyright (C) 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Solutions.
-
-   This file is part of GDB, the GNU debugger.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-#include "targ-vals.h"
-
-#define TRAP_FLUSH_CACHE 12
-/* The semantic code invokes this for invalid (unrecognized) instructions.  */
-
-SEM_PC
-sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-
-#if 0
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      h_bsm_set (current_cpu, h_sm_get (current_cpu));
-      h_bie_set (current_cpu, h_ie_get (current_cpu));
-      h_bcond_set (current_cpu, h_cond_get (current_cpu));
-      /* sm not changed */
-      h_ie_set (current_cpu, 0);
-      h_cond_set (current_cpu, 0);
-
-      h_bpc_set (current_cpu, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-			  EIT_RSVD_INSN_ADDR);
-    }
-  else
-#endif
-    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
-
-  return pc;
-}
-
-/* Process an address exception.  */
-
-void
-m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
-		  unsigned int map, int nr_bytes, address_word addr,
-		  transfer_type transfer, sim_core_signals sig)
-{
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
-		       m32rbf_h_cr_get (current_cpu, H_CR_BPC));
-      switch (MACH_NUM (CPU_MACH (current_cpu)))
-	{
-	case MACH_M32R:
-	  m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
-	  /* sm not changed.  */
-	  m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
-	  break;
-	case MACH_M32RX:
-  	  m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
-  	  /* sm not changed.  */
-  	  m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
-	  break;
-	case MACH_M32R2:
-	  m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
-	  /* sm not changed.  */
-	  m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
-	  break;
-	default:
-	  abort ();
-	}
-	    
-      m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
-
-      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
-			  EIT_ADDR_EXCP_ADDR);
-    }
-  else
-    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
-		     transfer, sig);
-}
-
-/* Read/write functions for system call interface.  */
-
-static int
-syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
-		  unsigned long taddr, char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
-}
-
-static int
-syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
-		   unsigned long taddr, const char *buf, int bytes)
-{
-  SIM_DESC sd = (SIM_DESC) sc->p1;
-  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
-
-  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
-}
-
-/* Trap support.
-   The result is the pc address to continue at.
-   Preprocessing like saving the various registers has already been done.  */
-
-USI
-m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
-{
-  SIM_DESC sd = CPU_STATE (current_cpu);
-  host_callback *cb = STATE_CALLBACK (sd);
-
-#ifdef SIM_HAVE_BREAKPOINTS
-  /* Check for breakpoints "owned" by the simulator first, regardless
-     of --environment.  */
-  if (num == TRAP_BREAKPOINT)
-    {
-      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
-	 it doesn't return.  Otherwise it returns and let's us try.  */
-      sim_handle_breakpoint (sd, current_cpu, pc);
-      /* Fall through.  */
-    }
-#endif
-
-  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
-    {
-      /* The new pc is the trap vector entry.
-	 We assume there's a branch there to some handler.
-         Use cr5 as EVB (EIT Vector Base) register.  */
-      /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
-      USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
-      return new_pc;
-    }
-
-  switch (num)
-    {
-    case TRAP_SYSCALL :
-      {
-	CB_SYSCALL s;
-
-	CB_SYSCALL_INIT (&s);
-	s.func = m32rbf_h_gr_get (current_cpu, 0);
-	s.arg1 = m32rbf_h_gr_get (current_cpu, 1);
-	s.arg2 = m32rbf_h_gr_get (current_cpu, 2);
-	s.arg3 = m32rbf_h_gr_get (current_cpu, 3);
-
-	if (s.func == TARGET_SYS_exit)
-	  {
-	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
-	  }
-
-	s.p1 = (PTR) sd;
-	s.p2 = (PTR) current_cpu;
-	s.read_mem = syscall_read_mem;
-	s.write_mem = syscall_write_mem;
-	cb_syscall (cb, &s);
-	m32rbf_h_gr_set (current_cpu, 2, s.errcode);
-	m32rbf_h_gr_set (current_cpu, 0, s.result);
-	m32rbf_h_gr_set (current_cpu, 1, s.result2);
-	break;
-      }
-
-    case TRAP_BREAKPOINT:
-      sim_engine_halt (sd, current_cpu, NULL, pc,
-		       sim_stopped, SIM_SIGTRAP);
-      break;
-
-    case TRAP_FLUSH_CACHE:
-      /* Do nothing.  */
-      break;
-
-    default :
-      {
-	/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
-        /* Use cr5 as EVB (EIT Vector Base) register.  */
-        USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
-	return new_pc;
-      }
-    }
-
-  /* Fake an "rte" insn.  */
-  /* FIXME: Should duplicate all of rte processing.  */
-  return (pc & -4) + 4;
-}