* sim-main.h: #include symcat.h.

	* m32r-sim.h (BRANCH_NEW_PC): Delete current_cpu arg.
	(NEW_PC_{BASE,SKIP,2,4,BRANCH_P}): New macros.
	* cpu.[ch],decode.[ch],extract.c,model.c: Regenerate.
	* sem.c,sem-switch.c: Regenerate.
	* m32r-sim.h (SEM_NEXT_PC): Modify to handle parallel exec.
	* mloopx.in: Rewrite.
	* cpux.[ch],decodex.[ch],readx.c,semx.c: Regenerate.

1 files changed, 86 insertions, 37 deletions

diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in
index 533aca5..fca05cd 100644
--- a/sim/m32r/mloopx.in
+++ b/sim/m32r/mloopx.in
@@ -36,12 +36,9 @@ EOF
 xinit)
 
 cat <<EOF
-  USI insn,insn1,insn2;
-  DECODE *decode,*d1,*d2;
-  int icount,icount2;
+  DECODE *d1,*d2;
   ARGBUF abufs[MAX_PARALLEL_INSNS];
-  SEM_ARG sem_arg;
-
+  PAREXEC pbufs[MAX_PARALLEL_INSNS];
 EOF
 
 ;;
@@ -52,52 +49,61 @@ cat <<EOF
 {
   PCADDR pc = CPU (h_pc);
 
+  /* ??? This code isn't very fast.  Let's get it working first.  */
+
   if ((pc & 3) != 0)
     {
-      insn1 = GETIMEMUHI (current_cpu, pc);
-      insn1 &= 0x7fff;
-      d1 = m32rx_decode (current_cpu, pc, insn1);
+      USI insn = GETIMEMUHI (current_cpu, pc);
+      insn &= 0x7fff;
+      d1 = m32rx_decode (current_cpu, pc, insn);
+      abufs[0].insn = insn;
       icount = 1;
     }
   else
     {
-      insn1 = GETIMEMUSI (current_cpu, pc);
-      if ((SI) insn1 < 0)
+      USI insn = GETIMEMUSI (current_cpu, pc);
+      if ((SI) insn < 0)
 	{
-	  d1 = m32rx_decode (current_cpu, pc, insn1 >> 16);
+	  d1 = m32rx_decode (current_cpu, pc, insn >> 16);
+	  abufs[0].insn = insn;
 	  icount = 1;
 	}
       else
 	{
 	  if (insn & 0x8000)
 	    {
-	      insn2 = insn1 & 0x7fff;
-	      insn1 = insn1 >> 16;
-	      d1 = m32rx_decode (current_cpu, pc, insn1);
-	      d2 = m32rx_decode (current_cpu, pc, insn2);
+	      d1 = m32rx_decode (current_cpu, pc, insn >> 16);
+	      abufs[0].insn = insn >> 16;
+	      d2 = m32rx_decode (current_cpu, pc, insn & 0x7fff);
+	      abufs[1].insn = insn & 0x7fff;
 	      icount = 2;
 	    }
 	  else
 	    {
-	      insn1 = insn1 >> 16;
-	      d1 = m32rx_decode (current_cpu, pc, insn1);
+	      d1 = m32rx_decode (current_cpu, pc, insn >> 16);
+	      abufs[0].insn = insn >> 16;
 	      icount = 1;
 	    }
 	}
     }
 
-  icount2 = icount;
-  insn = insn1;
-  decode = d1;
-  do
-    {
+  {
+    int icount2 = icount;
+    USI insn = abufs[0].insn;
+    DECODE *decode = d1;
+    /* decode, par_exec, and insn are refered to by readx.c.  */
+    PAREXEC *par_exec = &pbufs[0];
+    do
+      {
 #define DEFINE_SWITCH
 #include "readx.c"
 
-      insn = insn2;
-      decode = d2;
-    }
-  while (--icount2 > 0);
+	decode = d2;
+	insn = abufs[1].insn;
+	++par_exec;
+      }
+    while (--icount2 != 0);
+  }
 }
 EOF
 
@@ -107,19 +113,62 @@ xfull-exec-* | xfast-exec-*)
 
 cat <<EOF
 {
-  decode = d1;
-  do
+  SEM_ARG sem_arg = &abufs[0];
+  PAREXEC *par_exec = &pbufs[0];
+  PCADDR new_pc;
+
+  /* If doing parallel execution, verify insns are in the right pipeline.  */
+  if (icount == 2)
+    {
+      ; /*wip*/
+    }
+
+  TRACE_INSN_INIT (current_cpu);
+  TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
+  new_pc = (*d1->semantic) (current_cpu, sem_arg, par_exec);
+  TRACE_INSN_FINI (current_cpu);
+  PROFILE_COUNT_INSN (current_cpu, CPU (h_pc), CGEN_INSN_INDEX (d1->opcode));
+
+  /* The result of the semantic fn is one of:
+     - next address, branch only
+     - NEW_PC_SKIP, sc/snc insn
+     - NEW_PC_2, 2 byte non-branch non-sc/snc insn
+     - NEW_PC_4, 4 byte non-branch insn
+     */
+
+  if (new_pc == NEW_PC_4)
+    CPU (h_pc) += 4;
+  else if (NEW_PC_BRANCH_P (new_pc))
+    CPU (h_pc) = new_pc;
+  else
     {
-      PCADDR new_pc;
-      TRACE_INSN_INIT (current_cpu);
-      TRACE_INSN (current_cpu, sc->argbuf.opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr);
-      new_pc = (*decode->semantic) (current_cpu, &sc->argbuf);
-      TRACE_INSN_FINI (current_cpu);
-      PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (sc->argbuf.opcode));
-      CPU (h_pc) = new_pc;
-      decode = d2;
+      PCADDR pc = CPU (h_pc);
+
+      CPU (h_pc) = pc + 2;
+      if (icount == 2)
+	{
+	  /* Note that we only get here if doing parallel execution.  */
+	  if (new_pc == NEW_PC_SKIP)
+	    {
+	      /* ??? Need generic notion of bypassing an insn for the name of
+		 this macro.  Annulled?  On the otherhand such tracing can go
+		 in the sc/snc semantic fn.  */
+	      ; /*TRACE_INSN_SKIPPED (current_cpu);*/
+	    }
+	  else
+	    {
+	      ++sem_arg;
+	      ++par_exec;
+	      TRACE_INSN_INIT (current_cpu);
+	      TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc));
+	      /* new_pc isn't used.  It's assigned a value for debugging.  */
+	      new_pc = (*d2->semantic) (current_cpu, sem_arg, par_exec);
+	      TRACE_INSN_FINI (current_cpu);
+	      PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (d2->opcode));
+	    }
+	  CPU (h_pc) = pc + 4;
+	}
     }
-  while (--icount > 0);
 }
 EOF