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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-13 17:57:14 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-22 10:02:20 +0000 |
| commit | fb44d95af64dd0609760c1400b9ce4da09296cd1 (patch) | |
| tree | 97e7d0a1637fc65aafdd0c7cbaca2798d2ec28a9 /sim/igen | |
| parent | e08b849efa7af6cb13d7d3d02dc366b9d7f4208c (diff) | |
| download | gdb-fb44d95af64dd0609760c1400b9ce4da09296cd1.zip gdb-fb44d95af64dd0609760c1400b9ce4da09296cd1.tar.gz gdb-fb44d95af64dd0609760c1400b9ce4da09296cd1.tar.bz2 | |
gdb/riscv: Add gdb to dwarf register number mapping
Provide a mapping between GDB's register numbers and DWARF's register
numbers. This resolves some failures that I was seeing on
gdb.base/store.exp when running on an rv64imfdc target.
gdb/ChangeLog:
* riscv-tdep.c (riscv_dwarf_reg_to_regnum): New function.
(riscv_gdbarch_init): Register new function with gdbarch.
* riscv-tdep.h: New enum to define RISC-V DWARF register numbers.
Diffstat (limited to 'sim/igen')
0 files changed, 0 insertions, 0 deletions