[sim] Run spellcheck.sh in sim (part 1)

Run gdb/contrib/spellcheck.sh on directory sim.

Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...

Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.

Tested by rebuilding on x86_64-linux.

Approved-By: Tom Tromey <tom@tromey.com>

11 files changed, 18 insertions, 18 deletions

diff --git a/sim/igen/gen-engine.c b/sim/igen/gen-engine.c
index cdf77ad..2533536 100644
--- a/sim/igen/gen-engine.c
+++ b/sim/igen/gen-engine.c
@@ -67,7 +67,7 @@ print_run_body (lf *file, const gen_entry *table)
 {
   /* Output the function to execute real code:
 
-     Unfortunatly, there are multiple cases to consider vis:
+     Unfortunately, there are multiple cases to consider vis:
 
      <icache> X <smp>
 
diff --git a/sim/igen/gen-icache.c b/sim/igen/gen-icache.c
index 77d170d..641c20e 100644
--- a/sim/igen/gen-icache.c
+++ b/sim/igen/gen-icache.c
@@ -152,7 +152,7 @@ print_icache_extraction (lf *file,
   switch (what_to_declare)
     {
     case undef_variables:
-      /* We've finished with the #define value - destory it */
+      /* We've finished with the #define value - destroy it */
       lf_indent_suppress (file);
       lf_printf (file, "#undef %s\n", entry_name);
       return;
@@ -632,7 +632,7 @@ print_icache_struct (lf *file, const insn_table *isa, cache_entry *cache_rules)
   else
     {
       /* alernativly, since no cache, emit a dummy definition for
-         idecode_cache so that code refering to the type can still compile */
+         idecode_cache so that code referring to the type can still compile */
       lf_printf (file, "typedef void %sidecode_cache;\n",
 		 options.module.global.prefix.l);
     }
diff --git a/sim/igen/gen-semantics.c b/sim/igen/gen-semantics.c
index f6cb55a..fed0914 100644
--- a/sim/igen/gen-semantics.c
+++ b/sim/igen/gen-semantics.c
@@ -246,7 +246,7 @@ print_semantic_body (lf *file,
     }
 
   /* Architecture expects a REG to be zero.  Instead of having to
-     check every read to see if it is refering to that REG just zap it
+     check every read to see if it is referring to that REG just zap it
      at the start of every instruction */
   if (options.gen.zero_reg)
     {
diff --git a/sim/igen/gen-semantics.h b/sim/igen/gen-semantics.h
index 786e5ba..7844f6a 100644
--- a/sim/igen/gen-semantics.h
+++ b/sim/igen/gen-semantics.h
@@ -36,9 +36,9 @@
 
 	o	cached - separate cracker and semantic
 
-		Two independant functions are created.  Firstly the
+		Two independent functions are created.  Firstly the
 		function that cracks an instruction entering it into a
-		cache and secondly the semantic function propper that
+		cache and secondly the semantic function proper that
 		uses the cache.
 
 	o	cached - semantic + cracking semantic
diff --git a/sim/igen/gen.c b/sim/igen/gen.c
index 1499147..bf57162 100644
--- a/sim/igen/gen.c
+++ b/sim/igen/gen.c
@@ -644,7 +644,7 @@ insns_bit_useless (const insn_list *insns, const decode_table *rule, int bit_nr)
 
   /* Given only one constant value has been found, check through all
      the instructions to see if at least one conditional makes it
-     usefull */
+     useful */
   if (value >= 0 && is_useless)
     {
       for (entry = insns; entry != NULL; entry = entry->next)
@@ -981,7 +981,7 @@ gen_entry_expand_opcode (gen_entry *table,
 						     condition->field->last);
 					  /* this is a requirement of
 					     a conditonal field
-					     refering to another field */
+					     referring to another field */
 					  ASSERT ((condition->field->first -
 						   condition->field->last) ==
 						  (first_pos - last_pos));
diff --git a/sim/igen/igen.c b/sim/igen/igen.c
index 94caf6e..60314a6 100644
--- a/sim/igen/igen.c
+++ b/sim/igen/igen.c
@@ -481,7 +481,7 @@ print_itrace (lf *file, const insn_entry *insn, int idecode)
 {
   /* NB: Here we escape each EOLN. This is so that the the compiler
      treats a trace function call as a single line.  Consequently any
-     errors in the line are refered back to the same igen assembler
+     errors in the line are referred back to the same igen assembler
      source line */
   const char *phase = (idecode) ? "DECODE" : "INSN";
   lf_printf (file, "\n");
diff --git a/sim/igen/igen.h b/sim/igen/igen.h
index 7d3b9b4..6e68bfb 100644
--- a/sim/igen/igen.h
+++ b/sim/igen/igen.h
@@ -138,7 +138,7 @@ struct _igen_decode_options
   int combine;
 
   /* Instruction expansion? Should the semantic code for each
-     instruction, when the oportunity arrises, be expanded according
+     instruction, when the opportunity arrises, be expanded according
      to the variable opcode files that the instruction decode process
      renders constant */
   int duplicate;
diff --git a/sim/igen/ld-decode.c b/sim/igen/ld-decode.c
index 5f67d52..368138e 100644
--- a/sim/igen/ld-decode.c
+++ b/sim/igen/ld-decode.c
@@ -161,7 +161,7 @@ load_decode_table (const char *file_name)
       else
 	new_rule->last = options.insn_bit_size - 1;
       if (new_rule->first > new_rule->last)
-	error (new_rule->line, "First must preceed last\n");
+	error (new_rule->line, "First must precede last\n");
 
       /* force first/last, with default values based on first/last */
       if (entry->nr_fields > decode_force_first_field
diff --git a/sim/igen/ld-decode.h b/sim/igen/ld-decode.h
index e26de29..562628a 100644
--- a/sim/igen/ld-decode.h
+++ b/sim/igen/ld-decode.h
@@ -89,7 +89,7 @@
 
    If an instruction field was found, enlarge the field size so that
    it is forced to at least include bits starting from <force_first>
-   (<force_last>).  To stop this occuring, use <force_first> = <last>
+   (<force_last>).  To stop this occurring, use <force_first> = <last>
    + 1 and <force_last> = <first> - 1.
 
    <force_reserved>
@@ -101,7 +101,7 @@
 
    Treat any contained register (string) fields as constant when
    determining the instruction field.  For the instruction decode (and
-   controled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
+   controlled by IDECODE_EXPAND_SEMANTICS) this forces the expansion of
    what would otherwize be non constant bits of an instruction.
 
    <use_switch>
diff --git a/sim/igen/ld-insn.c b/sim/igen/ld-insn.c
index a561bad..baa8e12 100644
--- a/sim/igen/ld-insn.c
+++ b/sim/igen/ld-insn.c
@@ -201,7 +201,7 @@ parse_insn_word (const line_ref *line, char *string, int word_nr)
 	{
 	  if (strlen_pos == 0)
 	    {
-	      /* when the length/pos field is omited, an integer field
+	      /* when the length/pos field is omitted, an integer field
 	         is always binary */
 	      uint64_t val = 0;
 	      int i;
@@ -409,7 +409,7 @@ parse_insn_words (insn_entry * insn, char *formats)
       insn->word[i] = word;
   }
 
-  /* Go over all fields that have conditionals refering to other
+  /* Go over all fields that have conditionals referring to other
      fields.  Link the fields up.  Verify that the two fields have the
      same size. Verify that the two fields are different */
   {
@@ -442,9 +442,9 @@ parse_insn_words (insn_entry * insn, char *formats)
 				&& strcmp (refered_field->val_string,
 					   cond->string) == 0)
 			      {
-				/* found field being refered to by conditonal */
+				/* found field being referred to by conditonal */
 				cond->field = refered_field;
-				/* check refered to and this field are
+				/* check referred to and this field are
 				   the same size */
 				if (f->width != refered_field->width)
 				  error (insn->line,
diff --git a/sim/igen/lf.h b/sim/igen/lf.h
index 6a6c1e2..eac9fa4 100644
--- a/sim/igen/lf.h
+++ b/sim/igen/lf.h
@@ -47,7 +47,7 @@ lf_file_references;
 
 
 /* Open the file NAME for writing ("-" for stdout).  Use REAL_NAME
-   when refering to the opened file.  Line number information (in the
+   when referring to the opened file.  Line number information (in the
    output) can be suppressed with FILE_REFERENCES ==
    LF_OMIT_REFERENCES.  TYPE is to determine the formatting of some of
    the print messages below. */