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| author | Tom de Vries <tdevries@suse.de> | 2024-11-23 13:07:38 +0100 |
|---|---|---|
| committer | Tom de Vries <tdevries@suse.de> | 2024-11-23 13:07:38 +0100 |
| commit | d2d240ff89b4d3359ea70cdb47d3e79294ca891a (patch) | |
| tree | d277cf5c4263881d513deb2d7389c2a0c1f4610b /sim/erc32/float.c | |
| parent | 8dfa29fcbd60bead4d67569bd14c818540959130 (diff) | |
| download | gdb-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.zip gdb-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.tar.gz gdb-d2d240ff89b4d3359ea70cdb47d3e79294ca891a.tar.bz2 | |
[sim] Run spellcheck.sh in sim (part 1)
Run gdb/contrib/spellcheck.sh on directory sim.
Fix auto-corrected typos:
...
accessable -> accessible
accidently -> accidentally
accomodate -> accommodate
adress -> address
afair -> affair
agains -> against
agressively -> aggressively
annuled -> annulled
arbitary -> arbitrary
arround -> around
auxillary -> auxiliary
availablity -> availability
clasic -> classic
comming -> coming
controled -> controlled
controling -> controlling
destory -> destroy
existance -> existence
explictly -> explicitly
faciliate -> facilitate
fouth -> fourth
fullfilled -> fulfilled
guarentee -> guarantee
hinderance -> hindrance
independant -> independent
inital -> initial
loosing -> losing
occurance -> occurrence
occured -> occurred
occuring -> occurring
omited -> omitted
oportunity -> opportunity
parallely -> parallelly
permissable -> permissible
postive -> positive
powerfull -> powerful
preceed -> precede
preceeding -> preceding
preceeds -> precedes
primative -> primitive
probaly -> probably
programable -> programmable
propogate -> propagate
propper -> proper
recieve -> receive
reconized -> recognized
refered -> referred
refering -> referring
relevent -> relevant
responisble -> responsible
retreive -> retrieve
safty -> safety
specifiying -> specifying
spontanous -> spontaneous
sqaure -> square
successfull -> successful
supress -> suppress
sytem -> system
thru -> through
transfered -> transferred
trigered -> triggered
unfortunatly -> unfortunately
upto -> up to
usefull -> useful
wierd -> weird
writen -> written
doesnt -> doesn't
isnt -> isn't
...
Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs
and sim/cr16/simops.c.
Tested by rebuilding on x86_64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
Diffstat (limited to 'sim/erc32/float.c')
| -rw-r--r-- | sim/erc32/float.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/erc32/float.c b/sim/erc32/float.c index 2b851ca..069436c 100644 --- a/sim/erc32/float.c +++ b/sim/erc32/float.c @@ -20,7 +20,7 @@ FPU. IEEE trap handling is done as follows: 1. In the host, all IEEE traps are masked 2. After each simulated FPU instruction, check if any exception - occured by reading the exception bits from the host FPU status + occurred by reading the exception bits from the host FPU status register (get_accex()). 3. Propagate any exceptions to the simulated FSR. 4. Clear host exception bits. |