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| author | Mike Frysinger <vapier@gentoo.org> | 2015-03-23 00:44:54 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-02-06 12:12:51 -0500 |
| commit | 4c0d76b9c420bb29cb3365c5edc9c78c50d2b231 (patch) | |
| tree | 1cbf362654cf185294337a5f27e6d3c94fdb9d65 /sim/avr | |
| parent | cd89c53f6d475cd05a1858b9195770e347fb2e9e (diff) | |
| download | gdb-4c0d76b9c420bb29cb3365c5edc9c78c50d2b231.zip gdb-4c0d76b9c420bb29cb3365c5edc9c78c50d2b231.tar.gz gdb-4c0d76b9c420bb29cb3365c5edc9c78c50d2b231.tar.bz2 | |
sim: watchpoints: use common sim_pc_get
Few arches implement STATE_WATCHPOINTS()->pc while all of them implement
sim_pc_get. Lets switch the sim-watch core for monitoring pc events to
the sim_pc_get API so this module works for all ports, and then we can
delete this old back channel of snooping in the port's cpu state -- the
code needs the pointer to the pc storage so that it can read out bytes
and compare them to the watchrange.
This also fixes the logic on multi-cpu sims by removing the limitation
of only being able to watch CPU0's state.
Diffstat (limited to 'sim/avr')
| -rw-r--r-- | sim/avr/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/avr/interp.c | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/sim/avr/ChangeLog b/sim/avr/ChangeLog index 505e284..b67888b 100644 --- a/sim/avr/ChangeLog +++ b/sim/avr/ChangeLog @@ -1,5 +1,9 @@ 2021-02-06 Mike Frysinger <vapier@gentoo.org> + * interp.c (sim_open): Delete call to STATE_WATCHPOINTS. + +2021-02-06 Mike Frysinger <vapier@gentoo.org> + * configure: Regenerate. 2021-01-30 Mike Frysinger <vapier@gentoo.org> diff --git a/sim/avr/interp.c b/sim/avr/interp.c index ba89eb5..cce84a9 100644 --- a/sim/avr/interp.c +++ b/sim/avr/interp.c @@ -1690,12 +1690,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, return 0; } - { - /* XXX: Only first core gets profiled ? */ - SIM_CPU *cpu = STATE_CPU (sd, 0); - STATE_WATCHPOINTS (sd)->pc = &cpu->pc; - } - if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) { free_state (sd); |