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authorTom de Vries <tdevries@suse.de>2024-11-23 13:07:38 +0100
committerTom de Vries <tdevries@suse.de>2024-11-23 13:07:38 +0100
commitd2d240ff89b4d3359ea70cdb47d3e79294ca891a (patch)
treed277cf5c4263881d513deb2d7389c2a0c1f4610b /sim/arm
parent8dfa29fcbd60bead4d67569bd14c818540959130 (diff)
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[sim] Run spellcheck.sh in sim (part 1)
Run gdb/contrib/spellcheck.sh on directory sim. Fix auto-corrected typos: ... accessable -> accessible accidently -> accidentally accomodate -> accommodate adress -> address afair -> affair agains -> against agressively -> aggressively annuled -> annulled arbitary -> arbitrary arround -> around auxillary -> auxiliary availablity -> availability clasic -> classic comming -> coming controled -> controlled controling -> controlling destory -> destroy existance -> existence explictly -> explicitly faciliate -> facilitate fouth -> fourth fullfilled -> fulfilled guarentee -> guarantee hinderance -> hindrance independant -> independent inital -> initial loosing -> losing occurance -> occurrence occured -> occurred occuring -> occurring omited -> omitted oportunity -> opportunity parallely -> parallelly permissable -> permissible postive -> positive powerfull -> powerful preceed -> precede preceeding -> preceding preceeds -> precedes primative -> primitive probaly -> probably programable -> programmable propogate -> propagate propper -> proper recieve -> receive reconized -> recognized refered -> referred refering -> referring relevent -> relevant responisble -> responsible retreive -> retrieve safty -> safety specifiying -> specifying spontanous -> spontaneous sqaure -> square successfull -> successful supress -> suppress sytem -> system thru -> through transfered -> transferred trigered -> triggered unfortunatly -> unfortunately upto -> up to usefull -> useful wierd -> weird writen -> written doesnt -> doesn't isnt -> isn't ... Manually undid the "andd -> and" transformation in sim/testsuite/cr16/andd.cgs and sim/cr16/simops.c. Tested by rebuilding on x86_64-linux. Approved-By: Tom Tromey <tom@tromey.com>
Diffstat (limited to 'sim/arm')
-rw-r--r--sim/arm/armcopro.c6
-rw-r--r--sim/arm/armemu.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c
index 5cd33fb..70cebcd 100644
--- a/sim/arm/armcopro.c
+++ b/sim/arm/armcopro.c
@@ -134,7 +134,7 @@ check_cp15_access (ARMul_State * state,
return ARMul_CANT;
break;
case 7:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -157,7 +157,7 @@ check_cp15_access (ARMul_State * state,
break;
case 8:
- /* Permissable combinations:
+ /* Permissible combinations:
Opcode_2 CRm
0 5
0 6
@@ -232,7 +232,7 @@ write_cp15_reg (ARMul_State * state,
/* Writes are not allowed. */
return;
- case 1: /* Auxillary Control. */
+ case 1: /* Auxiliary Control. */
/* Only BITS (5, 4) and BITS (1, 0) can be written. */
value &= 0x33;
break;
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index cafaabb..2958977 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -6033,7 +6033,7 @@ Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
/* We now need to add all of these results together, taking
- care to propogate the carries from the additions. */
+ care to propagate the carries from the additions. */
RdLo = Add32 (lo, (mid1 << 16), &carry);
RdHi = carry;
RdLo = Add32 (RdLo, (mid2 << 16), &carry);