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authorNick Clifton <nickc@redhat.com>2002-02-04 16:27:22 +0000
committerNick Clifton <nickc@redhat.com>2002-02-04 16:27:22 +0000
commit25180f8aefdfb363742aa577363184fd2a43c0b6 (patch)
tree953e830d69ddc2425b1c51eafff4e864125f0926 /sim/arm/wrapper.c
parentfdf4122d8d23ba39cc3792c8ad3413fdf0bced59 (diff)
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If a v5 architecture is detected, assume it might be an XScale binary, since
there is no way to distinguish between the two in the COFF file format.
Diffstat (limited to 'sim/arm/wrapper.c')
-rw-r--r--sim/arm/wrapper.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 524377d..c2fd8be 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -234,6 +234,15 @@ sim_create_inferior (sd, abfd, argv, env)
break;
case bfd_mach_arm_5:
+ /* This is a special case in order to support COFF based ARM toolchains.
+ The COFF header does not have enough room to store all the different
+ kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
+ to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
+ machine type here, we assume it could be any of the above architectures
+ and so select the most feature-full. */
+ ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
+ break;
+
case bfd_mach_arm_5T:
ARMul_SelectProcessor (state, ARM_v5_Prop);
break;