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authorStafford Horne <shorne@gmail.com>2017-12-09 05:57:25 +0900
committerStafford Horne <shorne@gmail.com>2017-12-12 23:44:14 +0900
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sim: or1k: add or1k target to sim
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file.
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+2017-12-12 Stafford Horne <shorne@gmail.com>
+ Peter Gavin <pgavin@gmail.com>
+
+ * configure.tgt: Add or1k sim.
+ * or1k/README: New file.
+ * or1k/Makefile.in: New file.
+ * or1k/configure.ac: New file.
+ * or1k/mloop.in: New file.
+ * or1k/or1k-sim.h: New file.
+ * or1k/or1k.c: New file.
+ * or1k/sim-if.c: New file.
+ * or1k/sim-main.h: New file.
+ * or1k/traps.c: New file.
+
2017-11-01 James Bowman <james.bowman@ftdichip.com>
* ft32/interp.c (step_once): Add ft32 shortcode decoder.