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authorJin Ma <jinma@linux.alibaba.com>2023-11-18 14:58:25 +0800
committerNelson Chu <nelson@rivosinc.com>2023-11-23 09:31:29 +0800
commit6fdd02bb1f5bbeaa4d38b8a39e26ba414a850001 (patch)
tree88f107408a73304f5adb00b4ee3d9a32c4223967 /opcodes/tilepro-dis.c
parent86fbfedd715df8a89d73374d70b1f068f95b450e (diff)
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RISC-V: Add CSRs for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the CSRs for XTheadVector. Because of the conflict between encoding and teh 'V' extension, it is implemented by alias. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add the class for the CSRs of the "XTheadVector" extension. (riscv_csr_address): Likewise. * testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test. * testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test. * testsuite/gas/riscv/x-thead-vector-csr.d: New test. * testsuite/gas/riscv/x-thead-vector-csr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
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