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authorNelson Chu <nelson.chu@sifive.com>2021-01-08 04:04:13 -0800
committerNelson Chu <nelson.chu@sifive.com>2021-01-19 09:40:18 +0800
commit85e963f185884ffec4ed9577da9b9fbd028b62ee (patch)
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parentf0c1efa53d78b335dfc0f86166121f051ecc3d02 (diff)
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ld: Just xfail riscv little endian targets for compressed1d.d test.
The sizes of compressed and uncompressed .debug_aranges are the same for the riscv big endian targets, but different for the little endian targets. The compress rule is fine and isn't broken by riscv, just the original compressed1d.d fails by accident. Ideally, we should fill the R_RISCV_ADD/SUB relocations when disabling relaxations in the assembler. But before that, Jim already had written an alternative test compressed1d-alt to relpace compressed1d.d for riscv, so we can only xfail the riscv little endian targets in the short-term. ld/ * testsuite/ld-elf/elf.exp (riscv_little_endian): Added. Return true if target is riscv little endian. Otherwise, return false. * testsuite/ld-elf/compressed1d.d: Only xfail the riscv little endian targets by [riscv_little_endian].
Diffstat (limited to 'opcodes/tilegx-opc.c')
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