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authorMartin Aberg <maberg@gaisler.com>2018-08-29 20:52:28 +0200
committerJose E. Marchesi <jose.marchesi@oracle.com>2018-08-29 20:52:28 +0200
commitdf28970fcc741fa744a51aece29bb755c20eceab (patch)
tree9a37e0ca7847b549f56d17ef7427ec13b45c582a /opcodes/sparc-opc.c
parent4d3928d7e0a141e0fb16405d33b375cbe2f13123 (diff)
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sparc/leon: add support for partial write psr instruction
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR instruction to only affect the %PSR.ET field. When available it is enabled by setting the rd field of the WRPSR instruction to a value other than 0. For Leon processors with support for partial write %PSR (currently GR740 and GR716) the rd value must be 1. opcodes/ChangeLog: 2018-08-29 Martin Aberg <maberg@gaisler.com> * sparc-opc.c (sparc_opcodes): Add Leon specific partial write psr (PWRPSR) instruction. gas/ChangeLog: 2018-08-29 Daniel Cederman <cederman@gaisler.com> * testsuite/gas/sparc/leon.d: New test. * testsuite/gas/sparc/leon.s: New test. * testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
Diffstat (limited to 'opcodes/sparc-opc.c')
-rw-r--r--opcodes/sparc-opc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 6de9305..ab39398 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -71,6 +71,7 @@
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define sparclet (MASK_SPARCLET)
+#define leon (MASK_LEON)
/* sparclet insns supported by leon. */
#define letandleon (MASK_SPARCLET | MASK_LEON)
#define sparclite (MASK_SPARCLITE)
@@ -1023,6 +1024,13 @@ wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr */
wrasr (27, HWCAP_PAUSE, 0, v9e), /* wr ...,%pause */
wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */
+{ "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI(~0), "1,2,p", 0, 0, 0, leon }, /* pwr r,r,%psr */
+{ "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1), "1,i,p", 0, 0, 0, leon }, /* pwr r,i,%psr */
+{ "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,rs2,%psr */
+{ "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|RS1_G0, "i,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,i,%psr */
+{ "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,0,%psr */
+{ "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,%g0,%psr */
+
{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */
{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */