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| author | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2017-10-09 18:37:53 +0200 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@linux.vnet.ibm.com> | 2017-10-09 18:37:53 +0200 |
| commit | ee6767daf13a13867f8e716c2a53b748ab0da536 (patch) | |
| tree | 305c790d9ee8818864db0bde7373a436df0aac2b /opcodes/s390-opc.txt | |
| parent | 890e97902a21a3b88f9b6028852736b813303029 (diff) | |
| download | gdb-ee6767daf13a13867f8e716c2a53b748ab0da536.zip gdb-ee6767daf13a13867f8e716c2a53b748ab0da536.tar.gz gdb-ee6767daf13a13867f8e716c2a53b748ab0da536.tar.bz2 | |
S/390: Sync with IBM z14 POP - SI_RD format
The recent POP adjusted a few of the instruction formats. This patch
adjusts our optable accordingly. No user visible change - hopefully.
opcodes/ChangeLog:
2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
* s390-opc.c (INSTR_SI_RD): New macro.
(INSTR_S_RD): Adjust example instruction.
* s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
SI_RD.
Diffstat (limited to 'opcodes/s390-opc.txt')
| -rw-r--r-- | opcodes/s390-opc.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 535d6c9..67683b1 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -103,7 +103,7 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch 20 lpdr RR_FF "load positive (long)" g5 esa,zarch 30 lper RR_FF "load positive (short)" g5 esa,zarch 10 lpr RR_RR "load positive" g5 esa,zarch -82 lpsw S_RD "load PSW" g5 esa,zarch +82 lpsw SI_RD "load PSW" g5 esa,zarch 18 lr RR_RR "load" g5 esa,zarch b1 lra RX_RRRD "load real address" g5 esa,zarch 25 ldxr RR_FFE "load rounded (ext. to long)" g5 esa,zarch @@ -199,7 +199,7 @@ b25e srst RRE_RR "search string" g5 esa,zarch b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch b233 ssch S_RD "start subchannel" g5 esa,zarch b22b sske RRE_RR "set storage key extended" g5 esa,zarch -80 ssm S_RD "set system mask" g5 esa,zarch +80 ssm SI_RD "set system mask" g5 esa,zarch 50 st RX_RRRD "store" g5 esa,zarch 9b stam RS_AARD "store access multiple" g5 esa,zarch b212 stap S_RD "store CPU address" g5 esa,zarch @@ -235,7 +235,7 @@ e501 tprot SSE_RDRD "test protection" g5 esa,zarch dc tr SS_L0RDRD "translate" g5 esa,zarch 99 trace RS_RRRD "trace" g5 esa,zarch dd trt SS_L0RDRD "translate and test" g5 esa,zarch -93 ts S_RD "test and set" g5 esa,zarch +93 ts SI_RD "test and set" g5 esa,zarch b235 tsch S_RD "test subchannel" g5 esa,zarch f3 unpk SS_LLRDRD "unpack" g5 esa,zarch 0102 upt E "update tree" g5 esa,zarch |