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authorGraydon Hoare <graydon@redhat.com>2002-01-22 21:45:36 +0000
committerGraydon Hoare <graydon@redhat.com>2002-01-22 21:45:36 +0000
commit9a2e995d8ac926488ad1472e6fb76352122ff576 (patch)
tree1dd67859a8e2fafd835e85a4402d25c92b2ee589 /opcodes/openrisc-desc.c
parentcc096b7166610e6cca71574ef936acbabc922708 (diff)
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[ include/opcode/ChangeLog ]
2002-01-22 Graydon Hoare <graydon@redhat.com> * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. [ opcodes/ChangeLog ] 2002-01-22 Graydon Hoare <graydon@redhat.com> * fr30-asm.c: Regenerate. * fr30-desc.c: Likewise. * fr30-desc.h: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * fr30-opc.c: Likewise. * fr30-opc.h: Likewise. * m32r-asm.c: Likewise. * m32r-desc.c: Likewise. * m32r-desc.h: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * m32r-opc.c: Likewise. * m32r-opc.h: Likewise. * m32r-opinst.c: Likewise. * openrisc-asm.c: Likewise. * openrisc-desc.c: Likewise. * openrisc-desc.h: Likewise. * openrisc-dis.c: Likewise. * openrisc-ibld.c: Likewise. * openrisc-opc.c: Likewise. * openrisc-opc.h: Likewise. * xstormy16-desc.c: Likewise. [ cgen/ChangeLog ] 2002-01-22 Graydon Hoare <graydon@redhat.com> * desc-cpu.scm (ifld-number-cache): Add. (ifld-number): Add. (gen-maybe-multi-ifld-of-op): Add. (gen-maybe-multi-ifld): Add. (gen-multi-ifield-nodes): Add. (cgen-desc.c): Add call to gen-multi-ifield-nodes.
Diffstat (limited to 'opcodes/openrisc-desc.c')
-rw-r--r--opcodes/openrisc-desc.c41
1 files changed, 36 insertions, 5 deletions
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
index f1fb3ab..e5eded9 100644
--- a/opcodes/openrisc-desc.c
+++ b/opcodes/openrisc-desc.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@@ -253,6 +253,21 @@ const CGEN_IFLD openrisc_cgen_ifld_table[] =
#undef A
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
+{
+ { 0, &(openrisc_cgen_ifld_table[19]) },
+ { 0, &(openrisc_cgen_ifld_table[20]) },
+ {0,0}
+};
+
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@@ -270,51 +285,67 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(openrisc_cgen_ifld_table[0]) },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: special register */
{ "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: condition bit */
{ "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* simm-16: 16 bit signed immediate */
{ "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[7]) },
{ 0, { (1<<MACH_BASE) } } },
/* uimm-16: 16 bit unsigned immediate */
{ "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[8]) },
{ 0, { (1<<MACH_BASE) } } },
/* disp-26: pc-rel 26 bit */
{ "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
+ { 0, &(openrisc_cgen_ifld_table[21]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* abs-26: abs 26 bit */
{ "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
+ { 0, &(openrisc_cgen_ifld_table[22]) },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* uimm-5: imm5 */
{ "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
+ { 0, &(openrisc_cgen_ifld_table[9]) },
{ 0, { (1<<MACH_BASE) } } },
/* rD: destination register */
{ "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
+ { 0, &(openrisc_cgen_ifld_table[4]) },
{ 0, { (1<<MACH_BASE) } } },
/* rA: source register A */
{ "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
+ { 0, &(openrisc_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* rB: source register B */
{ "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
+ { 0, &(openrisc_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-23: f-op23 */
{ "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
+ { 0, &(openrisc_cgen_ifld_table[15]) },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-3: f-op3 */
{ "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
+ { 0, &(openrisc_cgen_ifld_table[16]) },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[7]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* lo16: low 16 bit immediate, sign optional */
{ "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[11]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* ui16nc: 16 bit immediate, sign optional */
{ "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
+ { 2, &(OPENRISC_F_I16NC_MULTI_IFIELD[0]) },
{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
};
@@ -804,8 +835,8 @@ openrisc_cgen_rebuild_tables (cd)
{
const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
- /* Default insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
@@ -813,8 +844,8 @@ openrisc_cgen_rebuild_tables (cd)
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
- /* Base insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)