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author | Borislav Petkov <bp@suse.de> | 2017-07-05 11:27:49 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2017-07-05 11:27:49 +0200 |
commit | e4bdd679556e4e4ba71bcd066cc98ee7c2f4fca2 (patch) | |
tree | 9659a1146cb84fda14a65d62524d3d85e65c03b1 /opcodes/nds32-asm.h | |
parent | 60c96dbf02fcdb30942b9db7a138afcfc2b7220e (diff) | |
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X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
Diffstat (limited to 'opcodes/nds32-asm.h')
0 files changed, 0 insertions, 0 deletions