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| author | Nick Clifton <nickc@redhat.com> | 2022-12-01 13:09:26 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2022-12-01 13:09:26 +0000 |
| commit | 6ef35c04dffe685ece08212201c4c032baf8aa86 (patch) | |
| tree | 3eba01220e92f2f24152d4ad94f4be8c45c9f53b /opcodes/nds32-asm.h | |
| parent | 7505bb034c7c8a3d9ecf34e22777114c8bc4a93e (diff) | |
| download | gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.zip gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.tar.gz gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.tar.bz2 | |
Fix verilog output when the width is > 1.
PR 25202
bfd * bfd.c (VerilogDataEndianness): New variable.
(verilog_write_record): Use VerilogDataEndianness, if set, to
choose the endianness of the output.
(verilog_write_section): Adjust the address by the data width.
binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
endianness of the input file.
(copy_main): Verifiy the value set by the --verilog-data-width
option.
* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
* testsuite/binutils-all/verilog-I4.hex: New file.
Diffstat (limited to 'opcodes/nds32-asm.h')
0 files changed, 0 insertions, 0 deletions