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authorRichard Sandiford <rdsandiford@googlemail.com>2013-08-01 20:55:25 +0000
committerRichard Sandiford <rdsandiford@googlemail.com>2013-08-01 20:55:25 +0000
commitfc76e730568e8dfd035147a8d5c608205574a61c (patch)
tree3ebfc54f4b8687f9dbd9e8d6d01dfb177efcb6ff /opcodes/mips16-opc.c
parent265459441cc4d0b2123f2266b183e10d97aad639 (diff)
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include/opcode/
* mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.
Diffstat (limited to 'opcodes/mips16-opc.c')
-rw-r--r--opcodes/mips16-opc.c256
1 files changed, 129 insertions, 127 deletions
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index b833e91..f386962 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -144,19 +144,18 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
#define UBD INSN_UNCOND_BRANCH_DELAY
-#define WR_x MIPS16_INSN_WRITE_X
-#define WR_y MIPS16_INSN_WRITE_Y
-#define WR_z MIPS16_INSN_WRITE_Z
-#define WR_T MIPS16_INSN_WRITE_T
-#define WR_31 MIPS16_INSN_WRITE_31
-#define WR_Y MIPS16_INSN_WRITE_GPR_Y
+#define WR_1 INSN_WRITE_1
+#define WR_2 INSN_WRITE_2
+#define RD_1 INSN_READ_1
+#define RD_2 INSN_READ_2
+#define RD_3 INSN_READ_3
+#define RD_4 INSN_READ_4
+#define MOD_1 (WR_1|RD_1)
+#define MOD_2 (WR_2|RD_2)
-#define RD_x MIPS16_INSN_READ_X
-#define RD_y MIPS16_INSN_READ_Y
-#define RD_Z MIPS16_INSN_READ_Z
-#define RD_T MIPS16_INSN_READ_T
-#define RD_SP MIPS16_INSN_READ_SP
-#define RD_X MIPS16_INSN_READ_GPR_X
+#define RD_T INSN_READ_GPR_24
+#define WR_T INSN_WRITE_GPR_24
+#define WR_31 INSN_WRITE_GPR_31
#define WR_HI INSN_WRITE_HI
#define WR_LO INSN_WRITE_LO
@@ -166,7 +165,10 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
#define NODS INSN_NO_DELAY_SLOT
#define TRAP INSN_NO_DELAY_SLOT
-#define MOD_SP INSN2_MOD_SP
+#define RD_16 INSN2_READ_GPR_16
+#define RD_SP INSN2_READ_SP
+#define WR_SP INSN2_WRITE_SP
+#define MOD_SP (RD_SP|WR_SP)
#define RD_31 INSN2_READ_GPR_31
#define RD_PC INSN2_READ_PC
#define UBR INSN2_UNCOND_BRANCH
@@ -181,27 +183,27 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
const struct mips_opcode mips16_opcodes[] =
{
/* name, args, match, mask, pinfo, pinfo2, membership */
-{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1, 0, 0 }, /* move $0,$Z */
-{"la", "x,A", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
+{"nop", "", 0x6500, 0xffff, 0, RD_16, I1, 0, 0 }, /* move $0,$Z */
+{"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
-{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
-{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
+{"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
+{"addiu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
{"addiu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
{"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
-{"addiu", "x,P,V", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
-{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
-{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 },
-{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
-{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
+{"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
+{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
+{"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 },
+{"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 },
{"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
{"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 },
-{"addu", "x,P,V", 0x0800, 0xf800, WR_x, RD_PC, I1, 0, 0 },
-{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
-{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
+{"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
+{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
{"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 },
{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
-{"beqz", "x,p", 0x2000, 0xf800, RD_x, CBR, I1, 0, 0 },
+{"beqz", "x,p", 0x2000, 0xf800, RD_1, CBR, I1, 0, 0 },
{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
@@ -220,52 +222,52 @@ const struct mips_opcode mips16_opcodes[] =
{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bnez", "x,p", 0x2800, 0xf800, RD_x, CBR, I1, 0, 0 },
+{"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 },
{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 },
{"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 },
{"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 },
-{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
-{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"dla", "y,E", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
-{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
-{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
+{"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
+{"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
+{"daddiu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
{"daddiu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
-{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
-{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
-{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 },
-{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
-{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
+{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
+{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
+{"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
+{"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
{"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
{"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
-{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
-{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
-{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
+{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 },
-{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 },
-{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
-{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
-{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
-{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
-{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 },
-{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
+{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 },
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 },
-{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3, 0, 0 },
-{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 },
-{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 },
-{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
-{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 },
+{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 },
+{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 },
+{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 },
+{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 },
+{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 },
{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 },
@@ -275,88 +277,88 @@ const struct mips_opcode mips16_opcodes[] =
{"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 },
{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 },
{"extend", "e", 0xf000, 0xf800, 0, 0, I1, 0, 0 },
-{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
-{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
-{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
-{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
-{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
-{"jalx", "i", 0x1c00, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
-{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
+{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 },
+{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 },
+{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 },
+{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 },
+{"jal", "a", 0x1800, 0xfc00, WR_31|UBD, 0, I1, 0, 0 },
+{"jalx", "i", 0x1c00, 0xfc00, WR_31|UBD, 0, I1, 0, 0 },
+{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 },
{"jr", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
-{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
+{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 },
{"j", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 },
/* MIPS16e compact branches. We keep them near the ordinary branches
so that we easily find them when converting a normal branch to a
compact one. */
-{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|NODS, UBR, I32, 0, 0 },
-{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|NODS, UBR, I32, 0, 0 },
-{"jrc", "x", 0xe880, 0xf8ff, RD_x|NODS, UBR, I32, 0, 0 },
-{"jrc", "R", 0xe8a0, 0xffff, NODS, UBR|RD_31, I32, 0, 0 },
-{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
-{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
-{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
-{"ld", "y,B", 0xfc00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
-{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y, RD_PC, I3, 0, 0 },
-{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
-{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
-{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
-{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1, 0, 0 },
-{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
-{"lw", "x,A", 0xb000, 0xf800, WR_x, RD_PC, I1, 0, 0 },
-{"lw", "x,V(P)", 0xb000, 0xf800, WR_x, RD_PC, I1, 0, 0 },
-{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
-{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
-{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1, 0, 0 },
-{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1, 0, 0 },
-{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1, 0, 0 },
-{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1, 0, 0 },
+{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, UBR, I32, 0, 0 },
+{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, UBR, I32, 0, 0 },
+{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, UBR, I32, 0, 0 },
+{"jrc", "R", 0xe8a0, 0xffff, NODS, RD_31|UBR, I32, 0, 0 },
+{"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
+{"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
+{"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
+{"ld", "y,B", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"ld", "y,D(P)", 0xfc00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
+{"ld", "y,D(S)", 0xf800, 0xff00, WR_1, RD_SP, I3, 0, 0 },
+{"lh", "y,H(x)", 0x8800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
+{"lhu", "y,H(x)", 0xa800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
+{"li", "x,U", 0x6800, 0xf800, WR_1, 0, I1, 0, 0 },
+{"lw", "y,W(x)", 0x9800, 0xf800, WR_1|RD_3, 0, I1, 0, 0 },
+{"lw", "x,A", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 },
+{"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 },
+{"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 },
+{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, 0, I1, 0, 0 },
+{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, 0, I1, 0, 0 },
+{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, 0, I1, 0, 0 },
+{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, 0, I1, 0, 0 },
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
-{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
-{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
-{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 },
-{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 },
-{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
-{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 },
+{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 },
+{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
-{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
+{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 },
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
-{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
-{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3, 0, 0 },
-{"sd", "y,D(S)", 0xf900, 0xff00, RD_y, RD_PC, I3, 0, 0 },
-{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_PC|RD_31, I1, 0, 0 },
-{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
-{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
-{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
-{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
-{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
-{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
-{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
-{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
-{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 },
+{"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
+{"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 },
+{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_PC, I3, 0, 0 },
+{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_PC, I1, 0, 0 },
+{"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
+{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
+{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
+{"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 },
+{"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 },
+{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
+{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 },
+{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
+{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
-{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
-{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1, 0, 0 },
-{"sw", "R,V(S)", 0x6200, 0xff00, RD_SP, RD_31, I1, 0, 0 },
-{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
+{"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 },
+{"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 },
+{"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 },
+{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 },
/* MIPS16e additions */
{"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 },
-{"save", "m", 0x6480, 0xff80, NODS, MOD_SP|RD_31, I32, 0, 0 },
+{"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 },
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 },
-{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
-{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
-{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 },
-{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
-{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
-{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 },
+{"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 },
+{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 },
+{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 },
+{"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 },
+{"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 },
+{"zew", "x", 0xe851, 0xf8ff, MOD_1, 0, I64, 0, 0 },
};
const int bfd_mips16_num_opcodes =