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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 01:53:03 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 11:52:11 +0000 |
| commit | 4ebce1a0a5911e71aa2d00932ffb2126ff1f3633 (patch) | |
| tree | 0896d0aaa8e3ba12db285c77e7a572822f6e007b /opcodes/mips16-opc.c | |
| parent | c97dda72b905d5ba9b82004bf4e57dd4cf343147 (diff) | |
| download | gdb-4ebce1a0a5911e71aa2d00932ffb2126ff1f3633.zip gdb-4ebce1a0a5911e71aa2d00932ffb2126ff1f3633.tar.gz gdb-4ebce1a0a5911e71aa2d00932ffb2126ff1f3633.tar.bz2 | |
MIPS16/opcodes: Correct 64-bit macros' ISA membership
Limit the DDIV, DDIVU, DREM, DREMU and DSUBU macros to the MIPS III
rather than MIPS I ISA. These macros expand to machine code sequences
including 64-bit instructions which require a 64-bit ISA. Entries for
those instructions are already correctly marked, however the marking is
ignored if entries are used in the process of macro expansion rather
than directly, making it possible to indirectly produce 64-bit machine
code even when output requested has been limited to a 32-bit ISA.
opcodes/
* mips16-opc.c (mips16_opcodes): Set membership to I3 rather
than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
INSN_MACRO entries.
gas/
* testsuite/gas/mips/mips16-macro.l: New list test.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'opcodes/mips16-opc.c')
| -rw-r--r-- | opcodes/mips16-opc.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 14d82bf..0c4bb7f 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -241,9 +241,9 @@ const struct mips_opcode mips16_opcodes[] = {"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, {"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, {"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, {"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, {"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, {"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, @@ -252,9 +252,9 @@ const struct mips_opcode mips16_opcodes[] = {"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, {"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, {"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, {"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, {"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, {"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, {"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, @@ -265,8 +265,8 @@ const struct mips_opcode mips16_opcodes[] = {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, {"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, {"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, +{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, +{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 }, {"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 }, {"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 }, {"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 }, |