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authorH.J. Lu <hjl.tools@gmail.com>2015-08-12 04:45:07 -0700
committerH.J. Lu <hjl.tools@gmail.com>2015-08-12 04:45:07 -0700
commit43e65147c07b1400ae0dbb6694882eceb2363713 (patch)
treee52d56a58d00c74db6c82e736464ab0f500a7181 /opcodes/lm32-asm.c
parentf3445b37b67deb8f67f7885274b2544684503f78 (diff)
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Remove trailing spaces in opcodes
Diffstat (limited to 'opcodes/lm32-asm.c')
-rw-r--r--opcodes/lm32-asm.c38
1 files changed, 19 insertions, 19 deletions
diff --git a/opcodes/lm32-asm.c b/opcodes/lm32-asm.c
index e69a023..3ae16ae 100644
--- a/opcodes/lm32-asm.c
+++ b/opcodes/lm32-asm.c
@@ -352,7 +352,7 @@ lm32_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
-cgen_parse_fn * const lm32_cgen_parse_handlers[] =
+cgen_parse_fn * const lm32_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@@ -382,9 +382,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
-char *
+char *
lm32_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@ -423,18 +423,18 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@ -464,20 +464,20 @@ lm32_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
@@ -676,7 +676,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@@ -736,7 +736,7 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@@ -745,11 +745,11 @@ lm32_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
-
+
*errmsg = errbuf;
return NULL;
}