gas/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add .sse4.1.
	(process_operands): Adjust implicit operand for blendvpd,
	blendvps and pblendvb in SSE4.1.
	(output_insn): Support SSE4.1.

gas/testsuite/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.

	* gas/i386/sse4_1.d: New file.
	* gas/i386/sse4_1.s: Likewise.
	* gas/i386/x86-64-sse4_1.d: Likewise.
	* gas/i386/x86-64-sse4_1.s: Likewise.

opcodes/

2007-04-18  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (XMM_Fixup): New.
	(Edqb): New.
	(Edqd): New.
	(XMM0): New.
	(dqb_mode): New.
	(dqd_mode): New.
	(PREGRP39 ... PREGRP85): New.
	(threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
	(threebyte_0x3a_uses_DATA_prefix): Likewise.
	(prefix_user_table): Add PREGRP39 ... PREGRP85.
	(three_byte_table): Likewise.
	(putop): Handle 'K'.
	(intel_operand_size): Handle dqb_mode, dqd_mode):
	(OP_E): Likewise.
	(OP_G): Likewise.

	* i386-opc.c (i386_optab): Add SSE4.1 opcodes.

	* i386-opc.h (CpuSSE4_1): New.
	(CpuUnknownFlags): Add CpuSSE4_1.
	(regKludge): Update comment.

1 files changed, 55 insertions, 0 deletions

diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c
index 7d9d44f..b1b62a6 100644
--- a/opcodes/i386-opc.c
+++ b/opcodes/i386-opc.c
@@ -1167,6 +1167,10 @@ const template i386_optab[] =
 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pextrw",    3, 0x0fc5,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegMMX, Reg32|Reg64 } },
 {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegXMM, Reg32|Reg64 } },
+
+/* Streaming SIMD extensions 4.1 Instructions.  */
+{"pextrw",    3, 0x660f3a15,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64|ShortMem } },
+
 {"pinsrw",    3, 0x0fc4,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ShortMem, RegMMX } },
 {"pinsrw",    3, 0x660fc4,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ShortMem, RegXMM } },
 {"pmaxsw",    2, 0x0fee,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
@@ -1380,6 +1384,57 @@ const template i386_optab[] =
 {"pabsd",    2,    0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,	{ RegMMX|LongMem, RegMMX, 0 } },
 {"pabsd",    2,  0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
+/* Streaming SIMD extensions 4.1 Instructions.  */
+
+{"blendpd",  3,  0x660f3a0d,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"blendps",  3,  0x660f3a0c,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"blendvpd", 3,  0x660f3815,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"blendvps", 3,  0x660f3814,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"dppd",     3,  0x660f3a41,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"dpps",     3,  0x660f3a40,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"extractps",3,  0x660f3a17,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM, Reg32|Reg64|LongMem } },
+{"insertps", 3,  0x660f3a21,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
+{"movntdqa", 2,  0x660f382a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"mpsadbw",  3,  0x660f3a42,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"packusdw", 2,  0x660f382b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pblendvb", 3,  0x660f3810,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm|regKludge, { RegXMM, RegXMM|LLongMem, RegXMM } },
+{"pblendw",  3,  0x660f3a0e,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"pcmpeqq",  2,  0x660f3829,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pextrb",   3,  0x660f3a14,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM, Reg32|Reg64|ByteMem } },
+{"pextrd",   3,  0x660f3a16,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM, Reg32|LongMem } },
+{"pextrq",   3,  0x660f3a16,X, CpuSSE4_1|Cpu64, NoSuf|IgnoreSize|Modrm|Size64, { Imm8, RegXMM, Reg64|LLongMem } },
+{"phminposuw",2, 0x660f3841,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pinsrb",   3,  0x660f3a20,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ByteMem, RegXMM } },
+{"pinsrd",   3,  0x660f3a22,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, Reg32|LongMem, RegXMM } },
+{"pinsrq",   3,  0x660f3a22,X, CpuSSE4_1|Cpu64, NoSuf|IgnoreSize|Modrm|Size64, { Imm8, Reg64|LLongMem, RegXMM } },
+{"pmaxsb",   2,  0x660f383c,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaxsd",   2,  0x660f383d,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaxud",   2,  0x660f383f,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaxuw",   2,  0x660f383e,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminsb",   2,  0x660f3838,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminsd",   2,  0x660f3839,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminud",   2,  0x660f383b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pminuw",   2,  0x660f383a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovsxbw", 2,  0x660f3820,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovsxbd", 2,  0x660f3821,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"pmovsxbq", 2,  0x660f3822,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|ShortMem, RegXMM, 0 } },
+{"pmovsxwd", 2,  0x660f3823,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovsxwq", 2,  0x660f3824,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"pmovsxdq", 2,  0x660f3825,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovzxbw", 2,  0x660f3830,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovzxbd", 2,  0x660f3831,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"pmovzxbq", 2,  0x660f3832,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|ShortMem, RegXMM, 0 } },
+{"pmovzxwd", 2,  0x660f3833,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmovzxwq", 2,  0x660f3834,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
+{"pmovzxdq", 2,  0x660f3835,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmuldq",   2,  0x660f3828,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulld",   2,  0x660f3840,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"ptest",    2,  0x660f3817,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"roundpd",  3,  0x660f3a09,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"roundps",  3,  0x660f3a08,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"roundsd",  3,  0x660f3a0b,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LLongMem, RegXMM } },
+{"roundss",  3,  0x660f3a0a,X, CpuSSE4_1, NoSuf|IgnoreSize|Modrm,	{ Imm8, RegXMM|LongMem, RegXMM } },
+
 /* AMD 3DNow! instructions.  */
 
 {"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, NoSuf|IgnoreSize|Modrm,	{ ByteMem, 0, 0 } },