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author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-09-12 13:10:14 +0100 |
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committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-07 21:54:19 +0000 |
commit | f3f6c0df60c4e8a6c3409db4f23f2cdec5a9d41c (patch) | |
tree | befa3e9332d98f77d7168b4b0a11f3a09909e1e1 /opcodes/fr30-opc.c | |
parent | f0d70d8ee63b6f6a59cf4a10268f546b0bc80777 (diff) | |
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aarch64: Add LSE128 instructions
Implement, together with the necessary tests, the following new LSE128
atomic instructions:
* Atomic bit clear on quadword in memory (ldclrp{a|l|al});
* Atomic bit set on quadword in memory (ldsetp{a|l|al});
* Swap quadword in memory (swpp{a|l|al});
gas/ChangeLog:
* testsuite/gas/aarch64/lse128-atomic.d: New.
* testsuite/gas/aarch64/lse128-atomic.s: Likewise.
opcodes/ChangeLog:
* aarch64-tbl.h (ldclrp): new _LSE128_INSN entry.
(ldclrpa): Likewise.
(ldclrpal): Likewise.
(ldclrpl): Likewise.
(ldsetp): Likewise.
(ldsetpa): Likewise.
(ldsetpal): Likewise.
(ldsetpl): Likewise.
(swpp): Likewise.
(swppa): Likewise.
(swppal): Likewise.
(swppl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
Diffstat (limited to 'opcodes/fr30-opc.c')
0 files changed, 0 insertions, 0 deletions