CSKY: Fix and add some instructions for VDSPV1.

gas/
	* config/tc-csky.c (get_operand_value): Add handler for
	OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
	* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
	for vector register.

opcodes/
	* csky-dis.c (csky_output_operand): Add handler for
	OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
	* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
	(OPRND_TYPE_IMM5b_VSH): New enum.
	(csky_v2_opcodes): Fix and add some instructions for VDSPV1.

Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb

1 files changed, 205 insertions, 38 deletions

diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 199b891..e309253 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -44,6 +44,7 @@ enum operand_type
   OPRND_TYPE_AREG_WITH_LSHIFT_FPU,
 
   OPRND_TYPE_FREG_WITH_INDEX,
+  OPRND_TYPE_VREG_WITH_INDEX,
   /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA.  */
   OPRND_TYPE_REG_r1a,
   /* r1 only, for divs/divu in csky v1 ISA.  */
@@ -133,6 +134,7 @@ enum operand_type
   OPRND_TYPE_IMM5b_LS,
   /* Operand type for rori and rotri.  */
   OPRND_TYPE_IMM5b_RORI,
+  OPRND_TYPE_IMM5b_VSH,
   OPRND_TYPE_IMM5b_POWER,
   OPRND_TYPE_IMM5b_7_31_POWER,
   OPRND_TYPE_IMM5b_BMASKI,
@@ -6416,200 +6418,215 @@ const struct csky_opcode csky_v2_opcodes[] =
     /* The followings are vdsp instructions for ck810.  */
     OP32 ("vdup.8",
 	  OPCODE_INFO2 (0xf8000e80,
-			(0_3, FREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vdup.16",
 	  OPCODE_INFO2 (0xf8100e80,
-			(0_3, FREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vdup.32",
 	  OPCODE_INFO2 (0xfa000e80,
-			(0_3, FREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmfvr.u8",
 	  OPCODE_INFO2 (0xf8001200,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmfvr.u16",
 	  OPCODE_INFO2 (0xf8001220,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmfvr.u32",
 	  OPCODE_INFO2 (0xf8001240,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmfvr.s8",
 	  OPCODE_INFO2 (0xf8001280,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmfvr.s16",
 	  OPCODE_INFO2 (0xf80012a0,
 			(0_4, AREG, OPRND_SHIFT_0_BIT),
-			(16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmtvr.u8",
 	  OPCODE_INFO2 (0xf8001300,
-			(0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
 			(16_20, AREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vmtvr.u16",
 	  OPCODE_INFO2 (0xf8001320,
-			(0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
 			(16_20, AREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
+    OP32 ("vins.8",
+	  OPCODE_INFO2 (0xf8001400,
+			(0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vins.16",
+	  OPCODE_INFO2 (0xf8101400,
+			(0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vins.32",
+	  OPCODE_INFO2 (0xfa001400,
+			(0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
     OP32 ("vmtvr.u32",
 	  OPCODE_INFO2 (0xf8001340,
-			(0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
+			(0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT),
 			(16_20, AREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
     OP32 ("vldd.8",
 	  SOPCODE_INFO2 (0xf8002000,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldd.16",
 	  SOPCODE_INFO2 (0xf8002100,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldd.32",
 	  SOPCODE_INFO2 (0xf8002200,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldq.8",
 	  SOPCODE_INFO2 (0xf8002400,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldq.16",
 	  SOPCODE_INFO2 (0xf8002500,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldq.32",
 	  SOPCODE_INFO2 (0xf8002600,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstd.8",
 	  SOPCODE_INFO2 (0xf8002800,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstd.16",
 	  SOPCODE_INFO2 (0xf8002900,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstd.32",
 	  SOPCODE_INFO2 (0xf8002a00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstq.8",
 	  SOPCODE_INFO2 (0xf8002c00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstq.16",
 	  SOPCODE_INFO2 (0xf8002d00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstq.32",
 	  SOPCODE_INFO2 (0xf8002e00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrd.8",
 	  SOPCODE_INFO2 (0xf8003000,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrd.16",
 	  SOPCODE_INFO2 (0xf8003100,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrd.32",
 	  SOPCODE_INFO2 (0xf8003200,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrq.8",
 	  SOPCODE_INFO2 (0xf8003400,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrq.16",
 	  SOPCODE_INFO2 (0xf8003500,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vldrq.32",
 	  SOPCODE_INFO2 (0xf8003600,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrd.8",
 	  SOPCODE_INFO2 (0xf8003800,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrd.16",
 	  SOPCODE_INFO2 (0xf8003900,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrd.32",
 	  SOPCODE_INFO2 (0xf8003a00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrq.8",
 	  SOPCODE_INFO2 (0xf8003c00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrq.16",
 	  SOPCODE_INFO2 (0xf8003d00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
     OP32 ("vstrq.32",
 	  SOPCODE_INFO2 (0xf8003e00,
-			 (0_3, FREG, OPRND_SHIFT_0_BIT),
+			 (0_3, VREG, OPRND_SHIFT_0_BIT),
 			 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT),
 					(5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))),
 	  CSKY_ISA_VDSP),
@@ -7888,6 +7905,84 @@ const struct csky_opcode csky_v2_opcodes[] =
 			(16_19, VREG, OPRND_SHIFT_0_BIT),
 			(21_24, VREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u8",
+	  OPCODE_INFO3 (0xf8000600,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u16",
+	  OPCODE_INFO3 (0xf8100600,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u32",
+	  OPCODE_INFO3 (0xfa000600,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s8",
+	  OPCODE_INFO3 (0xf8000610,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s16",
+	  OPCODE_INFO3 (0xf8100610,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s32",
+	  OPCODE_INFO3 (0xfa000610,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u8.r",
+	  OPCODE_INFO3 (0xf8000640,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u16.r",
+	  OPCODE_INFO3 (0xf8100640,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.u32.r",
+	  OPCODE_INFO3 (0xfa000640,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s8.r",
+	  OPCODE_INFO3 (0xf8000650,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s16.r",
+	  OPCODE_INFO3 (0xf8100650,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshri.s32.r",
+	  OPCODE_INFO3 (0xfa000650,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshr.s32.r",
+	  OPCODE_INFO3 (0xfa0006d0,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(21_24, VREG, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
     OP32 ("vshr.s32.r",
 	  OPCODE_INFO3 (0xfa0006d0,
 			(0_3, VREG, OPRND_SHIFT_0_BIT),
@@ -7966,6 +8061,78 @@ const struct csky_opcode csky_v2_opcodes[] =
 			(16_19, VREG, OPRND_SHIFT_0_BIT),
 			(21_24, VREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u8",
+	  OPCODE_INFO3 (0xf8000700,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u16",
+	  OPCODE_INFO3 (0xf8100700,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u32",
+	  OPCODE_INFO3 (0xfa000700,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s8",
+	  OPCODE_INFO3 (0xf8000710,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s16",
+	  OPCODE_INFO3 (0xf8100710,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s32",
+	  OPCODE_INFO3 (0xfa000710,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u8.s",
+	  OPCODE_INFO3 (0xf8000740,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u16.s",
+	  OPCODE_INFO3 (0xf8100740,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.u32.s",
+	  OPCODE_INFO3 (0xfa000740,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s8.s",
+	  OPCODE_INFO3 (0xf8000750,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s16.s",
+	  OPCODE_INFO3 (0xf8100750,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
+    OP32 ("vshli.s32.s",
+	  OPCODE_INFO3 (0xfa000750,
+			(0_3, VREG, OPRND_SHIFT_0_BIT),
+			(16_19, VREG, OPRND_SHIFT_0_BIT),
+			(5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_VDSP),
     OP32 ("vcmphs.u8",
 	  OPCODE_INFO3 (0xf8000800,
 			(0_3, VREG, OPRND_SHIFT_0_BIT),