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| author | srinath <srinath.parvathaneni@arm.com> | 2023-11-02 13:04:20 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-02 13:06:00 +0000 |
| commit | f985c2512aee1c4440998db62d6aea98c737b3ef (patch) | |
| tree | ad00ac3226ee025d907b7706bd95ce8bc8fbf7f2 /opcodes/aarch64-tbl.h | |
| parent | 6c0ecdbad70456b22b538d957e93478b14d0e0bc (diff) | |
| download | gdb-f985c2512aee1c4440998db62d6aea98c737b3ef.zip gdb-f985c2512aee1c4440998db62d6aea98c737b3ef.tar.gz gdb-f985c2512aee1c4440998db62d6aea98c737b3ef.tar.bz2 | |
aarch64: Add support for GCS extension.
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is
optional from Armv9.4-A architecture and enabled by passing +gcs option to -march
(eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file.
Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx,
gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 8f4bfc3..f281fd5 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2574,6 +2574,8 @@ static const aarch64_feature_set aarch64_feature_cssc = AARCH64_FEATURE (CSSC); static const aarch64_feature_set aarch64_feature_chk = AARCH64_FEATURE (CHK); +static const aarch64_feature_set aarch64_feature_gcs = + AARCH64_FEATURE (GCS); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2633,6 +2635,7 @@ static const aarch64_feature_set aarch64_feature_chk = #define HBC &aarch64_feature_hbc #define CSSC &aarch64_feature_cssc #define CHK &aarch64_feature_chk +#define GCS &aarch64_feature_gcs #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2782,6 +2785,8 @@ static const aarch64_feature_set aarch64_feature_chk = { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } +#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ + { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -4141,6 +4146,16 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0), CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0), + GCS_INSN ("gcspushx", 0xd508779f, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopx", 0xd50877df, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopcx", 0xd50877bf, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcsss1", 0xd50b7740, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcspushm", 0xd50b7700, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), + GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), |