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authorPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-11-17 19:31:25 +0000
committerPrzemyslaw Wirkus <przemyslaw.wirkus@arm.com>2021-11-17 19:32:17 +0000
commit7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a (patch)
treee8a7449925ac32ef3a5ebf0db7276c348ca5bb8c /opcodes/aarch64-opc.h
parent971eda734150ea9cdea47be259486c3a8d087037 (diff)
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aarch64: [SME] Add MOV and MOVA instructions
This patch is adding new MOV (alias) and MOVA SME instruction. gas/ChangeLog: * config/tc-aarch64.c (enum sme_hv_slice): new enum. (struct reloc_entry): Added ZAH and ZAV registers. (parse_sme_immediate): Immediate parser. (parse_sme_za_hv_tiles_operand): ZA tile parser. (parse_sme_za_hv_tiles_operand_index): Index parser. (parse_operands): Added ZA tile parser calls. (REGNUMS): New macro. Regs with suffix. (REGSET16S): New macro. 16 regs with suffix. * testsuite/gas/aarch64/sme-2-illegal.d: New test. * testsuite/gas/aarch64/sme-2-illegal.l: New test. * testsuite/gas/aarch64/sme-2-illegal.s: New test. * testsuite/gas/aarch64/sme-2.d: New test. * testsuite/gas/aarch64/sme-2.s: New test. * testsuite/gas/aarch64/sme-2a.d: New test. * testsuite/gas/aarch64/sme-2a.s: New test. * testsuite/gas/aarch64/sme-3-illegal.d: New test. * testsuite/gas/aarch64/sme-3-illegal.l: New test. * testsuite/gas/aarch64/sme-3-illegal.s: New test. * testsuite/gas/aarch64/sme-3.d: New test. * testsuite/gas/aarch64/sme-3.s: New test. * testsuite/gas/aarch64/sme-3a.d: New test. * testsuite/gas/aarch64/sme-3a.s: New test. include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): New enums AARCH64_OPND_SME_ZA_HV_idx_src and AARCH64_OPND_SME_ZA_HV_idx_dest. (struct aarch64_opnd_info): New ZA tile vector struct. opcodes/ChangeLog: * aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_sme_za_hv_tiles. * aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_sme_za_hv_tiles. * aarch64-opc.c (aarch64_print_operand): Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest. * aarch64-opc.h (enum aarch64_field_kind): New enums FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv. (struct aarch64_operand): Increase fields size to 5. * aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers aarch64-asm-2.c: Regenerate. aarch64-dis-2.c: Regenerate. aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-opc.h')
-rw-r--r--opcodes/aarch64-opc.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index ba19c12..9c657df 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -71,6 +71,7 @@ enum aarch64_field_kind
FLD_imm4,
FLD_imm4_2,
FLD_imm4_3,
+ FLD_imm4_5,
FLD_imm5,
FLD_imm7,
FLD_imm8,
@@ -152,6 +153,10 @@ enum aarch64_field_kind
FLD_SVE_xs_22,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
+ FLD_SME_size_10,
+ FLD_SME_Q,
+ FLD_SME_V,
+ FLD_SME_Rv,
FLD_SME_Pm,
FLD_rotate1,
FLD_rotate2,
@@ -186,7 +191,7 @@ struct aarch64_operand
/* The associated instruction bit-fields; no operand has more than 4
bit-fields */
- enum aarch64_field_kind fields[4];
+ enum aarch64_field_kind fields[5];
/* Brief description */
const char *desc;