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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 11:30:24 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | f50b1a3c1f9514efdff6d808b2700eb18ab55630 (patch) | |
| tree | 2e56bf3b6c0291ba5507d7110f7e0e11774f1df0 /opcodes/aarch64-opc.c | |
| parent | f5f38efc0a20cb50105da4fd2f656cda4561ccc2 (diff) | |
| download | gdb-f50b1a3c1f9514efdff6d808b2700eb18ab55630.zip gdb-f50b1a3c1f9514efdff6d808b2700eb18ab55630.tar.gz gdb-f50b1a3c1f9514efdff6d808b2700eb18ab55630.tar.bz2 | |
aarch64: Fix sve2p1 extq instruction operands.
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction. Also removed the unused operand
AARCH64_OPND_SVE_Zm_imm4.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 918d988..6393474 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1852,11 +1852,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; - case AARCH64_OPND_SVE_Zm_imm4: - if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 15)) - return 0; - break; - case AARCH64_OPND_SVE_Zn_5_INDEX: size = aarch64_get_qualifier_esize (opnd->qualifier); if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, @@ -2742,6 +2737,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_UIMM3: case AARCH64_OPND_SVE_UIMM7: case AARCH64_OPND_SVE_UIMM8: + case AARCH64_OPND_SVE_UIMM4: case AARCH64_OPND_SVE_UIMM8_53: case AARCH64_OPND_CSSC_UIMM8: size = get_operand_fields_width (get_operand_from_code (type)); @@ -4296,7 +4292,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_Zn_INDEX3_14: case AARCH64_OPND_SME_Zn_INDEX3_15: case AARCH64_OPND_SME_Zn_INDEX4_14: - case AARCH64_OPND_SVE_Zm_imm4: snprintf (buf, size, "%s[%s]", (opnd->qualifier == AARCH64_OPND_QLF_NIL ? style_reg (styler, "z%d", opnd->reglane.regno) @@ -4463,6 +4458,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_UIMM3: case AARCH64_OPND_SVE_UIMM7: case AARCH64_OPND_SVE_UIMM8: + case AARCH64_OPND_SVE_UIMM4: case AARCH64_OPND_SVE_UIMM8_53: case AARCH64_OPND_IMM_ROT1: case AARCH64_OPND_IMM_ROT2: @@ -5590,7 +5586,8 @@ verify_constraints (const struct aarch64_inst *inst, instruction for better error messages. */ if (!opcode->avariant || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE) - && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2))) + && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2) + && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1))) { mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR; mismatch_detail->error = _("SVE instruction expected after " |