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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:24 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:24 +0000 |
| commit | 31a8056f2f519fda71682cffd0eac6ba87a59c8e (patch) | |
| tree | 9434d8f31b29e4ab743cf8c340a33623b9e59a8d /opcodes/aarch64-opc.c | |
| parent | 2dd3146b4ffcb8528a6e093741ba31636afdf8ae (diff) | |
| download | gdb-31a8056f2f519fda71682cffd0eac6ba87a59c8e.zip gdb-31a8056f2f519fda71682cffd0eac6ba87a59c8e.tar.gz gdb-31a8056f2f519fda71682cffd0eac6ba87a59c8e.tar.bz2 | |
aarch64: Remove duplicate system register entries
There is a lot of overlap between the ETM and ETE system registers,
so some registers were listed twice.
Already tested by etm.[sd] and ete.[sd].
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Combine ETE and ETM blocks
and remove redundant entries.
gas/
* testsuite/gas/aarch64/etm.s: Remove duplicated test.
* testsuite/gas/aarch64/etm.d: Update accordingly.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ef0ba8a..714c705 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4486,12 +4486,6 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0), SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0), - SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0), - SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0), - SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0), - SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0), - SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0), - SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ), SR_CORE ("trccidr0", CPENC (2,1,C7,C12,7), F_REG_READ), SR_CORE ("trccidr1", CPENC (2,1,C7,C13,7), F_REG_READ), @@ -4612,7 +4606,6 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0), SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0), SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0), - SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0), SR_CORE ("trcimspec1", CPENC (2,1,C0,C1,7), 0), SR_CORE ("trcimspec2", CPENC (2,1,C0,C2,7), 0), SR_CORE ("trcimspec3", CPENC (2,1,C0,C3,7), 0), @@ -4625,6 +4618,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("trcprgctlr", CPENC (2,1,C0,C1,0), 0), SR_CORE ("trcprocselr", CPENC (2,1,C0,C2,0), 0), SR_CORE ("trcqctlr", CPENC (2,1,C0,C1,1), 0), + SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0), SR_CORE ("trcrsctlr2", CPENC (2,1,C1,C2,0), 0), SR_CORE ("trcrsctlr3", CPENC (2,1,C1,C3,0), 0), SR_CORE ("trcrsctlr4", CPENC (2,1,C1,C4,0), 0), |