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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:02:03 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | 524e985281588b929b75c9dc5adf56c19de1d0b8 (patch) | |
| tree | 8cb3a966c1d203452026243bb7fd56a847d5f898 /opcodes/aarch64-dis-2.c | |
| parent | 98043d5fae27fa31e65e421ba1aef18732b2acd5 (diff) | |
| download | gdb-524e985281588b929b75c9dc5adf56c19de1d0b8.zip gdb-524e985281588b929b75c9dc5adf56c19de1d0b8.tar.gz gdb-524e985281588b929b75c9dc5adf56c19de1d0b8.tar.bz2 | |
aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.
The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.*
to maintain consistency in the testsuite.
The bfloat16-1-invalid.* tests are modified so that "selected
processor does not support" is generated by the assembler, since
+b16b16 is not passed in the command line.
The bfloat16-2-invalid.* testcase includes the wrong operands
bfloat16 tests.
Diffstat (limited to 'opcodes/aarch64-dis-2.c')
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 95342ce..49ca823 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -17566,7 +17566,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x00x1xxxxx000x10xxxxxxxxxx bfmla. */ - return 3295; + return 3292; } } else @@ -17585,7 +17585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x00x1xxxxx000x11xxxxxxxxxx bfmls. */ - return 3296; + return 3293; } } } @@ -33782,16 +33782,16 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 1697: return NULL; /* ldff1b --> NULL. */ case 1715: value = 1716; break; /* ldff1h --> ldff1h. */ case 1716: return NULL; /* ldff1h --> NULL. */ - case 2475: value = 3292; break; /* fclamp --> bfclamp. */ - case 3292: return NULL; /* bfclamp --> NULL. */ + case 2475: value = 3291; break; /* fclamp --> bfclamp. */ + case 3291: return NULL; /* bfclamp --> NULL. */ case 1789: value = 1790; break; /* ldr --> ldr. */ case 1790: return NULL; /* ldr --> NULL. */ - case 1445: value = 3291; break; /* fadd --> bfadd. */ - case 3291: return NULL; /* bfadd --> NULL. */ - case 1512: value = 3293; break; /* fmul --> bfmul. */ - case 3293: return NULL; /* bfmul --> NULL. */ - case 1538: value = 3294; break; /* fsub --> bfsub. */ - case 3294: return NULL; /* bfsub --> NULL. */ + case 1445: value = 3294; break; /* fadd --> bfadd. */ + case 3294: return NULL; /* bfadd --> NULL. */ + case 1512: value = 3295; break; /* fmul --> bfmul. */ + case 3295: return NULL; /* bfmul --> NULL. */ + case 1538: value = 3296; break; /* fsub --> bfsub. */ + case 3296: return NULL; /* bfsub --> NULL. */ case 1503: value = 3287; break; /* fmla --> bfmla. */ case 3287: return NULL; /* bfmla --> NULL. */ case 2008: value = 2009; break; /* str --> str. */ |