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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:24 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:24 +0100 |
| commit | 31e36ab341498bb477a46a0475100ec5d471c4f2 (patch) | |
| tree | fb56a49e0b0fd35ecabbf84b3dc7f128ba84441d /opcodes/aarch64-dis-2.c | |
| parent | 1be5f94f9c85821287b9ae423f738a8bab499526 (diff) | |
| download | gdb-31e36ab341498bb477a46a0475100ec5d471c4f2.zip gdb-31e36ab341498bb477a46a0475100ec5d471c4f2.tar.gz gdb-31e36ab341498bb477a46a0475100ec5d471c4f2.tar.bz2 | |
[binutils][aarch64] New SVE_Zm4_11_INDEX operand.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
Diffstat (limited to 'opcodes/aarch64-dis-2.c')
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index d70a290..16faf59 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -20078,8 +20078,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 191: case 192: case 193: - case 198: - case 201: + case 199: + case 202: return aarch64_ext_regno (self, info, code, inst, errors); case 9: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 204: + case 205: return aarch64_ext_reglane (self, info, code, inst, errors); case 35: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -20140,7 +20140,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 182: case 183: case 184: - case 203: + case 204: return aarch64_ext_imm (self, info, code, inst, errors); case 43: case 44: @@ -20289,11 +20289,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 195: case 196: case 197: + case 198: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 199: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 200: - case 202: + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 201: + case 203: return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } |