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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 16:32:21 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 16:32:21 +0000 |
| commit | 622b9eb1a6047bd3ad3e1a3f120cf7318ac25b57 (patch) | |
| tree | ac51bb2427fc5af358e473775b99a31857313c3d /opcodes/ChangeLog | |
| parent | cf86120bae8973340583a0613ad622f0ca013efd (diff) | |
| download | gdb-622b9eb1a6047bd3ad3e1a3f120cf7318ac25b57.zip gdb-622b9eb1a6047bd3ad3e1a3f120cf7318ac25b57.tar.gz gdb-622b9eb1a6047bd3ad3e1a3f120cf7318ac25b57.tar.bz2 | |
[AArch64][PATCH 3/3] Add floating-point FP16 instructions
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch adds the new FP16 instructions,
making them available when the architecture extension +fp+fp16 is
specified.
The instructions added are:
- Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL.
- Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB,
FNMADD and FNMSUB.
- Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI.
- Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point)
UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU
(fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU,
FCVTPS, FCVTPU, FCVTMS and FCVTMU.
- Scalar FMOV: immediate, general and register
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/float-fp16.d: New.
* gas/aarch64/float-fp16.s: New.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
(QL_INT2FP_H, QL_FP2INT_H): New.
(QL_FP2_H, QL_FP3_H, QL_FP4_H): New
(QL_DST_H): New.
(QL_FCCMP_H): New.
(aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
fcsel.
Change-Id: Ie6d40bd1b215a9bc024e12ba75e52afbe1675eb7
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 36b3d56..8024b52 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,23 @@ 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. + (QL_INT2FP_H, QL_FP2INT_H): New. + (QL_FP2_H, QL_FP3_H, QL_FP4_H): New + (QL_DST_H): New. + (QL_FCCMP_H): New. + (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, + fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, + fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, + fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, + frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, + fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and + fcsel. + +2015-11-27 Matthew Wahab <matthew.wahab@arm.com> + * aarch64-opc.c (half_conv_t): New. (expand_fp_imm): Replace is_dp flag with the parameter size to specify the number of bytes for the required expansion. Treat |