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| author | Tejas Belagod <tejas.belagod@arm.com> | 2021-04-09 12:21:38 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2021-04-09 12:27:54 +0100 |
| commit | 52efda8266cb1f8ade0193f45801fdd6e42165ac (patch) | |
| tree | 90be33f93f897c9524d0cbdb15240eb33f5798ad /opcodes/ChangeLog | |
| parent | c3f72de4f53bc3e5f13762633d78d8a7efb8dd79 (diff) | |
| download | gdb-52efda8266cb1f8ade0193f45801fdd6e42165ac.zip gdb-52efda8266cb1f8ade0193f45801fdd6e42165ac.tar.gz gdb-52efda8266cb1f8ade0193f45801fdd6e42165ac.tar.bz2 | |
AArch64: Fix Atomic LD64/ST64 classification.
Patch 1: Fix diagnostics for exclusive load/stores and reclassify
Armv8.7-A ST/LD64 Atomics.
Following upstream pointing out some inconsistencies in diagnostics,
https://sourceware.org/pipermail/binutils/2021-February/115356.html
attached is a patch set that fixes the issues. I believe a combination
of two patches mainly contributed to these bugs:
https://sourceware.org/pipermail/binutils/2020-November/113961.html
https://sourceware.org/pipermail/binutils/2018-June/103322.html
A summary of what this patch set fixes:
For instructions
STXR w0,x2,[x0]
STLXR w0,x2,[x0]
The warning we emit currently is misleading:
Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]'
it ought to be:
Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]'
For instructions:
ldaxp x0,x0,[x0]
ldxp x0,x0,[x0]
The warning we emit is incorrect
Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]'
Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]'
it ought to be:
Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]'
Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]'
For instructions
stlxp w0, x2, x2, [x0]
stxp w0, x2, x2, [x0]
We don't emit any warning when it ought to be:
Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]'
For instructions:
st64bv x0, x2, [x0]
st64bv x2, x0, [x0]
We incorrectly warn when its not necessary. This is because we classify them
incorrectly as ldstexcl when it should be lse_atomics in the opcode table.
The incorrect classification makes it pick up the warnings from warning on
exclusive load/stores.
Patch 2: Reclassify Armv8.7-A ST/LD64 Atomics.
This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl
according to their encoding class as specified in the architecture. This also
has the fortunate side-effect of spurious unpredictable warnings getting
eliminated.
For eg. For instruction:
st64bv x0, x2, [x0]
We incorrectly warn when its not necessary:
Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]'
This is because we classify them incorrectly as ldstexcl when it should be
lse_atomics in the opcode table. The incorrect classification makes it pick
up the warnings from warning on exclusive load/stores. This patch fixes it
by reclassifying it and no warnings are issued for this instruction.
opcodes/ChangeLog:
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
* aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
LD64/ST64 instructions to lse_atomic instead of ldstexcl.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f6c5eef..d2b5435 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-04-09 Tejas Belagod <tejas.belagod@arm.com> + + * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify + LD64/ST64 instructions to lse_atomic instead of ldstexcl. + 2021-04-09 Alan Modra <amodra@gmail.com> * ppc-dis.c (struct dis_private): Add "special". |