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| author | Jim Wilson <jimw@sifive.com> | 2018-01-09 16:40:06 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-01-09 16:40:06 -0800 |
| commit | 35fd2b2bcf370837a03f077acf1222f0a7e9c4d1 (patch) | |
| tree | 4c6fc1540f4073b297ddcb097539fce0f9f01a47 /opcodes/ChangeLog | |
| parent | d9ccd460fdbe0e0f3dd9263175aa4b23b207a51e (diff) | |
| download | gdb-35fd2b2bcf370837a03f077acf1222f0a7e9c4d1.zip gdb-35fd2b2bcf370837a03f077acf1222f0a7e9c4d1.tar.gz gdb-35fd2b2bcf370837a03f077acf1222f0a7e9c4d1.tar.bz2 | |
RISC-V: Disassemble x0 based addresses as 0.
gas/
* testsuite/gas/riscv/auipc-x0.d: New.
* testsuite/gas/riscv/auipc-x0.s: New.
opcodes/
* riscv-dis.c (maybe_print_address): If base_reg is zero,
then the hi_addr value is zero.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 96bc41c..24d1101 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-01-09 Jim Wilson <jimw@sifive.com> + + * riscv-dis.c (maybe_print_address): If base_reg is zero, + then the hi_addr value is zero. + 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. |