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| author | Jan Beulich <jbeulich@novell.com> | 2015-06-01 09:50:00 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2015-06-01 09:50:00 +0200 |
| commit | 015c54d5a6a052f074fab168bc70296131276e80 (patch) | |
| tree | b8c9f2048c1b8ace631bf6172b460a40273bd63e /opcodes/ChangeLog | |
| parent | b2e38b610c237b159578a595537d9c1137e7a6a0 (diff) | |
| download | gdb-015c54d5a6a052f074fab168bc70296131276e80.zip gdb-015c54d5a6a052f074fab168bc70296131276e80.tar.gz gdb-015c54d5a6a052f074fab168bc70296131276e80.tar.bz2 | |
x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.
gas/testsuite/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
* gas/i386/evex-lig256-intel.d: Likewise.
* gas/i386/evex-lig512-intel.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.
* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
* gas/i386/x86-64-evex-lig512-intel.d: Likewise.
opcodes/
2015-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
* i386-tbl.h: Regenerate.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ef05d2d..648669c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2015-06-01 Jan Beulich <jbeulich@suse.com> + + * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. + * i386-tbl.h: Regenerate. + 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. |