From 015c54d5a6a052f074fab168bc70296131276e80 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Mon, 1 Jun 2015 09:50:00 +0200 Subject: x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} As pointed out before, the documentation mandates the rounding mode to follow the GPR, so gas should accept such input. As the brojen code got released already we sadly will need to continue to also accept the badly ordered operands. gas/testsuite/ 2015-06-01 Jan Beulich * gas/i386/avx512f-intel.d: Adjust expectations on operand order. * gas/i386/evex-lig256-intel.d: Likewise. * gas/i386/evex-lig512-intel.d: Likewise. * gas/i386/x86-64-avx512f-intel.d: Likewise. * gas/i386/x86-64-evex-lig256-intel.d: Likewise. * gas/i386/x86-64-evex-lig512-intel.d: Likewise. opcodes/ 2015-06-01 Jan Beulich * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate. --- opcodes/ChangeLog | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'opcodes/ChangeLog') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ef05d2d..648669c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2015-06-01 Jan Beulich + + * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. + * i386-tbl.h: Regenerate. + 2015-05-18 H.J. Lu * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. -- cgit v1.1