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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:00:03 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | f3eefcc18bb6f1cc98831b063a58aa5a9ee0b811 (patch) | |
| tree | b2453b3a2eea55d833334e5734f6e7f2d3260d89 /libctf | |
| parent | 4f2cb9d129f8a5eba81379b70322d013b670045c (diff) | |
| download | gdb-f3eefcc18bb6f1cc98831b063a58aa5a9ee0b811.zip gdb-f3eefcc18bb6f1cc98831b063a58aa5a9ee0b811.tar.gz gdb-f3eefcc18bb6f1cc98831b063a58aa5a9ee0b811.tar.bz2 | |
arch64: Fix the wrong constraint used for sve2p1 instructions.
The current implementation for the following SVE2p1 instructions add a
constraint in aarch64_opcode_table[] array, so that these instruction
might be immediately preceded in program order by a MOVPRFX instruction.
As per the spec these instruction does not immediately preceded in
program order by a MOVPRFX instruction and to fix this issue, SVE2p1_INSNC
macro is replaced with SVE2p1_INSN macro for the entries of these
instructions in aarch64_opcode_table[] array.
List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv,
eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Diffstat (limited to 'libctf')
0 files changed, 0 insertions, 0 deletions