RISC-V: Fixed overwritten IRELATIVE relocs in the .rel.iplt for data reloc.

This was originally reported by Hau Hsu <hau.hsu@sifive.com>.

Similar to commit 51a8a7c2e3cc0730831963651a55d23d1fae624d

We shouldn't use riscv_elf_append_rela to add dynamic relocs into .rela.iplt
in the riscv_elf_relocate_section when handling ifunc data reloc R_RISCV_32/64.
This just like what did in the riscv_elf_finish_dynamic_symbol.

bfd/
	* elfnn-riscv.c (riscv_elf_relocate_section): We shouldn't use
	riscv_elf_append_rela to add dynamic relocs into .rela.iplt in the
	riscv_elf_relocate_section when handling ifunc data reloc.
ld/
	* testsuite/ld-riscv-elf/ifunc-overwrite.s: Updated and renamed.
	* testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd: Likewise.
	* testsuite/ld-riscv-elf/ifunc-overwrite.d: Renamed.

6 files changed, 28 insertions, 7 deletions

diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd
index 0de47a4..a99170c 100644
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd
+++ b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-exe.rd
@@ -2,3 +2,4 @@ Relocation section '.rela.plt' at .*
 [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd
index f65d789..85fbb4f 100644
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd
+++ b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-pic.rd
@@ -2,7 +2,11 @@ Relocation section '.rela.got' at .*
 [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_(32|64)[ 	]+foo2\(\)[ 	]+foo2 \+ 0
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_(32|64)[ 	]+foo1\(\)[ 	]+foo1 \+ 0
-#...
+
+Relocation section '.rela.ifunc' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_(32|64)[ 	]+foo3\(\)[ 	]+foo3 \+ 0
+
 Relocation section '.rela.plt' at .*
 [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_JUMP_SLOT[ 	]+foo1\(\)[ 	]+foo1 \+ 0
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd
index 32e66f0..3c0b06e 100644
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd
+++ b/ld/testsuite/ld-riscv-elf/ifunc-overwrite-pie.rd
@@ -2,6 +2,10 @@ Relocation section '.rela.got' at .*
 [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
 
+Relocation section '.rela.ifunc' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
+
 Relocation section '.rela.plt' at .*
 [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
 [0-9a-f]+[ 	]+[0-9a-f]+[ 	]+R_RISCV_IRELATIVE[ 	]+[0-9a-f]*
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d b/ld/testsuite/ld-riscv-elf/ifunc-overwrite.d
index 333dea3..333dea3 100644
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d
+++ b/ld/testsuite/ld-riscv-elf/ifunc-overwrite.d
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s b/ld/testsuite/ld-riscv-elf/ifunc-overwrite.s
index 6c2f8e8..fd83ae8 100644
--- a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s
+++ b/ld/testsuite/ld-riscv-elf/ifunc-overwrite.s
@@ -13,6 +13,10 @@ foo_resolver:
 	.type	foo2, %gnu_indirect_function
 	.set	foo2, foo_resolver
 
+	.globl	foo3
+	.type	foo3, %gnu_indirect_function
+	.set	foo3, foo_resolver
+
 	.globl	bar
 	.type	bar, @function
 bar:
@@ -36,3 +40,11 @@ bar:
 .endif
 	ret
 	.size	bar, .-bar
+
+	.data
+foo3_addr:
+.ifdef __64_bit__
+	.quad	foo3
+.else
+	.long	foo3
+.endif
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index a1dd0e5..669ac5d 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -277,12 +277,12 @@ if [istarget "riscv*-*-*"] {
     run_dump_test_ifunc "ifunc-plt-02" rv64 pie
     run_dump_test_ifunc "ifunc-plt-02" rv64 pic
     # Check the .rela.iplt overwrite issue.
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 exe
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pie
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pic
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 exe
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pie
-    run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pic
+    run_dump_test_ifunc "ifunc-overwrite" rv32 exe
+    run_dump_test_ifunc "ifunc-overwrite" rv32 pie
+    run_dump_test_ifunc "ifunc-overwrite" rv32 pic
+    run_dump_test_ifunc "ifunc-overwrite" rv64 exe
+    run_dump_test_ifunc "ifunc-overwrite" rv64 pie
+    run_dump_test_ifunc "ifunc-overwrite" rv64 pic
 
     # TODO: Make the following tests work under RV32.
     if [istarget "riscv32-*-*"] {