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authorJim Wilson <jimw@sifive.com>2019-09-20 15:01:20 -0700
committerJim Wilson <jimw@sifive.com>2019-09-20 15:01:20 -0700
commit9d1da81b261a20050ef2ad01a5b4c8cf78404222 (patch)
treebc9c73aaa8be63ebed399e1d3666a7fc84811883 /ld
parentabf516c6931af1683d1e51203de1ca01467f9f85 (diff)
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RISC-V: Optimize lui and auipc relaxations for undefweak symbol.
For the lui and auipc relaxations, since the symbol value of an undefined weak symbol is always be zero, we can optimize the patterns into a single LI/MV/ADDI instruction. bfd/ * elfnn-riscv.c (riscv_pcgp_hi_reloc): Add new field undefined_weak. (riscv_record_pcgp_hi_reloc): New parameter undefined_weak. Set undefined_weak field from it. (relax_func_t): New parameter undefined_weak. (_bfd_riscv_relax_call): New ignored parameter undefined_weak. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_delete): Likewise. (_bfd_riscv_relax_lui): New parameter undefined_weak. If true, allow relaxing. For LO12* relocs, set rs1 to x0 when undefined_weak. (_bfd_riscv_relax_pc): New parameter undefined_weak. For LO12* relocs, set undefined_weak from hi_reloc. If true, allow relaxing. For LO12* relocs, set rs1 to x0 when undefined_weak and change to non-pcrel reloc. (_bfd_riscv_relax_section): New local undefined_weak. Set for undef weak relocs that can be relaxed. Pass to relax_func call. ld/ * testsuite/ld-riscv-elf/weakref32.s: Add relaxable undef weak code. * testsuite/ld-riscv-elf/weakref64.s: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Updated. * testsuite/ld-riscv-elf/weakref64.d: Updated.
Diffstat (limited to 'ld')
-rw-r--r--ld/ChangeLog7
-rw-r--r--ld/testsuite/ld-riscv-elf/weakref32.d25
-rw-r--r--ld/testsuite/ld-riscv-elf/weakref32.s3
-rw-r--r--ld/testsuite/ld-riscv-elf/weakref64.d25
-rw-r--r--ld/testsuite/ld-riscv-elf/weakref64.s3
5 files changed, 39 insertions, 24 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 3f62dad..57d4df7 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,10 @@
+2019-09-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/ld-riscv-elf/weakref32.s: Add relaxable undef weak code.
+ * testsuite/ld-riscv-elf/weakref64.s: Likewise.
+ * testsuite/ld-riscv-elf/weakref32.d: Updated.
+ * testsuite/ld-riscv-elf/weakref64.d: Updated.
+
2019-09-20 Alan Modra <amodra@gmail.com>
* emultempl/xtensaelf.em (xtensa_get_section_deps): Comment.
diff --git a/ld/testsuite/ld-riscv-elf/weakref32.d b/ld/testsuite/ld-riscv-elf/weakref32.d
index 5ede7cb..eaeb6da 100644
--- a/ld/testsuite/ld-riscv-elf/weakref32.d
+++ b/ld/testsuite/ld-riscv-elf/weakref32.d
@@ -5,15 +5,16 @@
Disassembly of section \.text:
90000000 <_start>:
-90000000: 70000797 auipc a5,0x70000
-90000004: 00078793 mv a5,a5
-90000008: 02078263 beqz a5,9000002c <_start\+0x2c>
-9000000c: ff010113 addi sp,sp,-16
-90000010: 00112623 sw ra,12\(sp\)
-90000014: 00000097 auipc ra,0x0
-90000018: 000000e7 jalr zero # 0 <_start\-0x90000000>
-9000001c: 00c12083 lw ra,12\(sp\)
-90000020: 01010113 addi sp,sp,16
-90000024: 00000317 auipc t1,0x0
-90000028: 00000067 jr zero # 0 <_start\-0x90000000>
-9000002c: 00008067 ret
+90000000: 00000793 li a5,0
+90000004: 02078663 beqz a5,90000030 <_start\+0x30>
+90000008: 00000793 li a5,0
+9000000c: 02078263 beqz a5,90000030 <_start\+0x30>
+90000010: ff010113 addi sp,sp,-16
+90000014: 00112623 sw ra,12\(sp\)
+90000018: 00000097 auipc ra,0x0
+9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000>
+90000020: 00c12083 lw ra,12\(sp\)
+90000024: 01010113 addi sp,sp,16
+90000028: 00000317 auipc t1,0x0
+9000002c: 00000067 jr zero # 0 <_start\-0x90000000>
+90000030: 00008067 ret
diff --git a/ld/testsuite/ld-riscv-elf/weakref32.s b/ld/testsuite/ld-riscv-elf/weakref32.s
index 14df041..6c3d84d 100644
--- a/ld/testsuite/ld-riscv-elf/weakref32.s
+++ b/ld/testsuite/ld-riscv-elf/weakref32.s
@@ -4,6 +4,9 @@
.globl _start
.type _start, @function
_start:
+ lui a5,%hi(f)
+ addi a5,a5,%lo(f)
+ beq a5,zero,.L1
lla a5,f
beqz a5,.L1
addi sp,sp,-16
diff --git a/ld/testsuite/ld-riscv-elf/weakref64.d b/ld/testsuite/ld-riscv-elf/weakref64.d
index 52db9c2..cc718a9 100644
--- a/ld/testsuite/ld-riscv-elf/weakref64.d
+++ b/ld/testsuite/ld-riscv-elf/weakref64.d
@@ -5,15 +5,16 @@
Disassembly of section \.text:
0000000090000000 <_start>:
- 90000000: 000007b7 lui a5,0x0
- 90000004: 00078793 mv a5,a5
- 90000008: 02078263 beqz a5,9000002c <_start\+0x2c>
- 9000000c: ff010113 addi sp,sp,-16
- 90000010: 00113423 sd ra,8\(sp\)
- 90000014: 00000097 auipc ra,0x0
- 90000018: 000000e7 jalr zero # 0 <_start\-0x90000000>
- 9000001c: 00813083 ld ra,8\(sp\)
- 90000020: 01010113 addi sp,sp,16
- 90000024: 00000317 auipc t1,0x0
- 90000028: 00000067 jr zero # 0 <_start\-0x90000000>
- 9000002c: 00008067 ret
+ 90000000: 00000793 li a5,0
+ 90000004: 02078663 beqz a5,90000030 <_start\+0x30>
+ 90000008: 00000793 li a5,0
+ 9000000c: 02078263 beqz a5,90000030 <_start\+0x30>
+ 90000010: ff010113 addi sp,sp,-16
+ 90000014: 00113423 sd ra,8\(sp\)
+ 90000018: 00000097 auipc ra,0x0
+ 9000001c: 000000e7 jalr zero # 0 <_start\-0x90000000>
+ 90000020: 00813083 ld ra,8\(sp\)
+ 90000024: 01010113 addi sp,sp,16
+ 90000028: 00000317 auipc t1,0x0
+ 9000002c: 00000067 jr zero # 0 <_start\-0x90000000>
+ 90000030: 00008067 ret
diff --git a/ld/testsuite/ld-riscv-elf/weakref64.s b/ld/testsuite/ld-riscv-elf/weakref64.s
index 5872626..83bcd28 100644
--- a/ld/testsuite/ld-riscv-elf/weakref64.s
+++ b/ld/testsuite/ld-riscv-elf/weakref64.s
@@ -4,6 +4,9 @@
.globl _start
.type _start, @function
_start:
+ lui a5,%hi(f)
+ addi a5,a5,%lo(f)
+ beq a5,zero,.L1
lla a5,f
beqz a5,.L1
addi sp,sp,-16