RISC-V: PR28789, Reject R_RISCV_PCREL relocations with ABS symbol in PIC/PIE.

The non-preemptible SHN_ABS symbol with a pc-relative relocation should be
disallowed when generating shared object (pic and pie).  Generally, the
following cases, which refer to pr25749, will cause a symbol be
non-preemptible,

* -pie, or -shared with -symbolic
* STV_HIDDEN, STV_INTERNAL, STV_PROTECTED
* Have dynamic symbol table, but without the symbol
* VER_NDX_LOCAL

However, PCREL_HI20/LO12 relocs are always bind locally when generating
shared object, so not only the non-preemptible absolute symbol need to
be disallowed, all absolute symbol references need but except that they
are defined in linker script.  If we also disallow the absolute symbol
in linker script, then the glibc-linux toolchain build failed, so regard
them as pc-relative symbols, just like what x86 did.

Maybe we should add this check for all pc-relative relocations, rather
than just handle in R_RISCV_PCREL relocs.  Ideally, since the value of
SHN_ABS symbol is a constant, only S - A relocations should be allowed
in the shared object, so only BFD_RELOC_8/16/32/64 are allowed, which
means R_RISCV_32/R_RISCV_64.

bfd/
    PR 28789
    * elfnn-riscv.c (riscv_elf_check_relocs): The absolute symbol cannot be
    referneced with pc-relative relocation when generating shared object.
ld/
    PR 28789
    * ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
    * ld/testsuite/ld-riscv-elf/pcrel-reloc*: New testcases.

8 files changed, 70 insertions, 0 deletions

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 1b2a5ce..43572c5 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -308,4 +308,11 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "ifunc-seperate-plt-pic"
     run_dump_test "ifunc-seperate-pcrel-pie"
     run_dump_test "ifunc-seperate-pcrel-pic"
+
+    # Tests related to mixing medany code into position-independent targets,
+    # where it's not always possible to generate correct addressing sequences.
+    run_dump_test "pcrel-reloc-rel-nopie"
+    run_dump_test "pcrel-reloc-rel-pie"
+    run_dump_test "pcrel-reloc-abs-nopie"
+    run_dump_test "pcrel-reloc-abs-pie"
 }
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-nopie.d b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-nopie.d
new file mode 100644
index 0000000..5402638
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-nopie.d
@@ -0,0 +1,14 @@
+#source: pcrel-reloc.s
+#source: pcrel-reloc-abs.s
+#as: -march=rv64i -mabi=lp64
+#ld: -melf64lriscv --no-pie --no-relax
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <_start>:
+.*auipc.*
+.*lw.*# [0-9a-f]* <sym>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-pie.d b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-pie.d
new file mode 100644
index 0000000..7f5eaa3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs-pie.d
@@ -0,0 +1,5 @@
+#source: pcrel-reloc.s
+#source: pcrel-reloc-abs.s
+#as: -march=rv64i -mabi=lp64
+#ld: -melf64lriscv --pie --no-relax
+#error: .*relocation R_RISCV_PCREL_HI20 against absolute symbol `sym' can not be used when making a shared objec.*t
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs.s b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs.s
new file mode 100644
index 0000000..1df32a1
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-abs.s
@@ -0,0 +1,2 @@
+.global sym
+.set sym,0x8000
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-nopie.d b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-nopie.d
new file mode 100644
index 0000000..ab2a377
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-nopie.d
@@ -0,0 +1,14 @@
+#source: pcrel-reloc.s
+#source: pcrel-reloc-rel.s
+#as: -march=rv64i -mabi=lp64
+#ld: -melf64lriscv --no-pie --no-relax
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <_start>:
+.*auipc.*
+.*lw.*# [0-9a-f]* <sym>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-pie.d b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-pie.d
new file mode 100644
index 0000000..aec612d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel-pie.d
@@ -0,0 +1,14 @@
+#source: pcrel-reloc.s
+#source: pcrel-reloc-rel.s
+#as: -march=rv64i -mabi=lp64
+#ld: -melf64lriscv --pie --no-relax
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <_start>:
+.*auipc.*
+.*lw.*# [0-9a-f]* <sym>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel.s b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel.s
new file mode 100644
index 0000000..fb0e6c0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc-rel.s
@@ -0,0 +1,9 @@
+.data
+# Makes sure "sym" doesn't end up at the beginning of ".data", as that makes it
+# tough to then later detect it from scripts.
+.global buf
+buf:
+    .fill 8192, 4, 1
+.global sym
+sym:
+    .fill 8192, 4, 2
diff --git a/ld/testsuite/ld-riscv-elf/pcrel-reloc.s b/ld/testsuite/ld-riscv-elf/pcrel-reloc.s
new file mode 100644
index 0000000..db2103b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/pcrel-reloc.s
@@ -0,0 +1,5 @@
+.text
+.global _start
+_start:
+    auipc t0, %pcrel_hi(sym)
+    lw t0, %pcrel_lo(_start)(t0)