LoongArch ld support

2021-10-22  Chenghua Xu  <xuchenghua@loongson.cn>
	    Zhensong Liu  <liuzhensong@loongson.cn>
	    Weinan Liu  <liuweinan@loongson.cn>
	    Xiaolin Tang  <tangxiaolin@loongson.cn>

ld/
	* Makefile.am: Add LoongArch.
	* NEWS: Mention LoongArch support.
	* configure.tgt: Add LoongArch.
	* emulparams/elf32loongarch-defs.sh: New.
	* emulparams/elf32loongarch.sh: Likewise.
	* emulparams/elf64loongarch-defs.sh: Likewise.
	* emulparams/elf64loongarch.sh: Likewise.
	* emultempl/loongarchelf.em: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
ld/testsuite/
	* ld-loongarch-elf/disas-jirl.d: New.
	* ld-loongarch-elf/disas-jirl.s: Likewise.
	* ld-loongarch-elf/jmp_op.d: Likewise.
	* ld-loongarch-elf/jmp_op.s: Likewise.
	* ld-loongarch-elf/ld-loongarch-elf.exp: Likewise.
	* ld-loongarch-elf/macro_op.d: Likewise.
	* ld-loongarch-elf/macro_op.s: Likewise.
	* ld-loongarch-elf/syscall-0.s: Likewise.
	* ld-loongarch-elf/syscall-1.s: Likewise.
	* ld-loongarch-elf/syscall.d: Likewise.
	* ld-srec/srec.exp: Add LoongArch.
	* ld-unique/pr21529.d: Likewise.

22 files changed, 1146 insertions, 1 deletions

diff --git a/ld/Makefile.am b/ld/Makefile.am
index 82d0af9..b41bba4 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -408,6 +408,7 @@ ALL_64_EMULATION_SOURCES = \
 	eelf32elmip.c \
 	eelf32elmipvxworks.c \
 	eelf32l4300.c \
+	eelf32loongarch.c \
 	eelf32lmip.c \
 	eelf32lr5900.c \
 	eelf32lr5900n32.c \
@@ -441,6 +442,7 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64hppa.c \
 	eelf64lppc.c \
 	eelf64lppc_fbsd.c \
+	eelf64loongarch.c \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64.c \
 	eelf64lriscv_lp64f.c \
@@ -901,6 +903,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmipvxworks.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32l4300.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32loongarch.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lr5900n32.Pc@am__quote@
@@ -934,6 +937,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
diff --git a/ld/Makefile.in b/ld/Makefile.in
index dbdbe0f..6a194ae 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -898,6 +898,7 @@ ALL_64_EMULATION_SOURCES = \
 	eelf32elmipvxworks.c \
 	eelf32l4300.c \
 	eelf32lmip.c \
+	eelf32loongarch.c \
 	eelf32lr5900.c \
 	eelf32lr5900n32.c \
 	eelf32lriscv.c \
@@ -930,6 +931,7 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64hppa.c \
 	eelf64lppc.c \
 	eelf64lppc_fbsd.c \
+	eelf64loongarch.c \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64.c \
 	eelf64lriscv_lp64f.c \
@@ -1355,6 +1357,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32iq10.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32iq2000.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32l4300.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32loongarch.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lm32.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lm32fd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lmip.Po@am__quote@
@@ -1426,6 +1429,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Po@am__quote@
@@ -2598,6 +2602,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lppc_fbsd.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64loongarch.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
diff --git a/ld/NEWS b/ld/NEWS
index 6e0b566..33dc02d 100644
--- a/ld/NEWS
+++ b/ld/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the LoongArch architecture.
+
 * Add -z indirect-extern-access/-z noindirect-extern-access to x86 ELF
   linker to control canonical function pointers and copy relocation.
 
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 5411104..9a491eb 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -1036,6 +1036,10 @@ z8k-*-coff)		targ_emul=z8002
 			targ_extra_emuls=z8001
 			targ_extra_ofiles=
 			;;
+loongarch32-*)		targ_emul=elf32loongarch
+			;;
+loongarch64-*)		targ_emul=elf64loongarch
+			;;
 *-*-ieee*)		targ_emul=vanilla
 			targ_extra_ofiles=
 			;;
diff --git a/ld/emulparams/elf32loongarch-defs.sh b/ld/emulparams/elf32loongarch-defs.sh
new file mode 100644
index 0000000..f80f574
--- /dev/null
+++ b/ld/emulparams/elf32loongarch-defs.sh
@@ -0,0 +1,36 @@
+# This is an ELF platform.
+SCRIPT_NAME=elf
+ARCH=loongarch
+NO_REL_RELOCS=yes
+
+TEMPLATE_NAME=elf
+EXTRA_EM_FILE=loongarchelf
+
+ELFSIZE=32
+
+if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then
+  case " $EMULATION_LIBPATH " in
+    *" ${EMULATION_NAME} "*)
+      NATIVE=yes
+      ;;
+  esac
+fi
+
+# Enable shared library support for everything except an embedded elf target.
+case "$target" in
+  loongarch*-elf)
+    ;;
+  *)
+    GENERATE_SHLIB_SCRIPT=yes
+    GENERATE_PIE_SCRIPT=yes
+    ;;
+esac
+
+IREL_IN_PLT=
+TEXT_START_ADDR=0x10000
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+
+SEPARATE_GOTPLT=0
+INITIAL_READONLY_SECTIONS=".interp         : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
+INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
diff --git a/ld/emulparams/elf32loongarch.sh b/ld/emulparams/elf32loongarch.sh
new file mode 100644
index 0000000..edc85ec
--- /dev/null
+++ b/ld/emulparams/elf32loongarch.sh
@@ -0,0 +1,11 @@
+source_sh ${srcdir}/emulparams/elf32loongarch-defs.sh
+OUTPUT_FORMAT="elf32-loongarch"
+
+case "$target" in
+  loongarch32*-linux*)
+    case "$EMULATION_NAME" in
+      *32*)
+	LIBPATH_SUFFIX="32" ;;
+    esac
+    ;;
+esac
diff --git a/ld/emulparams/elf64loongarch-defs.sh b/ld/emulparams/elf64loongarch-defs.sh
new file mode 100644
index 0000000..c793f5d
--- /dev/null
+++ b/ld/emulparams/elf64loongarch-defs.sh
@@ -0,0 +1,39 @@
+# This is an ELF platform.
+SCRIPT_NAME=elf
+ARCH=loongarch
+NO_REL_RELOCS=yes
+
+TEMPLATE_NAME=elf
+EXTRA_EM_FILE=loongarchelf
+
+ELFSIZE=64
+
+if test `echo "$host" | sed -e s/64//` = `echo "$target" | sed -e s/64//`; then
+  case " $EMULATION_LIBPATH " in
+    *" ${EMULATION_NAME} "*)
+      NATIVE=yes
+      ;;
+  esac
+fi
+
+# Enable shared library support for everything except an embedded elf target.
+case "$target" in
+  loongarch*-elf)
+    ;;
+  *)
+    GENERATE_SHLIB_SCRIPT=yes
+    GENERATE_PIE_SCRIPT=yes
+    ;;
+esac
+
+# In all cases, the number is big-endian.
+# LoongArch nop is 'andi $r0,$r0,0'.
+NOP=0x00004003
+
+TEXT_START_ADDR=0x120000000
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+
+SEPARATE_GOTPLT=0
+INITIAL_READONLY_SECTIONS=".interp         : { *(.interp) } ${CREATE_PIE-${INITIAL_READONLY_SECTIONS}}"
+INITIAL_READONLY_SECTIONS="${RELOCATING+${CREATE_SHLIB-${INITIAL_READONLY_SECTIONS}}}"
diff --git a/ld/emulparams/elf64loongarch.sh b/ld/emulparams/elf64loongarch.sh
new file mode 100644
index 0000000..d7b2229
--- /dev/null
+++ b/ld/emulparams/elf64loongarch.sh
@@ -0,0 +1,11 @@
+source_sh ${srcdir}/emulparams/elf64loongarch-defs.sh
+OUTPUT_FORMAT="elf64-loongarch"
+
+case "$target" in
+  loongarch64*-linux*)
+    case "$EMULATION_NAME" in
+      *64*)
+	LIBPATH_SUFFIX="64";;
+    esac
+    ;;
+esac
diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
new file mode 100644
index 0000000..b688ef7
--- /dev/null
+++ b/ld/emultempl/loongarchelf.em
@@ -0,0 +1,87 @@
+# This shell script emits a C file. -*- C -*-
+#   Copyright (C) 2021 Free Software Foundation, Inc.
+#   Contributed by Loongson Ltd.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; see the file COPYING3. If not,
+# see <http://www.gnu.org/licenses/>.
+
+fragment <<EOF
+
+#include "ldmain.h"
+#include "ldctor.h"
+#include "elf/loongarch.h"
+
+static void
+larch_elf_before_allocation (void)
+{
+  gld${EMULATION_NAME}_before_allocation ();
+
+  if (link_info.discard == discard_sec_merge)
+    link_info.discard = discard_l;
+
+  if (!bfd_link_relocatable (&link_info))
+    {
+      /* We always need at least some relaxation to handle code alignment.  */
+      if (RELAXATION_DISABLED_BY_USER)
+	TARGET_ENABLE_RELAXATION;
+      else
+	ENABLE_RELAXATION;
+    }
+
+  link_info.relax_pass = 3;
+}
+
+static void
+gld${EMULATION_NAME}_after_allocation (void)
+{
+  int need_layout = 0;
+
+  /* Don't attempt to discard unused .eh_frame sections until the final link,
+     as we can't reliably tell if they're used until after relaxation.  */
+  if (!bfd_link_relocatable (&link_info))
+    {
+      need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+      if (need_layout < 0)
+	{
+	  einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
+	  return;
+	}
+    }
+
+  /* gld${EMULATION_NAME}_map_segments (need_layout); */
+  ldelf_map_segments (need_layout);
+}
+
+/* This is a convenient point to tell BFD about target specific flags.
+   After the output has been created, but before inputs are read.  */
+
+static void
+larch_create_output_section_statements (void)
+{
+  /* See PR 22920 for an example of why this is necessary.  */
+  if (strstr (bfd_get_target (link_info.output_bfd), "loong") == NULL)
+    {
+      einfo (_("%F%P: error: cannot change output format"
+	       " whilst linking %s binaries\n"), "LoongArch");
+      return;
+    }
+}
+
+EOF
+
+LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation
+LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=larch_create_output_section_statements
diff --git a/ld/po/BLD-POTFILES.in b/ld/po/BLD-POTFILES.in
index 54975cd..9f9500d 100644
--- a/ld/po/BLD-POTFILES.in
+++ b/ld/po/BLD-POTFILES.in
@@ -116,6 +116,7 @@ eelf32l4300.c
 eelf32lm32.c
 eelf32lm32fd.c
 eelf32lmip.c
+eelf32loongarch.c
 eelf32lppc.c
 eelf32lppclinux.c
 eelf32lppcnto.c
@@ -184,6 +185,7 @@ eelf64briscv_lp64f.c
 eelf64btsmip.c
 eelf64btsmip_fbsd.c
 eelf64hppa.c
+eelf64loongarch.c
 eelf64lppc.c
 eelf64lppc_fbsd.c
 eelf64lriscv.c
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.d b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
new file mode 100644
index 0000000..8c60f63
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.d
@@ -0,0 +1,14 @@
+#name: jirl zero-offset symbols
+#source: disas-jirl.s
+#ld: --no-relax
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0000000120000078 <_start>:
+[ 	]+120000078:[ 	]+1c000014 [ 	]+pcaddu12i[ 	]+[ 	]+\$t8, 0
+[ 	]+12000007c:[ 	]+02c00294 [ 	]+addi.d[ 	]+[ 	]+\$t8, \$t8, 0
+[ 	]+120000080:[ 	]+4c000281 [ 	]+jirl[ 	]+[ 	]+\$ra, \$t8, 0
diff --git a/ld/testsuite/ld-loongarch-elf/disas-jirl.s b/ld/testsuite/ld-loongarch-elf/disas-jirl.s
new file mode 100644
index 0000000..d6027c9
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/disas-jirl.s
@@ -0,0 +1,5 @@
+	.text
+	.globl _start
+_start:
+	la.local $r20,_start
+	jirl $r1, $r20, 0
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
new file mode 100644
index 0000000..e6c50e8
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -0,0 +1,68 @@
+#as:
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+[ 	]+0:[ 	]+03400000 [ 	]+andi[ 	]+[ 	]+\$zero, \$zero, 0x0
+[ 	]+4:[ 	]+60000004 [ 	]+bgtz[ 	]+[ 	]+\$a0, 0[ 	]+# 0x4
+[ 	]+[ 	]+[ 	]+4: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+4: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+8:[ 	]+64000080 [ 	]+bgez[ 	]+[ 	]+\$a0, 0[ 	]+# 0x8
+[ 	]+[ 	]+[ 	]+8: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+8: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+c:[ 	]+64000004 [ 	]+blez[ 	]+[ 	]+\$a0, 0[ 	]+# 0xc
+[ 	]+[ 	]+[ 	]+c: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+c: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+10:[ 	]+40000080 [ 	]+beqz[ 	]+[ 	]+\$a0, 0[ 	]+# 0x10
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ 	]+\*ABS\*
+[ 	]+14:[ 	]+44000080 [ 	]+bnez[ 	]+[ 	]+\$a0, 0[ 	]+# 0x14
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ 	]+\*ABS\*
+[ 	]+18:[ 	]+48000000 [ 	]+bceqz[ 	]+[ 	]+\$fcc0, 0[ 	]+# 0x18
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ 	]+\*ABS\*
+[ 	]+1c:[ 	]+48000100 [ 	]+bcnez[ 	]+[ 	]+\$fcc0, 0[ 	]+# 0x1c
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_POP_32_S_0_5_10_16_S2[ 	]+\*ABS\*
+[ 	]+20:[ 	]+4c000080 [ 	]+jirl[ 	]+[ 	]+\$zero, \$a0, 0
+[ 	]+24:[ 	]+50000000 [ 	]+b[ 	]+[ 	]+0[ 	]+# 0x24
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_POP_32_S_0_10_10_16_S2[ 	]+\*ABS\*
+[ 	]+28:[ 	]+54000000 [ 	]+bl[ 	]+[ 	]+0[ 	]+# 0x28
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_POP_32_S_0_10_10_16_S2[ 	]+\*ABS\*
+[ 	]+2c:[ 	]+58000085 [ 	]+beq[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x2c
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+30:[ 	]+5c000085 [ 	]+bne[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x30
+[ 	]+[ 	]+[ 	]+30: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+30: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+34:[ 	]+60000085 [ 	]+blt[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x34
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+38:[ 	]+600000a4 [ 	]+blt[ 	]+[ 	]+\$a1, \$a0, 0[ 	]+# 0x38
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+3c:[ 	]+64000085 [ 	]+bge[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x3c
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+40:[ 	]+640000a4 [ 	]+bge[ 	]+[ 	]+\$a1, \$a0, 0[ 	]+# 0x40
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+44:[ 	]+68000085 [ 	]+bltu[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x44
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+48:[ 	]+680000a4 [ 	]+bltu[ 	]+[ 	]+\$a1, \$a0, 0[ 	]+# 0x48
+[ 	]+[ 	]+[ 	]+48: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+48: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+4c:[ 	]+6c000085 [ 	]+bgeu[ 	]+[ 	]+\$a0, \$a1, 0[ 	]+# 0x4c
+[ 	]+[ 	]+[ 	]+4c: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+4c: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
+[ 	]+50:[ 	]+6c0000a4 [ 	]+bgeu[ 	]+[ 	]+\$a1, \$a0, 0[ 	]+# 0x50
+[ 	]+[ 	]+[ 	]+50: R_LARCH_SOP_PUSH_PCREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+50: R_LARCH_SOP_POP_32_S_10_16_S2[ 	]+\*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loongarch-elf/jmp_op.s
new file mode 100644
index 0000000..01b043d
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.s
@@ -0,0 +1,22 @@
+.L1:
+	nop
+	bgtz  $r4,L1
+	bgez  $r4,L1
+	blez  $r4,L1
+	beqz  $r4,L1
+	bnez  $r4,L1
+	bceqz  $fcc0,L1
+	bcnez  $fcc0,L1
+	jr  $r4
+	b  L1
+	bl  L1
+	beq  $r4,$r5,L1
+	bne  $r4,$r5,L1
+	blt  $r4,$r5,L1
+	bgt  $r4,$r5,L1
+	bge  $r4,$r5,L1
+	ble  $r4,$r5,L1
+	bltu  $r4,$r5,L1
+	bgtu  $r4,$r5,L1
+	bgeu  $r4,$r5,L1
+	bleu  $r4,$r5,L1
diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
new file mode 100644
index 0000000..0d31c2a
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp
@@ -0,0 +1,34 @@
+# Expect script for LoongArch ELF linker tests
+#   Copyright (C) 2021 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+proc loongarch_choose_lp64_emul {} {
+    if { [istarget "loongarch64be-*"] } {
+	return "elf64bloongarch"
+    }
+    return "elf64lloongarch"
+}
+
+if [istarget "loongarch*-*-*"] {
+    run_dump_test "jmp_op"
+    run_dump_test "macro_op"
+    run_dump_test "syscall"
+    run_dump_test "disas-jirl"
+}
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
new file mode 100644
index 0000000..548553e
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -0,0 +1,732 @@
+#as:
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+[ 	]+0:[ 	]+00150004 [ 	]+move[ 	]+[ 	]+\$a0, \$zero
+[ 	]+4:[ 	]+02bffc04 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$zero, -1\(0xfff\)
+[ 	]+8:[ 	]+00150004 [ 	]+move[ 	]+[ 	]+\$a0, \$zero
+[ 	]+c:[ 	]+02bffc04 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$zero, -1\(0xfff\)
+[ 	]+10:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+10: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+14:[ 	]+28c00084 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a0, 0
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+18:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+18: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+1c:[ 	]+28c00084 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a0, 0
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+1c: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+20:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000000
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+20: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+24:[ 	]+03800005 [ 	]+ori[ 	]+[ 	]+\$a1, \$zero, 0x0
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000004
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xfff
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_AND[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+24: R_LARCH_SOP_POP_32_U_10_12[ 	]+\*ABS\*
+[ 	]+28:[ 	]+16000005 [ 	]+lu32i.d[ 	]+[ 	]+\$a1, 0
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000008
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+28: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+2c:[ 	]+030000a5 [ 	]+lu52i.d[ 	]+[ 	]+\$a1, \$a1, 0
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x34
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+2c: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+30:[ 	]+380c1484 [ 	]+ldx.d[ 	]+[ 	]+\$a0, \$a0, \$a1
+[ 	]+34:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+34: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+38:[ 	]+28c00084 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a0, 0
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+38: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+3c:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000000
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+3c: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+40:[ 	]+03800005 [ 	]+ori[ 	]+[ 	]+\$a1, \$zero, 0x0
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000004
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xfff
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_AND[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+40: R_LARCH_SOP_POP_32_U_10_12[ 	]+\*ABS\*
+[ 	]+44:[ 	]+16000005 [ 	]+lu32i.d[ 	]+[ 	]+\$a1, 0
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000008
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_PUSH_GPREL[ 	]+L1
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+44: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
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+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_PUSH_TLS_GOT[ 	]+L1
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xfff
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_AND[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+110: R_LARCH_SOP_POP_32_U_10_12[ 	]+\*ABS\*
+[ 	]+114:[ 	]+16000005 [ 	]+lu32i.d[ 	]+[ 	]+\$a1, 0
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000008
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_PUSH_TLS_GOT[ 	]+L1
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+114: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+118:[ 	]+030000a5 [ 	]+lu52i.d[ 	]+[ 	]+\$a1, \$a1, 0
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_PUSH_TLS_GOT[ 	]+L1
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x34
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+118: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+11c:[ 	]+380c1484 [ 	]+ldx.d[ 	]+[ 	]+\$a0, \$a0, \$a1
+[ 	]+120:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+120: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+124:[ 	]+02c00084 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a0, 0
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+124: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+128:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000000
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+128: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+12c:[ 	]+03800005 [ 	]+ori[ 	]+[ 	]+\$a1, \$zero, 0x0
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000004
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xfff
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_AND[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+12c: R_LARCH_SOP_POP_32_U_10_12[ 	]+\*ABS\*
+[ 	]+130:[ 	]+16000005 [ 	]+lu32i.d[ 	]+[ 	]+\$a1, 0
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000008
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+130: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+134:[ 	]+030000a5 [ 	]+lu52i.d[ 	]+[ 	]+\$a1, \$a1, 0
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x34
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+134: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+138:[ 	]+00109484 [ 	]+add.d[ 	]+[ 	]+\$a0, \$a0, \$a1
+[ 	]+13c:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x800
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+13c: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+140:[ 	]+02c00084 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a0, 0
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x804
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+140: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+144:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000000
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+144: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+148:[ 	]+03800005 [ 	]+ori[ 	]+[ 	]+\$a1, \$zero, 0x0
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x4
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000004
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x20
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_SUB[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xfff
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_AND[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+148: R_LARCH_SOP_POP_32_U_10_12[ 	]+\*ABS\*
+[ 	]+14c:[ 	]+16000005 [ 	]+lu32i.d[ 	]+[ 	]+\$a1, 0
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x80000008
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0xc
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_SL[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x2c
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+14c: R_LARCH_SOP_POP_32_S_5_20[ 	]+\*ABS\*
+[ 	]+150:[ 	]+030000a5 [ 	]+lu52i.d[ 	]+[ 	]+\$a1, \$a1, 0
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_PUSH_PCREL[ 	]+_GLOBAL_OFFSET_TABLE_\+0x8000000c
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_PUSH_TLS_GD[ 	]+L1
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_ADD[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_PUSH_ABSOLUTE[ 	]+\*ABS\*\+0x34
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_SR[ 	]+\*ABS\*
+[ 	]+[ 	]+[ 	]+150: R_LARCH_SOP_POP_32_S_10_12[ 	]+\*ABS\*
+[ 	]+154:[ 	]+00109484 [ 	]+add.d[ 	]+[ 	]+\$a0, \$a0, \$a1
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.s b/ld/testsuite/ld-loongarch-elf/macro_op.s
new file mode 100644
index 0000000..c15e364
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.s
@@ -0,0 +1,29 @@
+.L1:
+	li.w  $r4,0
+	li.w  $r4,0xffffffff
+	li.d  $r4,0
+	li.d  $r4,0xffffffffffffffff
+	la  $r4,L1
+	la.global  $r4,L1
+	la.global  $r4,$r5,L1
+	la.global  $r4,L1
+	la.global  $r4,$r5,L1
+	la.global  $r4,L1
+	la.global  $r4,$r5,L1
+	la.local  $r4,L1
+	la.local  $r4,$r5,L1
+	la.local  $r4,L1
+	la.local  $r4,$r5,L1
+	la.abs  $r4,L1
+	la.pcrel  $r4,L1
+	la.pcrel  $r4,L1
+	la.pcrel  $r4,$r5,L1
+	la.got  $r4,L1
+	la.got  $r4,$r5,L1
+	la.tls.le  $r4,L1
+	la.tls.ie  $r4,L1
+	la.tls.ie  $r4,$r5,L1
+	la.tls.ld  $r4,L1
+	la.tls.ld  $r4,$r5,L1
+	la.tls.gd  $r4,L1
+	la.tls.gd  $r4,$r5,L1
diff --git a/ld/testsuite/ld-loongarch-elf/syscall-0.s b/ld/testsuite/ld-loongarch-elf/syscall-0.s
new file mode 100644
index 0000000..f31e05f
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/syscall-0.s
@@ -0,0 +1,9 @@
+.globl _start
+
+.section .text.hot
+_start:
+	la.global $r20,cc
+	jirl $r1, $r20, 0
+	addi.w  $r11,$r0,93
+	addi.w  $r4,$r0,0
+	syscall 0
diff --git a/ld/testsuite/ld-loongarch-elf/syscall-1.s b/ld/testsuite/ld-loongarch-elf/syscall-1.s
new file mode 100644
index 0000000..e9acee9
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/syscall-1.s
@@ -0,0 +1,20 @@
+.globl cc
+
+.text
+cc:
+	addi.d	$r3,$r3,-16
+	st.d	$r1,$r3,8
+	la.local $r5,.LC0
+	addi.w $r4,$r0,0
+	addi.w $r6, $r0,12
+	addi.w $r11, $r0, 64
+	syscall 0
+	ld.d	$r1,$r3,8
+	addi.d	$r3,$r3,16
+	jirl $r0, $r1, 0
+.LC0:
+	.ascii	"hello world\012\000"
+	.text
+	.align	2
+	.globl	world
+	.type	world, @function
diff --git a/ld/testsuite/ld-loongarch-elf/syscall.d b/ld/testsuite/ld-loongarch-elf/syscall.d
new file mode 100644
index 0000000..b599277
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/syscall.d
@@ -0,0 +1,5 @@
+#name: syscall
+#source: syscall-0.s
+#source: syscall-1.s
+#objdump: -d
+#pass
diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp
index 57380ca..30a5a3d 100644
--- a/ld/testsuite/ld-srec/srec.exp
+++ b/ld/testsuite/ld-srec/srec.exp
@@ -291,6 +291,12 @@ proc run_srec_test { test objs } {
 	setup_xfail "riscv*-*-*"
     }
 
+    # LoongArch targets cannot convert format in the linker
+    # using the --oformat command line switch
+    if [istarget loongarch*-*-*] {
+	setup_xfail "loongarch*-*-*"
+    }
+
     # V850 targets need libgcc.a
     if [istarget v850*-*-elf] {
 	set objs "$objs -L ../gcc -lgcc"
diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d
index fb63794..896f872 100644
--- a/ld/testsuite/ld-unique/pr21529.d
+++ b/ld/testsuite/ld-unique/pr21529.d
@@ -1,6 +1,6 @@
 #ld: --oformat binary -T pr21529.ld -e main
 #objdump: -s -b binary
-#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-*
+#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* loongarch*-*-*
 # Skip targets which can't change output format to binary.
 
 #pass