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author | Alan Modra <amodra@gmail.com> | 2019-04-05 09:20:16 +1030 |
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committer | Alan Modra <amodra@gmail.com> | 2019-04-05 12:20:49 +1030 |
commit | c2b1c2754526acff8aae2fe8f5a56c2dd11d0b7f (patch) | |
tree | 86c506f4975df44a54e4ab0398dc9118eef9100f /ld/testsuite/ld-powerpc/tlsopt5.d | |
parent | 82477cd28aac011c884d75a429d47a0523cbac26 (diff) | |
download | gdb-c2b1c2754526acff8aae2fe8f5a56c2dd11d0b7f.zip gdb-c2b1c2754526acff8aae2fe8f5a56c2dd11d0b7f.tar.gz gdb-c2b1c2754526acff8aae2fe8f5a56c2dd11d0b7f.tar.bz2 |
PowerPC disassembler: Don't emit trailing spaces
When an instruction has operands, the PowerPC disassembler prints
spaces after the opcode so as to line up operands. If the operands
are all optional and all default value, then no operands are printed,
leaving trailing spaces. This patch fixes that.
opcodes/
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
opcode until first operand is output.
gas/
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
ld/
* testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
* testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
Diffstat (limited to 'ld/testsuite/ld-powerpc/tlsopt5.d')
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsopt5.d | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d index 4caf183..a285027 100644 --- a/ld/testsuite/ld-powerpc/tlsopt5.d +++ b/ld/testsuite/ld-powerpc/tlsopt5.d @@ -21,7 +21,7 @@ Disassembly of section \.text: .*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3 .*: (00 00 2b 2c|2c 2b 00 00) cmpdi r11,0 .*: (14 6a 6c 7c|7c 6c 6a 14) add r3,r12,r13 -.*: (20 00 82 4d|4d 82 00 20) beqlr +.*: (20 00 82 4d|4d 82 00 20) beqlr .*: (78 03 03 7c|7c 03 03 78) mr r3,r0 .*: (a6 02 68 7d|7d 68 02 a6) mflr r11 .*: (08 00 61 f9|f9 61 00 08) std r11,8\(r1\) |