PowerPC64 __tls_get_addr_desc

This implements register saving and restoring in the __tls_get_addr
call stub, so that when glibc supports the optimized tls call stub gcc
can generate code that assumes only r0, r12 and of course r3 are
changed on a __tls_get_addr call.  When gcc expects __tls_get_addr
calls to preserve registers the call will be to __tls_get_addr_desc,
which will be translated by the linker to a call to __tls_get_addr_opt.

bfd/
	* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
	* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
	tga_desc_fd.
	(is_tls_get_addr): Match tga_desc and tga_desc_df too.
	(STDU_R1_0R1, ADDI_R1_R1): Define.
	(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
	(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd.  Indirect
	tga_desc_fd to opt_fd, and tga_desc to opt.  Set
	no_tls_get_addr_regsave.
	(branch_reloc_hash_match): Add hash3 and hash4.
	(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
	(ppc64_elf_size_dynamic_sections): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	(plt_stub_size, build_plt_stub): Likewise.  Size regsave
	__tls_get_addr stub.
	(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
	eh_frame.
	(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too.  Size
	eh_frame for regsave __tls_get_addr.
gas/
	* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
	__tls_get_addr_desc and __tls_get_addr_opt.
ld/
	* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
	(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
	--tls-get-addr-regsave and --no-tls-get-addr-regsave.
	(params): Init new field.
	* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
	Document.
	* testsuite/ld-powerpc/tlsdesc.s,
	* testsuite/ld-powerpc/tlsdesc.d,
	* testsuite/ld-powerpc/tlsdesc.wf,
	* testsuite/ld-powerpc/tlsdesc2.d,
	* testsuite/ld-powerpc/tlsdesc2.wf,
	* testsuite/ld-powerpc/tlsexenors.d,
	* testsuite/ld-powerpc/tlsexenors.r,
	* testsuite/ld-powerpc/tlsexers.d,
	* testsuite/ld-powerpc/tlsexers.r,
	* testsuite/ld-powerpc/tlsexetocnors.d,
	* testsuite/ld-powerpc/tlsexetocrs.d,
	* testsuite/ld-powerpc/tlsexetocrs.r,
	* testsuite/ld-powerpc/tlsopt6.d,
	* testsuite/ld-powerpc/tlsopt6.wf: New.
	* testsuite/ld-powerpc/powerpc.exp: Run new tests.

1 files changed, 106 insertions, 0 deletions

diff --git a/ld/testsuite/ld-powerpc/tlsexenors.d b/ld/testsuite/ld-powerpc/tlsexenors.d
new file mode 100644
index 0000000..09c9705
--- /dev/null
+++ b/ld/testsuite/ld-powerpc/tlsexenors.d
@@ -0,0 +1,106 @@
+#source: tls.s
+#as: -a64
+#ld: --no-tls-optimize tmpdir/libtlslib.so
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*
+
+Disassembly of section \.text:
+
+.* <.*plt_call\.__tls_get_addr(|_opt)>:
+.*:	(e8 03 00 00|00 00 03 e8) 	ld      r0,0\(r3\)
+.*:	(e9 83 00 08|08 00 83 e9) 	ld      r12,8\(r3\)
+.*:	(2c 20 00 00|00 00 20 2c) 	cmpdi   r0,0
+.*:	(7c 60 1b 78|78 1b 60 7c) 	mr      r0,r3
+.*:	(7c 6c 6a 14|14 6a 6c 7c) 	add     r3,r12,r13
+.*:	(4d 82 00 20|20 00 82 4d) 	beqlr *
+.*:	(7c 03 03 78|78 03 03 7c) 	mr      r3,r0
+.*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
+.*:	(f8 01 00 10|10 00 01 f8) 	std     r0,16\(r1\)
+.*:	(f8 81 ff b8|b8 ff 81 f8) 	std     r4,-72\(r1\)
+.*:	(f8 a1 ff c0|c0 ff a1 f8) 	std     r5,-64\(r1\)
+.*:	(f8 c1 ff c8|c8 ff c1 f8) 	std     r6,-56\(r1\)
+.*:	(f8 e1 ff d0|d0 ff e1 f8) 	std     r7,-48\(r1\)
+.*:	(f9 01 ff d8|d8 ff 01 f9) 	std     r8,-40\(r1\)
+.*:	(f9 21 ff e0|e0 ff 21 f9) 	std     r9,-32\(r1\)
+.*:	(f9 41 ff e8|e8 ff 41 f9) 	std     r10,-24\(r1\)
+.*:	(f9 61 ff f0|f0 ff 61 f9) 	std     r11,-16\(r1\)
+.*:	(f8 21 ff 81|81 ff 21 f8) 	stdu    r1,-128\(r1\)
+.*:	(f8 41 00 28|28 00 41 f8) 	std     r2,40\(r1\)
+.*:	(e9 82 80 88|88 80 82 e9) 	ld      r12,-32632\(r2\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(e8 42 80 90|90 80 42 e8) 	ld      r2,-32624\(r2\)
+.*:	(4e 80 04 21|21 04 80 4e) 	bctrl
+.*:	(e8 41 00 28|28 00 41 e8) 	ld      r2,40\(r1\)
+.*:	(e8 81 00 38|38 00 81 e8) 	ld      r4,56\(r1\)
+.*:	(e8 a1 00 40|40 00 a1 e8) 	ld      r5,64\(r1\)
+.*:	(e8 c1 00 48|48 00 c1 e8) 	ld      r6,72\(r1\)
+.*:	(e8 e1 00 50|50 00 e1 e8) 	ld      r7,80\(r1\)
+.*:	(e9 01 00 58|58 00 01 e9) 	ld      r8,88\(r1\)
+.*:	(e9 21 00 60|60 00 21 e9) 	ld      r9,96\(r1\)
+.*:	(e9 41 00 68|68 00 41 e9) 	ld      r10,104\(r1\)
+.*:	(e9 61 00 70|70 00 61 e9) 	ld      r11,112\(r1\)
+.*:	(38 21 00 80|80 00 21 38) 	addi    r1,r1,128
+.*:	(e8 01 00 10|10 00 01 e8) 	ld      r0,16\(r1\)
+.*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(4e 80 00 20|20 00 80 4e) 	blr
+
+.* <\._start>:
+.*:	(38 62 80 20|20 80 62 38) 	addi    r3,r2,-32736
+.*:	(4b ff ff 6d|6d ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 62 80 30|30 80 62 38) 	addi    r3,r2,-32720
+.*:	(4b ff ff 61|61 ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 62 80 48|48 80 62 38) 	addi    r3,r2,-32696
+.*:	(4b ff ff 55|55 ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 62 80 60|60 80 62 38) 	addi    r3,r2,-32672
+.*:	(4b ff ff 49|49 ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(39 23 80 40|40 80 23 39) 	addi    r9,r3,-32704
+.*:	(3d 23 00 00|00 00 23 3d) 	addis   r9,r3,0
+.*:	(81 49 80 48|48 80 49 81) 	lwz     r10,-32696\(r9\)
+.*:	(e9 22 80 40|40 80 22 e9) 	ld      r9,-32704\(r2\)
+.*:	(7d 49 18 2a|2a 18 49 7d) 	ldx     r10,r9,r3
+.*:	(e9 22 80 58|58 80 22 e9) 	ld      r9,-32680\(r2\)
+.*:	(7d 49 6a 2e|2e 6a 49 7d) 	lhzx    r10,r9,r13
+.*:	(89 4d 90 60|60 90 4d 89) 	lbz     r10,-28576\(r13\)
+.*:	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
+.*:	(99 49 90 68|68 90 49 99) 	stb     r10,-28568\(r9\)
+.*:	(38 62 80 08|08 80 62 38) 	addi    r3,r2,-32760
+.*:	(4b ff ff 15|15 ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(38 62 80 60|60 80 62 38) 	addi    r3,r2,-32672
+.*:	(4b ff ff 09|09 ff ff 4b) 	bl      .*
+.*:	(60 00 00 00|00 00 00 60) 	nop
+.*:	(f9 43 80 08|08 80 43 f9) 	std     r10,-32760\(r3\)
+.*:	(3d 23 00 00|00 00 23 3d) 	addis   r9,r3,0
+.*:	(91 49 80 10|10 80 49 91) 	stw     r10,-32752\(r9\)
+.*:	(e9 22 80 18|18 80 22 e9) 	ld      r9,-32744\(r2\)
+.*:	(7d 49 19 2a|2a 19 49 7d) 	stdx    r10,r9,r3
+.*:	(e9 22 80 58|58 80 22 e9) 	ld      r9,-32680\(r2\)
+.*:	(7d 49 6b 2e|2e 6b 49 7d) 	sthx    r10,r9,r13
+.*:	(e9 4d 90 2a|2a 90 4d e9) 	lwa     r10,-28632\(r13\)
+.*:	(3d 2d 00 00|00 00 2d 3d) 	addis   r9,r13,0
+.*:	(a9 49 90 30|30 90 49 a9) 	lha     r10,-28624\(r9\)
+.*:	(00 00 00 00|78 02 01 00) 	.*
+.*:	(00 01 02 78|00 00 00 00) 	.*
+
+.* <__glink_PLTresolve>:
+.*:	(7d 88 02 a6|a6 02 88 7d) 	mflr    r12
+.*:	(42 9f 00 05|05 00 9f 42) 	bcl     .*
+.*:	(7d 68 02 a6|a6 02 68 7d) 	mflr    r11
+.*:	(e8 4b ff f0|f0 ff 4b e8) 	ld      r2,-16\(r11\)
+.*:	(7d 88 03 a6|a6 03 88 7d) 	mtlr    r12
+.*:	(7d 62 5a 14|14 5a 62 7d) 	add     r11,r2,r11
+.*:	(e9 8b 00 00|00 00 8b e9) 	ld      r12,0\(r11\)
+.*:	(e8 4b 00 08|08 00 4b e8) 	ld      r2,8\(r11\)
+.*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
+.*:	(e9 6b 00 10|10 00 6b e9) 	ld      r11,16\(r11\)
+.*:	(4e 80 04 20|20 04 80 4e) 	bctr
+
+.* <__tls_get_addr_opt@plt>:
+.*:	(38 00 00 00|00 00 00 38) 	li      r0,0
+.*:	(4b ff ff d0|d0 ff ff 4b) 	b       .* <__glink_PLTresolve>