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| author | Alan Modra <amodra@gmail.com> | 2020-09-26 15:10:09 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2020-09-26 19:03:02 +0930 |
| commit | 3cd7c7d7ef38ec5dc0a0c137c47d9ad0fc9e2e5f (patch) | |
| tree | 1b9ed3050e4eb9b5338592f702929c91e44be19e /ld/testsuite/ld-powerpc/elfv2so.d | |
| parent | 0be2fe677c53c6d363a40ae3612d4490ba377e02 (diff) | |
| download | gdb-3cd7c7d7ef38ec5dc0a0c137c47d9ad0fc9e2e5f.zip gdb-3cd7c7d7ef38ec5dc0a0c137c47d9ad0fc9e2e5f.tar.gz gdb-3cd7c7d7ef38ec5dc0a0c137c47d9ad0fc9e2e5f.tar.bz2 | |
PPC64_OPT_LOCALENTRY is incompatible with tail calls
The save of r2 in __glink_PLTresolve is the culprit. Remove it,
unless we know we need it for --plt-localentry. --plt-localentry
should not be used with power10 pc-relative code that makes tail
calls.
The patch also removes use of r2 as a scratch reg in the ELFv2
__glink_PLTresolve. Using r2 isn't a problem, this is just reducing
the number of scratch regs.
bfd/
* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Depend on has_plt_localentry0.
(LD_R0_0R11, ADD_R11_R0_R11): Define.
(ppc64_elf_tls_setup): Disable params->plt_localentry0 when power10
code detected.
(ppc64_elf_size_stubs): Update __glink_PLTresolve eh_frame.
(ppc64_elf_build_stubs): Move r2 save to start of __glink_PLTresolve,
and only emit for has_plt_localentry0. Don't use r2 in the stub.
ld/
* testsuite/ld-powerpc/elfv2so.d,
* testsuite/ld-powerpc/notoc2.d,
* testsuite/ld-powerpc/tlsdesc.wf,
* testsuite/ld-powerpc/tlsdesc2.d,
* testsuite/ld-powerpc/tlsdesc2.wf,
* testsuite/ld-powerpc/tlsopt5.d,
* testsuite/ld-powerpc/tlsopt5.wf,
* testsuite/ld-powerpc/tlsopt6.d,
* testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.
Diffstat (limited to 'ld/testsuite/ld-powerpc/elfv2so.d')
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 0162bd0..4018f05 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -74,12 +74,11 @@ Disassembly of section \.text: .*: (7c 08 02 a6|a6 02 08 7c) mflr r0 .*: (42 9f 00 05|05 00 9f 42) bcl .* .*: (7d 68 02 a6|a6 02 68 7d) mflr r11 -.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\) -.*: (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\) .*: (7c 08 03 a6|a6 03 08 7c) mtlr r0 +.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\) .*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12 -.*: (7d 62 5a 14|14 5a 62 7d) add r11,r2,r11 -.*: (38 0c ff d0|d0 ff 0c 38) addi r0,r12,-48 +.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11 +.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44 .*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\) .*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2 .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 @@ -87,16 +86,16 @@ Disassembly of section \.text: .*: (4e 80 04 20|20 04 80 4e) bctr .* <f5@plt>: -.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve> +.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve> .* <f3@plt>: -.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve> +.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve> .* <f2@plt>: -.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve> +.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve> .* <f4@plt>: -.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve> +.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve> .* <f1@plt>: -.*: (4b ff ff b8|b8 ff ff 4b) b .* <__glink_PLTresolve> +.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve> |