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| author | Alan Modra <amodra@gmail.com> | 2019-04-30 16:31:01 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2019-04-30 22:09:54 +0930 |
| commit | 066f4018ae7822d81cb6747fd9494e5dd63bfecf (patch) | |
| tree | d840b2ca4e38182f327d99d34a053d5b73a7b6a4 /ld/testsuite/ld-powerpc/elfv2so.d | |
| parent | 8107ddcea1da07f1c4e902c17f045684beb78079 (diff) | |
| download | gdb-066f4018ae7822d81cb6747fd9494e5dd63bfecf.zip gdb-066f4018ae7822d81cb6747fd9494e5dd63bfecf.tar.gz gdb-066f4018ae7822d81cb6747fd9494e5dd63bfecf.tar.bz2 | |
PowerPC64 GOT indirect to GOT relative optimisation
This implements an optimisation that converts sequences like
addis r9,r2,sym@got@ha
ld r3,sym@got@l(r9)
to
addis r9,r2,sym@toc@ha
addi r3,r9,sym@toc@l
when "sym" is locally defined and can't be overridden.
bfd/
* elf64-ppc.c (struct ppc64_elf_obj_tdata): Add has_gotrel.
(struct _ppc64_elf_section_data): Likewise.
(ppc64_elf_check_relocs): Set above fields.
(ppc64_elf_edit_toc): Add a pass over GOT relocs.
(ppc64_elf_relocate_section): Edit GOT indirect to GOT relative
when possible.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/tocopt.d: Update.
* testsuite/ld-powerpc/tocopt.s: Update.
* testsuite/ld-powerpc/tocopt5.d: Update.
* testsuite/ld-powerpc/tocopt5.s: Update.
* testsuite/ld-powerpc/tocopt7.d: Update.
* testsuite/ld-powerpc/tocopt7.s: Update.
* testsuite/ld-powerpc/tocopt8.d: Update.
* testsuite/ld-powerpc/tocopt8.s: Update.
Diffstat (limited to 'ld/testsuite/ld-powerpc/elfv2so.d')
| -rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 0853f8a..081eb49 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -9,35 +9,35 @@ Disassembly of section \.text: .* <.*\.plt_call\.f4>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) +.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f3>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) +.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f5>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\) +.*: (e9 82 80 20|20 80 82 e9) ld r12,-32736\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f1>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\) +.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. .* <.*\.plt_call\.f2>: .*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\) -.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\) +.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\) .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (4e 80 04 20|20 04 80 4e) bctr \.\.\. @@ -52,7 +52,7 @@ Disassembly of section \.text: .*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\) .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2> .*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\) -.*: (e8 62 80 10|10 80 62 e8) ld r3,-32752\(r2\) +.*: (38 62 80 48|48 80 62 38) addi r3,r2,-32696 .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3> .*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\) .*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4> |