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| author | Daniel Jacobowitz <drow@false.org> | 2006-11-13 21:18:36 +0000 |
|---|---|---|
| committer | Daniel Jacobowitz <drow@false.org> | 2006-11-13 21:18:36 +0000 |
| commit | f53e1b4030585ec2db270b8769d69c6b320ae348 (patch) | |
| tree | f632f88727775e0d03b9e01ead421e918ef279c6 /ld/testsuite/ld-arm/tls-app.d | |
| parent | d504ffc8519a0f1674715a8d55975c762c3ca1df (diff) | |
| download | gdb-f53e1b4030585ec2db270b8769d69c6b320ae348.zip gdb-f53e1b4030585ec2db270b8769d69c6b320ae348.tar.gz gdb-f53e1b4030585ec2db270b8769d69c6b320ae348.tar.bz2 | |
* ld-arm/arm-dyn.ld, ld-arm/arm-lib.ld: Remove .stack.
* ld-arm/armthumb-lib.d, ld-arm/mixed-app.d, ld-arm/mixed-lib.d:
Allow smaller section gap.
* ld-arm/armthumb-lib.sym, ld-arm/mixed-lib.sym: Reorder. Remove
_stack.
* ld-arm/mixed-app.sym: Remove _stack.
* ld-arm/tls-app.d: Update start address.
Diffstat (limited to 'ld/testsuite/ld-arm/tls-app.d')
| -rw-r--r-- | ld/testsuite/ld-arm/tls-app.d | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/ld/testsuite/ld-arm/tls-app.d b/ld/testsuite/ld-arm/tls-app.d index 67e5de4..c1d61ab 100644 --- a/ld/testsuite/ld-arm/tls-app.d +++ b/ld/testsuite/ld-arm/tls-app.d @@ -2,17 +2,17 @@ .*: file format elf32-.*arm architecture: arm, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED -start address 0x00008220 +start address 0x00008204 Disassembly of section .text: -00008220 <foo>: - 8220: e1a00000 nop \(mov r0,r0\) - 8224: e1a00000 nop \(mov r0,r0\) - 8228: e1a0f00e mov pc, lr - 822c: 000080bc streqh r8, \[r0\], -ip - 8230: 000080b4 streqh r8, \[r0\], -r4 - 8234: 000080ac andeq r8, r0, ip, lsr #1 - 8238: 00000004 andeq r0, r0, r4 - 823c: 000080c4 andeq r8, r0, r4, asr #1 - 8240: 00000014 andeq r0, r0, r4, lsl r0 +00008204 <foo>: + 8204: e1a00000 nop \(mov r0,r0\) + 8208: e1a00000 nop \(mov r0,r0\) + 820c: e1a0f00e mov pc, lr + 8210: 000080bc streqh r8, \[r0\], -ip + 8214: 000080b4 streqh r8, \[r0\], -r4 + 8218: 000080ac andeq r8, r0, ip, lsr #1 + 821c: 00000004 andeq r0, r0, r4 + 8220: 000080c4 andeq r8, r0, r4, asr #1 + 8224: 00000014 andeq r0, r0, r4, lsl r0 |