ld/

    * emultempl/armelf.em (fix_cortex_a8): New.
    (arm_elf_before_allocation): Call bfd_elf32_arm_set_cortex_a8_fix.
    (arm_elf_create_output_section_statements): Add fix_cortex_a8 to
    bfd_elf32_arm_set_target_relocs.
    (OPTION_FIX_CORTEX_A8, OPTION_NO_FIX_CORTEX_A8): New.
    (PARSE_AND_LIST_LONGOPTS): Add [no-]fix-cortex-a8 options.
    (PARSE_AND_LIST_OPTIONS): Add [no-]fix-cortex-a8 options.
    (PARSE_AND_LIST_ARGS_CASES): Handle OPTION_[NO_]FIX_CORTEX_A8.
    * ld.texinfo (--[no-]fix-cortex-a8): Briefly document new options.

    bfd/
    * elf32-arm.c (THUMB16_BCOND_INSN, THUMB32_INSN, THUMB32_B_INSN):
    New macros.
    (elf32_arm_stub_a8_veneer_b_cond, elf32_arm_stub_a8_veneer_b)
    (elf32_arm_stub_a8_veneer_blx): New stub sequences.
    (elf32_arm_stub_type): Add arm_stub_a8_veneer_b_cond,
    arm_stub_a8_veneer_b and arm_stub_a8_veneer_blx.
    (elf32_arm_stub_hash_entry): Add target_addend, orig_insn fields.
    (a8_erratum_fix, a8_erratum_reloc): New structs.
    (elf32_arm_link_hash_table): Add a8_erratum_fixes,
    num_a8_erratum_fixes, fix_cortex_a8 fields.
    (elf32_arm_link_hash_table_create): Zero fix_cortex_a8.
    (elf32_arm_add_stub): Split into two parts, creating...
    (elf32_arm_create_or_find_stub_sec): New function.
    (elf32_arm_final_link_relocate): Add forward declaration.
    (arm_build_one_stub): Add support for THUMB32_TYPE, Thumb-2
    relocations, multiple relocations per stub.
    (find_stub_size_and_template): New (using parts of
    arm_size_one_stub).
    (arm_size_one_stub): Use find_stub_size_and_template.
    (a8_reloc_compare): New.
    (find_thumb_glue): Add forward declaration.
    (cortex_a8_erratum_scan): New.
    (elf32_arm_size_stubs): Add Cortex-A8 erratum workaround support.
    (bfd_elf32_arm_set_cortex_a8_fix): New.
    (bfd_elf32_arm_set_target_relocs): Add fix_cortex_a8 argument.
    (arm_map_one_stub): Add THUMB32_TYPE support.
    (a8_branch_to_stub_data): New.
    (make_branch_to_a8_stub): New.
    (elf32_arm_write_section): Add Cortex-A8 erratum workaround support.
    * bfd-in.h (bfd_elf32_arm_set_cortex_a8_fix): New.
    (bfd_elf32_arm_set_target_relocs): Add argument for controlling
    Cortex-A8 erratum workaround.
    * bfd-in2.h: Regenerate.

    ld/testsuite/
    * ld-arm/cortex-a8-arm-target.s: New.
    * ld-arm/cortex-a8-thumb-target.s: New.
    * ld-arm/cortex-a8-fix-b-rel.s: New.
    * ld-arm/cortex-a8-fix-b-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-b-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-b.s: New.
    * ld-arm/cortex-a8-fix-b.d: New.
    * ld-arm/cortex-a8-fix-bl-rel.s: New.
    * ld-arm/cortex-a8-fix-bl-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-bl-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-bl.s: New.
    * ld-arm/cortex-a8-fix-bl.d: New.
    * ld-arm/cortex-a8-fix-bcc-rel.s: New.
    * ld-arm/cortex-a8-fix-bcc-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-bcc.s: New.
    * ld-arm/cortex-a8-fix-bcc.d: New.
    * ld-arm/cortex-a8-fix-blx-rel.s: New.
    * ld-arm/cortex-a8-fix-blx-rel-arm.d: New.
    * ld-arm/cortex-a8-fix-blx-rel-thumb.d: New.
    * ld-arm/cortex-a8-fix-blx.s: New.
    * ld-arm/cortex-a8-fix-blx.d: New.
    * ld-arm/arm-elf.exp: Add new tests.

1 files changed, 79 insertions, 0 deletions

diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
new file mode 100644
index 0000000..4805256
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <armfn>:
+    8f00:	e1a02413 	lsl	r2, r3, r4
+    8f04:	e12fff1e 	bx	lr
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <armfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <armfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <armfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <armfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <armfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <armfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <armfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <armfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <armfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <armfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <armfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <armfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <armfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <armfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <armfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <armfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <armfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <armfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <armfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <armfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <armfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <armfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <armfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <armfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <armfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <armfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <armfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <armfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <armfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <armfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <armfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <armfn>